target/avr: Add instruction translation - Bit and Bit-test Instructions
commit5718cef05a0fe306646dd0481eb6ccf4fef3979e
authorMichael Rolnik <mrolnik@gmail.com>
Fri, 24 Jan 2020 00:51:13 +0000 (24 01:51 +0100)
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>
Sat, 11 Jul 2020 09:02:05 +0000 (11 11:02 +0200)
tree96b88602f3de54c4fd5f9b3b60e3ff74161c23fb
parent9732b024f79217fbc685895791c4897d14096ef3
target/avr: Add instruction translation - Bit and Bit-test Instructions

This includes:
    - LSR, ROR
    - ASR
    - SWAP
    - SBI, CBI
    - BST, BLD
    - BSET, BCLR

Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Message-Id: <20200705140315.260514-15-huth@tuxfamily.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
target/avr/insn.decode
target/avr/translate.c