| commit | 53673d0ff4a45964322bd6bfe904eff7dc96197d | |
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | |
| Mon, 14 Dec 2020 00:32:15 +0000 (14 01:32 +0100) | ||
| committer | Laurent Vivier <laurent@vivier.eu> | |
| Thu, 17 Dec 2020 09:34:59 +0000 (17 10:34 +0100) | ||
| tree | 7905807b4e36d3bf790102636b98bcac9508886c | treesnapshot (tar.gz zip) |
| parent | 9ea313ba5d2071f6c3bf0897a7876c7c527964d6 | commitdiff |
linux-user: Add support for MIPS Loongson 2F/3A
Userland ELF binaries using Loongson SIMD instructions have the
HWCAP_LOONGSON_MMI bit set [1].
Binaries compiled for Loongson 3A [2] have the HWCAP_LOONGSON_EXT
bit set for the LQ / SQ instructions.
[1] commit 8e2d5831e4b ("target/mips: Legalize Loongson insn flags")
[2] commit af868995e1b ("target/mips: Add Loongson-3 CPU definition")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201214003215.344522-7-f4bug@amsat.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Userland ELF binaries using Loongson SIMD instructions have the
HWCAP_LOONGSON_MMI bit set [1].
Binaries compiled for Loongson 3A [2] have the HWCAP_LOONGSON_EXT
bit set for the LQ / SQ instructions.
[1] commit 8e2d5831e4b ("target/mips: Legalize Loongson insn flags")
[2] commit af868995e1b ("target/mips: Add Loongson-3 CPU definition")
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201214003215.344522-7-f4bug@amsat.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| linux-user/elfload.c | diffblobblamehistory |