| commit | 52a44ad2b92ba4cd81c2b271cd5e4a2d820e91fc | |
| author | Chenyi Qiang <chenyi.qiang@intel.com> | |
| Fri, 5 Feb 2021 08:33:25 +0000 (5 16:33 +0800) | ||
| committer | Paolo Bonzini <pbonzini@redhat.com> | |
| Mon, 8 Feb 2021 14:15:32 +0000 (8 15:15 +0100) | ||
| tree | b7e98ea6f6ba0322c30d284ef17aa85fc654b84d | treesnapshot (tar.gz zip) |
| parent | 6aa4228bd68cb251ccb5f802c015b494c6a10f19 | commitdiff |
target/i386: Expose VMX entry/exit load pkrs control bits
Expose the VMX exit/entry load pkrs control bits in
VMX_TRUE_EXIT_CTLS/VMX_TRUE_ENTRY_CTLS MSRs to guest, which supports the
PKS in nested VM.
Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com>
Message-Id: <20210205083325.13880-3-chenyi.qiang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Expose the VMX exit/entry load pkrs control bits in
VMX_TRUE_EXIT_CTLS/VMX_TRUE_ENTRY_CTLS MSRs to guest, which supports the
PKS in nested VM.
Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com>
Message-Id: <20210205083325.13880-3-chenyi.qiang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| target/i386/cpu.c | diffblobblamehistory | |
| target/i386/cpu.h | diffblobblamehistory |