| commit | 5235993f98f2842253b59d3ce786290b4644ca51 | |
| author | Philippe Mathieu-Daudé <philmd@linaro.org> | |
| Fri, 9 Feb 2024 07:49:43 +0000 (9 08:49 +0100) | ||
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | |
| Thu, 15 Feb 2024 14:53:12 +0000 (15 15:53 +0100) | ||
| tree | 38400f4ff0f982e6cbd43db95a97bc741f27bf96 | treesnapshot (tar.gz zip) |
| parent | addd0c28741df1a503a97a45e9dc4976ea8e0b9a | commitdiff |
target/mips: Remove CPUMIPSState::CP0_SAAR[2] field
Remove the unused CP0_SAAR[2] registers.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240209090513.9401-8-philmd@linaro.org>
Remove the unused CP0_SAAR[2] registers.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240209090513.9401-8-philmd@linaro.org>
| target/mips/cpu.h | diffblobblamehistory | |
| target/mips/sysemu/machine.c | diffblobblamehistory |