| commit | 5204ea79ea739b557f47fc4db96c94edcb33a5d6 | |
| author | Leon Alrae <leon.alrae@imgtec.com> | |
| Thu, 11 Sep 2014 15:28:17 +0000 (11 16:28 +0100) | ||
| committer | Leon Alrae <leon.alrae@imgtec.com> | |
| Fri, 12 Jun 2015 08:05:31 +0000 (12 09:05 +0100) | ||
| tree | 6b439e0077f4624a23b47ec81770e4debda4cf9c | treesnapshot (tar.gz zip) |
| parent | e117f52636d04502fab28bd3abe93347c29f39a5 | commitdiff |
target-mips: add MTHC0 and MFHC0 instructions
Implement MTHC0 and MFHC0 instructions. In MIPS32 they are used to access
upper word of extended to 64-bits CP0 registers.
In MIPS64, when CP0 destination register specified is the EntryLo0 or
EntryLo1, bits 1:0 of the GPR appear at bits 31:30 of EntryLo0 or
EntryLo1. This is to compensate for RI and XI, which were shifted to bits
63:62 by MTC0 to EntryLo0 or EntryLo1. Therefore creating separate
functions for EntryLo0 and EntryLo1.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Implement MTHC0 and MFHC0 instructions. In MIPS32 they are used to access
upper word of extended to 64-bits CP0 registers.
In MIPS64, when CP0 destination register specified is the EntryLo0 or
EntryLo1, bits 1:0 of the GPR appear at bits 31:30 of EntryLo0 or
EntryLo1. This is to compensate for RI and XI, which were shifted to bits
63:62 by MTC0 to EntryLo0 or EntryLo1. Therefore creating separate
functions for EntryLo0 and EntryLo1.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
| disas/mips.c | diffblobblamehistory | |
| target-mips/cpu.h | diffblobblamehistory | |
| target-mips/translate.c | diffblobblamehistory |