| commit | 51cb228a1d1c0e325b4e7dea0bfb3140d6d11422 | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 10 Sep 2020 17:38:54 +0000 (10 18:38 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 1 Oct 2020 14:31:00 +0000 (1 15:31 +0100) | ||
| tree | 8e4ce18682c9447df73be04a2e2b5104a7b96f38 | treesnapshot (tar.gz zip) |
| parent | d20c3ebda2972255e67c0a07368ac37f37a16c04 | commitdiff |
target/arm: Add ID register values for Cortex-M0
Give the Cortex-M0 ID register values corresponding to its
implemented behaviour. These will not be guest-visible but will be
used to govern the behaviour of QEMU's emulation. We use the same
values that the Cortex-M3 does.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200910173855.4068-5-peter.maydell@linaro.org
Give the Cortex-M0 ID register values corresponding to its
implemented behaviour. These will not be guest-visible but will be
used to govern the behaviour of QEMU's emulation. We use the same
values that the Cortex-M3 does.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200910173855.4068-5-peter.maydell@linaro.org
| target/arm/cpu_tcg.c | diffblobblamehistory |