| commit | 4c70e32f05fc7903185a4e9d01987ee3de2052f6 | |
| author | Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> | |
| Tue, 12 May 2020 14:54:46 +0000 (12 20:24 +0530) | ||
| committer | Jason Wang <jasowang@redhat.com> | |
| Thu, 18 Jun 2020 13:05:51 +0000 (18 21:05 +0800) | ||
| tree | 63eced1940fb741fc2bfb4778bd6c58b66023549 | treesnapshot (tar.gz zip) |
| parent | 86a29d4c72e42130e08bae3335c25575d4af0b4d | commitdiff |
net: cadence_gem: Define access permission for interrupt registers
Q1 to Q7 ISR's are clear-on-read, IER/IDR registers
are write-only, mask reg are read-only.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
Q1 to Q7 ISR's are clear-on-read, IER/IDR registers
are write-only, mask reg are read-only.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
| hw/net/cadence_gem.c | diffblobblamehistory |