| commit | 4836b45510aa84da52a29bf5a23794f71a29d98b | |
| author | Cédric Le Goater <clg@kaod.org> | |
| Wed, 6 Mar 2019 08:50:14 +0000 (6 09:50 +0100) | ||
| committer | David Gibson <david@gibson.dropbear.id.au> | |
| Tue, 12 Mar 2019 03:33:04 +0000 (12 14:33 +1100) | ||
| tree | 83f68cd4e861d20407de9389c742de1e0416db68 | treesnapshot (tar.gz zip) |
| parent | d8e4aad533573b6237b5da6ceb06027fc4eac9c7 | commitdiff |
ppc/xive: activate HV support
The NSR register of the HV ring has a different, although similar, bit
layout. TM_QW3_NSR_HE_PHYS bit should now be raised when the
Hypervisor interrupt line is signaled. Other bits TM_QW3_NSR_HE_POOL
and TM_QW3_NSR_HE_LSI are not modeled. LSI are for special interrupts
reserved for HW bringup and the POOL bit is used when signaling a
group of VPs. This is not currently implemented in Linux but it is in
pHyp.
The most important special commands on the HV TIMA page are added to
let the core manage interrupts : acking and changing the CPU priority.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20190306085032.15744-10-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
The NSR register of the HV ring has a different, although similar, bit
layout. TM_QW3_NSR_HE_PHYS bit should now be raised when the
Hypervisor interrupt line is signaled. Other bits TM_QW3_NSR_HE_POOL
and TM_QW3_NSR_HE_LSI are not modeled. LSI are for special interrupts
reserved for HW bringup and the POOL bit is used when signaling a
group of VPs. This is not currently implemented in Linux but it is in
pHyp.
The most important special commands on the HV TIMA page are added to
let the core manage interrupts : acking and changing the CPU priority.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20190306085032.15744-10-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| hw/intc/xive.c | diffblobblamehistory |