| commit | 3b27430177498a1728b6765c70b455900f93d73a | |
| author | Leonid Bloch <leonid.bloch@ravellosystems.com> | |
| Wed, 11 Nov 2015 13:52:46 +0000 (11 15:52 +0200) | ||
| committer | Jason Wang <jasowang@redhat.com> | |
| Thu, 12 Nov 2015 07:26:54 +0000 (12 15:26 +0800) | ||
| tree | c5a9e14dbf91d90b0d27f6540deb89a92ec2f8ec | treesnapshot (tar.gz zip) |
| parent | 4aeea330f022f45d0dabff6090ecbb98755c2116 | commitdiff |
e1000: Implementing various counters
This implements the following Statistic registers (various counters)
according to Intel's specs:
TSCTC GOTCL GOTCH GORCL GORCH MPRC BPRC RUC ROC
BPTC MPTC PTC... PRC...
PLEASE NOTE: these registers will not be active, nor will migrate, until
a compatibility flag will be set (in the next patch in this series).
Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
This implements the following Statistic registers (various counters)
according to Intel's specs:
TSCTC GOTCL GOTCH GORCL GORCH MPRC BPRC RUC ROC
BPTC MPTC PTC... PRC...
PLEASE NOTE: these registers will not be active, nor will migrate, until
a compatibility flag will be set (in the next patch in this series).
Signed-off-by: Leonid Bloch <leonid.bloch@ravellosystems.com>
Signed-off-by: Dmitry Fleytman <dmitry.fleytman@ravellosystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
| hw/net/e1000.c | diffblobblamehistory |