| commit | 388765a05bde86de9d9b66348afed6551c58f091 | |
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | |
| Mon, 14 Dec 2020 00:32:12 +0000 (14 01:32 +0100) | ||
| committer | Laurent Vivier <laurent@vivier.eu> | |
| Thu, 17 Dec 2020 09:34:59 +0000 (17 10:34 +0100) | ||
| tree | 899871a522f0ccdb60a047667c348491e06df027 | treesnapshot (tar.gz zip) |
| parent | 7d9a3d96f57dfed441622ebb9d1516473d51f919 | commitdiff |
linux-user/elfload: Introduce MIPS GET_FEATURE_REG_SET() macro
ISA features are usually denoted in read-only bits from
CPU registers. Add the GET_FEATURE_REG_SET() macro which
checks if a CPU register has bits set.
Use the macro to check for MSA (which sets the MSAP bit of
the Config3 register when the ASE implementation is present).
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201214003215.344522-4-f4bug@amsat.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
ISA features are usually denoted in read-only bits from
CPU registers. Add the GET_FEATURE_REG_SET() macro which
checks if a CPU register has bits set.
Use the macro to check for MSA (which sets the MSAP bit of
the Config3 register when the ASE implementation is present).
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201214003215.344522-4-f4bug@amsat.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
| linux-user/elfload.c | diffblobblamehistory |