| commit | 3278aa49d559ca191ff10735d363bd367d81fabf | |
| author | Giuseppe Musacchio <thatlemon@gmail.com> | |
| Thu, 12 Nov 2020 23:01:27 +0000 (13 00:01 +0100) | ||
| committer | David Gibson <david@gibson.dropbear.id.au> | |
| Mon, 14 Dec 2020 04:53:26 +0000 (14 15:53 +1100) | ||
| tree | 5d14b641f37e402d94cf6557f3af670a70fbb7cc | treesnapshot (tar.gz zip) |
| parent | b2bd5b20fd1854cdbfee87553855163081a6c531 | commitdiff |
ppc/translate: Fix unordered f64/f128 comparisons
According to the PowerISA v3.1 reference, Table 68 "Actions for xscmpudp
- Part 1: Compare Unordered", whenever one of the two operands is a NaN
the SO bit is set while the other three bits are cleared.
Apply the same change to xscmpuqp.
The respective ordered counterparts are unaffected.
Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com>
Message-Id: <20201112230130.65262-2-thatlemon@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
According to the PowerISA v3.1 reference, Table 68 "Actions for xscmpudp
- Part 1: Compare Unordered", whenever one of the two operands is a NaN
the SO bit is set while the other three bits are cleared.
Apply the same change to xscmpuqp.
The respective ordered counterparts are unaffected.
Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com>
Message-Id: <20201112230130.65262-2-thatlemon@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| target/ppc/fpu_helper.c | diffblobblamehistory |