target/arm: Handle SFPA and FPCA bits in reads and writes of CONTROL
commit2e1c5bcd32014c9ede1b604ae6c2c653de17fc53
authorPeter Maydell <peter.maydell@linaro.org>
Mon, 29 Apr 2019 16:35:59 +0000 (29 17:35 +0100)
committerPeter Maydell <peter.maydell@linaro.org>
Mon, 29 Apr 2019 16:35:59 +0000 (29 17:35 +0100)
tree9a254718cb81c34ee3af2c2dd7b17af37c8c985e
parent1702071302934af77a072b7ee7c5eadc45b37573
target/arm: Handle SFPA and FPCA bits in reads and writes of CONTROL

The M-profile CONTROL register has two bits -- SFPA and FPCA --
which relate to floating-point support, and should be RES0 otherwise.
Handle them correctly in the MSR/MRS register access code.
Neither is banked between security states, so they are stored
in v7m.control[M_REG_S] regardless of current security state.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190416125744.27770-9-peter.maydell@linaro.org
target/arm/helper.c