| commit | 2c628d98989fa224dc3c07033ba4d89562a9bb5f | |
| author | Peter Crosthwaite <peter.crosthwaite@xilinx.com> | |
| Mon, 6 Jan 2014 10:16:39 +0000 (6 10:16 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 7 Jan 2014 19:18:06 +0000 (7 19:18 +0000) | ||
| tree | 10712af9673866c6ff522d217497c97e7aa3e182 | treesnapshot (tar.gz zip) |
| parent | a24234cad03d70612e30494f21062fcee5eb9f0e | commitdiff |
char/cadence_uart: Define Missing SR/ISR fields
Some (interrupt) status register bits relating to the TxFIFO path were
not defined. Define them. This prepares support for proper Tx data path
flow control.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 2068b963f0af8cc834c353944e9fa816d950b163.1388626249.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Some (interrupt) status register bits relating to the TxFIFO path were
not defined. Define them. This prepares support for proper Tx data path
flow control.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 2068b963f0af8cc834c353944e9fa816d950b163.1388626249.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| hw/char/cadence_uart.c | diffblobblamehistory |