| commit | 2af3da91839c04a5d73643b4eacce4cd93b9d428 | |
| author | Max Filippov <jcmvbkbc@gmail.com> | |
| Mon, 5 Sep 2011 23:55:33 +0000 (6 03:55 +0400) | ||
| committer | Blue Swirl <blauwirbel@gmail.com> | |
| Sat, 10 Sep 2011 16:57:37 +0000 (10 16:57 +0000) | ||
| tree | b7351a28a6060aaf9f70d7688569f9fa74f74116 | treesnapshot (tar.gz zip) |
| parent | 5da4a6a8c5271234fdc2ab53b80cf7a23952849b | commitdiff |
target-xtensa: add special and user registers
Special Registers hold the majority of the state added to the processor
by the options. See ISA, 5.3 for details.
User Registers hold state added in support of designer's TIE and in some
cases of options that Tensilica provides. See ISA, 5.4 for details.
Only registers mapped in sregnames or uregnames are considered valid.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Special Registers hold the majority of the state added to the processor
by the options. See ISA, 5.3 for details.
User Registers hold state added in support of designer's TIE and in some
cases of options that Tensilica provides. See ISA, 5.4 for details.
Only registers mapped in sregnames or uregnames are considered valid.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
| target-xtensa/cpu.h | diffblobblamehistory | |
| target-xtensa/translate.c | diffblobblamehistory |