| commit | 2a99ab2b3545133961de034df27e24f4c22e3707 | |
| author | Richard Henderson <richard.henderson@linaro.org> | |
| Mon, 8 Oct 2018 13:55:03 +0000 (8 14:55 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Mon, 8 Oct 2018 13:55:03 +0000 (8 14:55 +0100) | ||
| tree | d96c8650632b711d3043e7d398d9d93fda72ed3c | treesnapshot (tar.gz zip) |
| parent | ced3155141755ba244c988c72c4bde32cc819670 | commitdiff |
target/arm: Clear unused predicate bits for LD1RQ
The 16-byte load only uses 16 predicate bits. But while
reusing the other load infrastructure, we find other bits
that are set and trigger an assert. To avoid this and
retain the assert, zero-extend the predicate that we pass
to the LD1 helper.
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181005175350.30752-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
The 16-byte load only uses 16 predicate bits. But while
reusing the other load infrastructure, we find other bits
that are set and trigger an assert. To avoid this and
retain the assert, zero-extend the predicate that we pass
to the LD1 helper.
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181005175350.30752-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| target/arm/translate-sve.c | diffblobblamehistory |