target/riscv: Don't expose the CPU properties on names CPUs
commit26b2bc58599c02b35e55afbd1bd050faa3d187c2
authorAlistair Francis <alistair.francis@wdc.com>
Wed, 8 Jun 2022 06:14:37 +0000 (8 16:14 +1000)
committerAlistair Francis <alistair.francis@wdc.com>
Thu, 9 Jun 2022 23:31:43 +0000 (10 09:31 +1000)
treea8dc37062cb08473fe68658fa17263f673a9a001
parentb8312675d62b878d6647065f01c2c1337a74d4ee
target/riscv: Don't expose the CPU properties on names CPUs

There are currently two types of RISC-V CPUs:
 - Generic CPUs (base or any) that allow complete custimisation
 - "Named" CPUs that match existing hardware

Users can use the base CPUs to custimise the extensions that they want, for
example -cpu rv64,v=true.

We originally exposed these as part of the named CPUs as well, but that was
by accident.

Exposing the CPU properties to named CPUs means that we accidently
enable extensions that don't exist on the CPUs by default. For example
the SiFive E CPU currently support the zba extension, which is a bug.

This patch instead only exposes the CPU extensions to the generic CPUs.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220608061437.314434-1-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c