| commit | 261c95a0e98e5e9b13c9c005a991b7e7dc27f38a | |
| author | Yongbok Kim <yongbok.kim@mips.com> | |
| Thu, 2 Aug 2018 14:16:02 +0000 (2 16:16 +0200) | ||
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | |
| Fri, 24 Aug 2018 15:51:59 +0000 (24 17:51 +0200) | ||
| tree | c95ba0033ff431f81a6567be4ff18df16399b588 | treesnapshot (tar.gz zip) |
| parent | fa7c0c9f5bc12970858a89f46dd5012c01545b80 | commitdiff |
target/mips: Add nanoMIPS base instruction set opcodes
Add nanoMIPS opcodes. nanoMIPS instruction are organized by so-called
instruction pools. Each pool contains a set of opcodes, that in turn
can be instruction opcodes or instruction pool opcodes.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Add nanoMIPS opcodes. nanoMIPS instruction are organized by so-called
instruction pools. Each pool contains a set of opcodes, that in turn
can be instruction opcodes or instruction pool opcodes.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
| target/mips/translate.c | diffblobblamehistory |