| commit | 252e8c69669599b4bcff802df300726300292f47 | |
| author | Richard Henderson <richard.henderson@linaro.org> | |
| Fri, 26 Jun 2020 03:31:00 +0000 (25 20:31 -0700) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 26 Jun 2020 13:31:11 +0000 (26 14:31 +0100) | ||
| tree | 0ba5ce6e95dc426838678822db3c46640d5f0a9e | treesnapshot (tar.gz zip) |
| parent | c7fd0baac0c24defec66263799faa8618327b352 | commitdiff |
target/arm: Improve masking of SCR RES0 bits
Protect reads of aa64 id registers with ARM_CP_STATE_AA64.
Use this as a simpler test than arm_el_is_aa64, since EL3
cannot change mode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Protect reads of aa64 id registers with ARM_CP_STATE_AA64.
Use this as a simpler test than arm_el_is_aa64, since EL3
cannot change mode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| target/arm/helper.c | diffblobblamehistory |