| commit | 2308092b2b78e6e083092bd3599cec6a0769319e | |
| author | Alistair Francis <alistair.francis@wdc.com> | |
| Thu, 26 Apr 2018 18:15:24 +0000 (26 11:15 -0700) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Thu, 5 Jul 2018 22:24:25 +0000 (5 15:24 -0700) | ||
| tree | b9db2f82d94eb9d0b1012b7ca5062212502c3123 | treesnapshot (tar.gz zip) |
| parent | cee35138b59c6d6b0808c5fa644e3f063832860f | commitdiff |
hw/riscv/sifive_u: Create a SiFive U SoC object
Create a SiFive Unleashed U54 SoC and use that in the sifive_u machine.
We leave the SoC, RAM, device tree and reset/fdt loading as part of the
machine. All the other device creation has been moved to the SoC.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Michael Clark <mjc@sifive.com>
Create a SiFive Unleashed U54 SoC and use that in the sifive_u machine.
We leave the SoC, RAM, device tree and reset/fdt loading as part of the
machine. All the other device creation has been moved to the SoC.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Michael Clark <mjc@sifive.com>
| hw/riscv/sifive_u.c | diffblobblamehistory | |
| include/hw/riscv/sifive_u.h | diffblobblamehistory |