target/arm: Fix sve_uzp_p vs odd vector lengths
commit226e6c046c0fce8da32575aad020ca56a5a8064d
authorRichard Henderson <richard.henderson@linaro.org>
Tue, 9 Mar 2021 15:52:58 +0000 (9 07:52 -0800)
committerPeter Maydell <peter.maydell@linaro.org>
Fri, 12 Mar 2021 12:40:10 +0000 (12 12:40 +0000)
treeda8f34e3670347fc9eb5e0d25fa8c237a4429e92
parentfe2f5cbcfc96f1db3e1a277233f52e2fd993a9e1
target/arm: Fix sve_uzp_p vs odd vector lengths

Missed out on compressing the second half of a predicate
with length vl % 512 > 256.

Adjust all of the x + (y << s) to x | (y << s) as a
general style fix.  Drop the extract64 because the input
uint64_t are known to be already zero-extended from the
current size of the predicate.

Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210309155305.11301-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target/arm/sve_helper.c