| commit | 1e0b21d856d7654ea683e743e964c3b292122081 | |
| author | Richard Henderson <rth@twiddle.net> | |
| Tue, 18 Jul 2017 20:02:40 +0000 (18 10:02 -1000) | ||
| committer | Aurelien Jarno <aurelien@aurel32.net> | |
| Tue, 18 Jul 2017 21:39:17 +0000 (18 23:39 +0200) | ||
| tree | 6972a3768b19e981129fdb0cdab2cdbb68419893 | treesnapshot (tar.gz zip) |
| parent | 0f73753d621b2dddc87bc3d8889cab8636d41d15 | commitdiff |
target/sh4: Merge DREG into fpr64 routines
Also add a debugging assert that we did signal illegal opc
for odd double-precision registers.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-16-rth@twiddle.net>
[aurel32: fix whitespace issues]
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Also add a debugging assert that we did signal illegal opc
for odd double-precision registers.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-16-rth@twiddle.net>
[aurel32: fix whitespace issues]
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
| target/sh4/translate.c | diffblobblamehistory |