| commit | 18aaa59c622208743565307668a2100ab24f7de9 | |
| author | Richard Henderson <richard.henderson@linaro.org> | |
| Fri, 15 Feb 2019 09:56:41 +0000 (15 09:56 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 15 Feb 2019 09:56:41 +0000 (15 09:56 +0000) | ||
| tree | cff4b27a02d325b0f26da5be2c5f23ed424ebe13 | treesnapshot (tar.gz zip) |
| parent | 55a889456ef78f3f9b8eae9846c2f1453b1dd77b | commitdiff |
target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
Given that we mask bits properly on set, there is no reason
to mask them again on get. We failed to clear the exception
status bits, 0x9f, which means that the wrong value would be
returned on get. Except in the (probably normal) case in which
the set clears all of the bits.
Simplify the code in set to also clear the RES0 bits.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190209033847.9014-10-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Given that we mask bits properly on set, there is no reason
to mask them again on get. We failed to clear the exception
status bits, 0x9f, which means that the wrong value would be
returned on get. Except in the (probably normal) case in which
the set clears all of the bits.
Simplify the code in set to also clear the RES0 bits.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190209033847.9014-10-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| target/arm/helper.c | diffblobblamehistory |