| commit | 183e6679e39fb5bcc17dbebaf668c1e83d8e57ee | |
| author | Paolo Bonzini <pbonzini@redhat.com> | |
| Mon, 9 Oct 2023 15:43:12 +0000 (9 17:43 +0200) | ||
| committer | Paolo Bonzini <pbonzini@redhat.com> | |
| Wed, 25 Oct 2023 15:35:07 +0000 (25 17:35 +0200) | ||
| tree | cdeb4dfb4886dceb484ac1d4abf7500ca9f43a07 | treesnapshot (tar.gz zip) |
| parent | 48adb240498de5f628631ba7c713a4ccd0cda358 | commitdiff |
target/i386: group common checks in the decoding phase
In preparation for adding more similar checks, move the VEX.L=0 check
and several X86_SPECIAL_* checks to a new field, where each bit represent
a common check on unused bits, or a restriction on the processor mode.
Likewise, many SVM intercepts can be checked during the decoding phase,
the main exception being the selective CR0 write, MSR and IOIO intercepts.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
In preparation for adding more similar checks, move the VEX.L=0 check
and several X86_SPECIAL_* checks to a new field, where each bit represent
a common check on unused bits, or a restriction on the processor mode.
Likewise, many SVM intercepts can be checked during the decoding phase,
the main exception being the selective CR0 write, MSR and IOIO intercepts.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| target/i386/tcg/decode-new.c.inc | diffblobblamehistory | |
| target/i386/tcg/decode-new.h | diffblobblamehistory | |
| target/i386/tcg/emit.c.inc | diffblobblamehistory |