| commit | 133b84c819166a6da1425a007cf44d7a96d507a4 | |
| author | Richard Henderson <rth@twiddle.net> | |
| Thu, 1 Oct 2015 02:32:52 +0000 (1 12:32 +1000) | ||
| committer | Richard Henderson <rth@twiddle.net> | |
| Wed, 7 Oct 2015 09:03:16 +0000 (7 20:03 +1100) | ||
| tree | 5418c048f1c669eee80221251d9466fb48575cc0 | treesnapshot (tar.gz zip) |
| parent | 95df61e6238c79c2dc14f2bffa76abb2bd3acba7 | commitdiff |
target-tilegx: Handle nofault prefetch instructions
These are mapped onto some of the normal load instructions, when the
destination is the zero register. Other load insns do fault even
when targeting the zero register.
Signed-off-by: Richard Henderson <rth@twiddle.net>
These are mapped onto some of the normal load instructions, when the
destination is the zero register. Other load insns do fault even
when targeting the zero register.
Signed-off-by: Richard Henderson <rth@twiddle.net>
| target-tilegx/translate.c | diffblobblamehistory |