| commit | 0e83f905fb043cedb0282f77b97c50292e148faa | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 19 Nov 2020 21:56:11 +0000 (19 21:56 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 10 Dec 2020 11:44:56 +0000 (10 11:44 +0000) | ||
| tree | 17bee91c698cfcca8a9c7c3fb008d80e2eae8dc4 | treesnapshot (tar.gz zip) |
| parent | fe6fa228a71f0eb8b8ee315452e6a7736c537b1f | commitdiff |
hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit
v8.1M introduces a new TRD flag in the CCR register, which enables
checking for stack frame integrity signatures on SG instructions.
This bit is not banked, and is always RAZ/WI to Non-secure code.
Adjust the code for handling CCR reads and writes to handle this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-23-peter.maydell@linaro.org
v8.1M introduces a new TRD flag in the CCR register, which enables
checking for stack frame integrity signatures on SG instructions.
This bit is not banked, and is always RAZ/WI to Non-secure code.
Adjust the code for handling CCR reads and writes to handle this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-23-peter.maydell@linaro.org
| hw/intc/armv7m_nvic.c | diffblobblamehistory | |
| target/arm/cpu.h | diffblobblamehistory |