target/riscv: Remove privileged spec version restriction for RVV
commit0e660142ca085284c31b8418104b22b18d33bc22
authorFrank Chang <frank.chang@sifive.com>
Wed, 8 Feb 2023 06:32:08 +0000 (8 14:32 +0800)
committerPalmer Dabbelt <palmer@rivosinc.com>
Thu, 23 Feb 2023 22:21:31 +0000 (23 14:21 -0800)
tree8c0968d98d6c6bd340adc12797f4a53d9bfa61c1
parent8b64475bd529ffe42f89b6c2f819e5133c9f8317
target/riscv: Remove privileged spec version restriction for RVV

The RVV specification does not require that the core needs to support
the privileged specification v1.12.0 to support RVV, and there is no
dependency from ISA level.

This commit removes the restriction from both RVV CSRs and extension CPU
ISA string.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230208063209.27279-1-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
target/riscv/cpu.c
target/riscv/csr.c