| commit | 0cf09852015e47a5fbb974ff7ac320366afd21ee | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 11 Jan 2018 13:25:40 +0000 (11 13:25 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 11 Jan 2018 13:25:40 +0000 (11 13:25 +0000) | ||
| tree | beade5d3d69aca0e4e7e1b29728effc133b693da | treesnapshot (tar.gz zip) |
| parent | f1945632b43e36bd9f3e0c2feb0e5b152be7ed91 | commitdiff |
hw/intc/arm_gic: reserved register addresses are RAZ/WI
The GICv2 specification says that reserved register addresses
must RAZ/WI; now that we implement external abort handling
for Arm CPUs this means we must return MEMTX_OK rather than
MEMTX_ERROR, to avoid generating a spurious guest data abort.
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1513183941-24300-3-git-send-email-peter.maydell@linaro.org
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
The GICv2 specification says that reserved register addresses
must RAZ/WI; now that we implement external abort handling
for Arm CPUs this means we must return MEMTX_OK rather than
MEMTX_ERROR, to avoid generating a spurious guest data abort.
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1513183941-24300-3-git-send-email-peter.maydell@linaro.org
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
| hw/intc/arm_gic.c | diffblobblamehistory |