| commit | 0c69996e22e22b85d2e2cdb98e7be5dd83ec5113 | |
| author | Andrew Jeffery <andrew@aj.id.au> | |
| Wed, 16 Mar 2016 17:06:00 +0000 (16 17:06 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Wed, 16 Mar 2016 17:42:18 +0000 (16 17:42 +0000) | ||
| tree | 061bcfc561fb43b67dd940c7d12a66acf296b6b1 | treesnapshot (tar.gz zip) |
| parent | c04bd47db6b95afa72528c9d3fb03b979dd7d426 | commitdiff |
hw/intc: Add (new) ASPEED VIC device model
Implement a basic ASPEED VIC device model for the AST2400 SoC[1], with
enough functionality to boot an aspeed_defconfig Linux kernel. The model
implements the 'new' (revised) register set: While the hardware exposes
both the new and legacy register sets, accesses to the model's legacy
register set will not be serviced (however the access will be logged).
[1] http://www.aspeedtech.com/products.php?fPath=20&rId=376
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Message-id: 1458096317-25223-3-git-send-email-andrew@aj.id.au
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Implement a basic ASPEED VIC device model for the AST2400 SoC[1], with
enough functionality to boot an aspeed_defconfig Linux kernel. The model
implements the 'new' (revised) register set: While the hardware exposes
both the new and legacy register sets, accesses to the model's legacy
register set will not be serviced (however the access will be logged).
[1] http://www.aspeedtech.com/products.php?fPath=20&rId=376
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Message-id: 1458096317-25223-3-git-send-email-andrew@aj.id.au
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| hw/intc/Makefile.objs | diffblobblamehistory | |
| hw/intc/aspeed_vic.c | [new file with mode: 0644] | blob |
| include/hw/intc/aspeed_vic.h | [new file with mode: 0644] | blob |
| trace-events | diffblobblamehistory |