tcg/arm: Use LDRD to load tlb mask+table
commit057b6e370b0947613b0e829c0bb0ddf960003d15
authorRichard Henderson <richard.henderson@linaro.org>
Sat, 23 Mar 2019 07:46:23 +0000 (23 00:46 -0700)
committerRichard Henderson <richard.henderson@linaro.org>
Mon, 10 Jun 2019 14:03:42 +0000 (10 07:03 -0700)
tree9ce1f90e582471cb99a282f815216241591f488b
parent65b23204d609c5aac819049c2d7314b4abd73122
tcg/arm: Use LDRD to load tlb mask+table

This changes the code generation for the tlb from e.g.

ldr      ip, [r6, #-0x10]
ldr      r2, [r6, #-0xc]
and      ip, ip, r4, lsr #8
ldrd     r0, r1, [r2, ip]!
ldr      r2, [r2, #0x18]

to

ldrd     r0, r1, [r6, #-0x10]
and      r0, r0, r4, lsr #8
ldrd     r2, r3, [r1, r0]!
ldr      r1, [r1, #0x18]

for armv7 hosts.  Rearranging the register allocation in
order to avoid overlap between the two ldrd pairs causes
the patch to be larger than it ordinarily would be.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
tcg/arm/tcg-target.inc.c