| commit | 0413d7a55a8161ebd33541ba1df4285bf180c583 | |
| author | Aleksandar Markovic <amarkovic@wavecomp.com> | |
| Thu, 2 Aug 2018 14:15:52 +0000 (2 16:15 +0200) | ||
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | |
| Thu, 16 Aug 2018 17:18:45 +0000 (16 19:18 +0200) | ||
| tree | 34fc512e2c6b2a75bee021312435f4c5015b84b6 | treesnapshot (tar.gz zip) |
| parent | e1555d7ddf2c86fb92165e47eb092f1f5fa9e8bd | commitdiff |
target/mips: Update some CP0 registers bit definitions
Update CP0 registers Config0, Config1, Config2, Config3,
Config4, and Config5 bit definitions.
Some of these bits will be utilized by upcoming nanoMIPS changes.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Update CP0 registers Config0, Config1, Config2, Config3,
Config4, and Config5 bit definitions.
Some of these bits will be utilized by upcoming nanoMIPS changes.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
| target/mips/cpu.h | diffblobblamehistory |