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Revert "usbredir: avoid queuing hello packet on snapshot restore"
[qemu/ar7.git] / hw / ppc / pnv.c
blob3d01e26f845b3429c9d65b76662fc13cd77273d6
1 /*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/datadir.h"
22 #include "qemu/units.h"
23 #include "qemu/cutils.h"
24 #include "qapi/error.h"
25 #include "sysemu/qtest.h"
26 #include "sysemu/sysemu.h"
27 #include "sysemu/numa.h"
28 #include "sysemu/reset.h"
29 #include "sysemu/runstate.h"
30 #include "sysemu/cpus.h"
31 #include "sysemu/device_tree.h"
32 #include "sysemu/hw_accel.h"
33 #include "target/ppc/cpu.h"
34 #include "hw/ppc/fdt.h"
35 #include "hw/ppc/ppc.h"
36 #include "hw/ppc/pnv.h"
37 #include "hw/ppc/pnv_core.h"
38 #include "hw/loader.h"
39 #include "hw/nmi.h"
40 #include "qapi/visitor.h"
41 #include "monitor/monitor.h"
42 #include "hw/intc/intc.h"
43 #include "hw/ipmi/ipmi.h"
44 #include "target/ppc/mmu-hash64.h"
45 #include "hw/pci/msi.h"
46 #include "hw/pci-host/pnv_phb.h"
47
48 #include "hw/ppc/xics.h"
49 #include "hw/qdev-properties.h"
50 #include "hw/ppc/pnv_xscom.h"
51 #include "hw/ppc/pnv_pnor.h"
52
53 #include "hw/isa/isa.h"
54 #include "hw/char/serial.h"
55 #include "hw/rtc/mc146818rtc.h"
56
57 #include <libfdt.h>
58
59 #define FDT_MAX_SIZE (1 * MiB)
60
61 #define FW_FILE_NAME "skiboot.lid"
62 #define FW_LOAD_ADDR 0x0
63 #define FW_MAX_SIZE (16 * MiB)
64
65 #define KERNEL_LOAD_ADDR 0x20000000
66 #define KERNEL_MAX_SIZE (128 * MiB)
67 #define INITRD_LOAD_ADDR 0x28000000
68 #define INITRD_MAX_SIZE (128 * MiB)
69
70 static const char *pnv_chip_core_typename(const PnvChip *o)
71 {
72 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
73 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
74 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
75 const char *core_type = object_class_get_name(object_class_by_name(s));
76 g_free(s);
77 return core_type;
78 }
79
80 /*
81 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
82 * 4 * 4 sockets * 12 cores * 8 threads = 1536
83 * Let's make it 2^11
84 */
85 #define MAX_CPUS 2048
86
87 /*
88 * Memory nodes are created by hostboot, one for each range of memory
89 * that has a different "affinity". In practice, it means one range
90 * per chip.
91 */
92 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
93 {
94 char *mem_name;
95 uint64_t mem_reg_property[2];
96 int off;
97
98 mem_reg_property[0] = cpu_to_be64(start);
99 mem_reg_property[1] = cpu_to_be64(size);
100
101 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
102 off = fdt_add_subnode(fdt, 0, mem_name);
103 g_free(mem_name);
104
105 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
106 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
107 sizeof(mem_reg_property))));
108 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
109 }
110
111 static int get_cpus_node(void *fdt)
112 {
113 int cpus_offset = fdt_path_offset(fdt, "/cpus");
114
115 if (cpus_offset < 0) {
116 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
117 if (cpus_offset) {
118 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
119 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
120 }
121 }
122 _FDT(cpus_offset);
123 return cpus_offset;
124 }
125
126 /*
127 * The PowerNV cores (and threads) need to use real HW ids and not an
128 * incremental index like it has been done on other platforms. This HW
129 * id is stored in the CPU PIR, it is used to create cpu nodes in the
130 * device tree, used in XSCOM to address cores and in interrupt
131 * servers.
132 */
133 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
134 {
135 PowerPCCPU *cpu = pc->threads[0];
136 CPUState *cs = CPU(cpu);
137 DeviceClass *dc = DEVICE_GET_CLASS(cs);
138 int smt_threads = CPU_CORE(pc)->nr_threads;
139 CPUPPCState *env = &cpu->env;
140 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
141 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads);
142 int i;
143 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
144 0xffffffff, 0xffffffff};
145 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
146 uint32_t cpufreq = 1000000000;
147 uint32_t page_sizes_prop[64];
148 size_t page_sizes_prop_size;
149 const uint8_t pa_features[] = { 24, 0,
150 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
151 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
152 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
153 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
154 int offset;
155 char *nodename;
156 int cpus_offset = get_cpus_node(fdt);
157
158 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
159 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
160 _FDT(offset);
161 g_free(nodename);
162
163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
164
165 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
167 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
168
169 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
171 env->dcache_line_size)));
172 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
173 env->dcache_line_size)));
174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
175 env->icache_line_size)));
176 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
177 env->icache_line_size)));
178
179 if (pcc->l1_dcache_size) {
180 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
181 pcc->l1_dcache_size)));
182 } else {
183 warn_report("Unknown L1 dcache size for cpu");
184 }
185 if (pcc->l1_icache_size) {
186 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
187 pcc->l1_icache_size)));
188 } else {
189 warn_report("Unknown L1 icache size for cpu");
190 }
191
192 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
193 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
194 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size",
195 cpu->hash64_opts->slb_size)));
196 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
197 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
198
199 if (ppc_has_spr(cpu, SPR_PURR)) {
200 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
201 }
202
203 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
204 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
205 segs, sizeof(segs))));
206 }
207
208 /*
209 * Advertise VMX/VSX (vector extensions) if available
210 * 0 / no property == no vector extensions
211 * 1 == VMX / Altivec available
212 * 2 == VSX available
213 */
214 if (env->insns_flags & PPC_ALTIVEC) {
215 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
216
217 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
218 }
219
220 /*
221 * Advertise DFP (Decimal Floating Point) if available
222 * 0 / no property == no DFP
223 * 1 == DFP available
224 */
225 if (env->insns_flags2 & PPC2_DFP) {
226 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
227 }
228
229 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
230 sizeof(page_sizes_prop));
231 if (page_sizes_prop_size) {
232 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
233 page_sizes_prop, page_sizes_prop_size)));
234 }
235
236 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
237 pa_features, sizeof(pa_features))));
238
239 /* Build interrupt servers properties */
240 for (i = 0; i < smt_threads; i++) {
241 servers_prop[i] = cpu_to_be32(pc->pir + i);
242 }
243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
244 servers_prop, sizeof(*servers_prop) * smt_threads)));
245 }
246
247 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
248 uint32_t nr_threads)
249 {
250 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
251 char *name;
252 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
253 uint32_t irange[2], i, rsize;
254 uint64_t *reg;
255 int offset;
256
257 irange[0] = cpu_to_be32(pir);
258 irange[1] = cpu_to_be32(nr_threads);
259
260 rsize = sizeof(uint64_t) * 2 * nr_threads;
261 reg = g_malloc(rsize);
262 for (i = 0; i < nr_threads; i++) {
263 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
264 reg[i * 2 + 1] = cpu_to_be64(0x1000);
265 }
266
267 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
268 offset = fdt_add_subnode(fdt, 0, name);
269 _FDT(offset);
270 g_free(name);
271
272 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
273 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
274 _FDT((fdt_setprop_string(fdt, offset, "device_type",
275 "PowerPC-External-Interrupt-Presentation")));
276 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
277 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
278 irange, sizeof(irange))));
279 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
280 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
281 g_free(reg);
282 }
283
284 static PnvPhb4PecState *pnv_phb4_get_pec(PnvChip *chip, PnvPHB4 *phb,
285 Error **errp)
286 {
287 PnvPHB *phb_base = phb->phb_base;
288 PnvPhb4PecState *pecs = NULL;
289 int chip_id = phb->chip_id;
290 int index = phb->phb_id;
291 int i, j;
292
293 if (phb_base->version == 4) {
294 Pnv9Chip *chip9 = PNV9_CHIP(chip);
295
296 pecs = chip9->pecs;
297 } else if (phb_base->version == 5) {
298 Pnv10Chip *chip10 = PNV10_CHIP(chip);
299
300 pecs = chip10->pecs;
301 } else {
302 g_assert_not_reached();
303 }
304
305 for (i = 0; i < chip->num_pecs; i++) {
306 /*
307 * For each PEC, check the amount of phbs it supports
308 * and see if the given phb4 index matches an index.
309 */
310 PnvPhb4PecState *pec = &pecs[i];
311
312 for (j = 0; j < pec->num_phbs; j++) {
313 if (index == pnv_phb4_pec_get_phb_id(pec, j)) {
314 return pec;
315 }
316 }
317 }
318 error_setg(errp,
319 "pnv-phb4 chip-id %d index %d didn't match any existing PEC",
320 chip_id, index);
321
322 return NULL;
323 }
324
325 /*
326 * Adds a PnvPHB to the chip. Returns the parent obj of the
327 * PHB which varies with each version (phb version 3 is parented
328 * by the chip, version 4 and 5 are parented by the PEC
329 * device).
330 *
331 * TODO: for version 3 we're still parenting the PHB with the
332 * chip. We should parent with a (so far not implemented)
333 * PHB3 PEC device.
334 */
335 Object *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp)
336 {
337 if (phb->version == 3) {
338 Pnv8Chip *chip8 = PNV8_CHIP(chip);
339
340 phb->chip = chip;
341
342 chip8->phbs[chip8->num_phbs] = phb;
343 chip8->num_phbs++;
344
345 return OBJECT(chip);
346 }
347
348 phb->pec = pnv_phb4_get_pec(chip, PNV_PHB4(phb->backend), errp);
349
350 return OBJECT(phb->pec);
351 }
352
353 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
354 {
355 static const char compat[] = "ibm,power8-xscom\0ibm,xscom";
356 int i;
357
358 pnv_dt_xscom(chip, fdt, 0,
359 cpu_to_be64(PNV_XSCOM_BASE(chip)),
360 cpu_to_be64(PNV_XSCOM_SIZE),
361 compat, sizeof(compat));
362
363 for (i = 0; i < chip->nr_cores; i++) {
364 PnvCore *pnv_core = chip->cores[i];
365
366 pnv_dt_core(chip, pnv_core, fdt);
367
368 /* Interrupt Control Presenters (ICP). One per core. */
369 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
370 }
371
372 if (chip->ram_size) {
373 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
374 }
375 }
376
377 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
378 {
379 static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
380 int i;
381
382 pnv_dt_xscom(chip, fdt, 0,
383 cpu_to_be64(PNV9_XSCOM_BASE(chip)),
384 cpu_to_be64(PNV9_XSCOM_SIZE),
385 compat, sizeof(compat));
386
387 for (i = 0; i < chip->nr_cores; i++) {
388 PnvCore *pnv_core = chip->cores[i];
389
390 pnv_dt_core(chip, pnv_core, fdt);
391 }
392
393 if (chip->ram_size) {
394 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
395 }
396
397 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
398 }
399
400 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
401 {
402 static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
403 int i;
404
405 pnv_dt_xscom(chip, fdt, 0,
406 cpu_to_be64(PNV10_XSCOM_BASE(chip)),
407 cpu_to_be64(PNV10_XSCOM_SIZE),
408 compat, sizeof(compat));
409
410 for (i = 0; i < chip->nr_cores; i++) {
411 PnvCore *pnv_core = chip->cores[i];
412
413 pnv_dt_core(chip, pnv_core, fdt);
414 }
415
416 if (chip->ram_size) {
417 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
418 }
419
420 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE);
421 }
422
423 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
424 {
425 uint32_t io_base = d->ioport_id;
426 uint32_t io_regs[] = {
427 cpu_to_be32(1),
428 cpu_to_be32(io_base),
429 cpu_to_be32(2)
430 };
431 char *name;
432 int node;
433
434 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
435 node = fdt_add_subnode(fdt, lpc_off, name);
436 _FDT(node);
437 g_free(name);
438
439 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
440 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
441 }
442
443 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
444 {
445 const char compatible[] = "ns16550\0pnpPNP,501";
446 uint32_t io_base = d->ioport_id;
447 uint32_t io_regs[] = {
448 cpu_to_be32(1),
449 cpu_to_be32(io_base),
450 cpu_to_be32(8)
451 };
452 uint32_t irq;
453 char *name;
454 int node;
455
456 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal);
457
458 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
459 node = fdt_add_subnode(fdt, lpc_off, name);
460 _FDT(node);
461 g_free(name);
462
463 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
464 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
465 sizeof(compatible))));
466
467 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
468 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
469 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
470 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
471 fdt_get_phandle(fdt, lpc_off))));
472
473 /* This is needed by Linux */
474 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
475 }
476
477 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
478 {
479 const char compatible[] = "bt\0ipmi-bt";
480 uint32_t io_base;
481 uint32_t io_regs[] = {
482 cpu_to_be32(1),
483 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
484 cpu_to_be32(3)
485 };
486 uint32_t irq;
487 char *name;
488 int node;
489
490 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
491 io_regs[1] = cpu_to_be32(io_base);
492
493 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
494
495 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
496 node = fdt_add_subnode(fdt, lpc_off, name);
497 _FDT(node);
498 g_free(name);
499
500 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
501 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
502 sizeof(compatible))));
503
504 /* Mark it as reserved to avoid Linux trying to claim it */
505 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
506 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
507 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
508 fdt_get_phandle(fdt, lpc_off))));
509 }
510
511 typedef struct ForeachPopulateArgs {
512 void *fdt;
513 int offset;
514 } ForeachPopulateArgs;
515
516 static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
517 {
518 ForeachPopulateArgs *args = opaque;
519 ISADevice *d = ISA_DEVICE(dev);
520
521 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
522 pnv_dt_rtc(d, args->fdt, args->offset);
523 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
524 pnv_dt_serial(d, args->fdt, args->offset);
525 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
526 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
527 } else {
528 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
529 d->ioport_id);
530 }
531
532 return 0;
533 }
534
535 /*
536 * The default LPC bus of a multichip system is on chip 0. It's
537 * recognized by the firmware (skiboot) using a "primary" property.
538 */
539 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
540 {
541 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
542 ForeachPopulateArgs args = {
543 .fdt = fdt,
544 .offset = isa_offset,
545 };
546 uint32_t phandle;
547
548 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
549
550 phandle = qemu_fdt_alloc_phandle(fdt);
551 assert(phandle > 0);
552 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle)));
553
554 /*
555 * ISA devices are not necessarily parented to the ISA bus so we
556 * can not use object_child_foreach()
557 */
558 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
559 &args);
560 }
561
562 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt)
563 {
564 int off;
565
566 off = fdt_add_subnode(fdt, 0, "ibm,opal");
567 off = fdt_add_subnode(fdt, off, "power-mgt");
568
569 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000));
570 }
571
572 static void *pnv_dt_create(MachineState *machine)
573 {
574 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
575 PnvMachineState *pnv = PNV_MACHINE(machine);
576 void *fdt;
577 char *buf;
578 int off;
579 int i;
580
581 fdt = g_malloc0(FDT_MAX_SIZE);
582 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
583
584 /* /qemu node */
585 _FDT((fdt_add_subnode(fdt, 0, "qemu")));
586
587 /* Root node */
588 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
589 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
590 _FDT((fdt_setprop_string(fdt, 0, "model",
591 "IBM PowerNV (emulated by qemu)")));
592 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size)));
593
594 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
595 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
596 if (qemu_uuid_set) {
597 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf)));
598 }
599 g_free(buf);
600
601 off = fdt_add_subnode(fdt, 0, "chosen");
602 if (machine->kernel_cmdline) {
603 _FDT((fdt_setprop_string(fdt, off, "bootargs",
604 machine->kernel_cmdline)));
605 }
606
607 if (pnv->initrd_size) {
608 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
609 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
610
611 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
612 &start_prop, sizeof(start_prop))));
613 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
614 &end_prop, sizeof(end_prop))));
615 }
616
617 /* Populate device tree for each chip */
618 for (i = 0; i < pnv->num_chips; i++) {
619 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
620 }
621
622 /* Populate ISA devices on chip 0 */
623 pnv_dt_isa(pnv, fdt);
624
625 if (pnv->bmc) {
626 pnv_dt_bmc_sensors(pnv->bmc, fdt);
627 }
628
629 /* Create an extra node for power management on machines that support it */
630 if (pmc->dt_power_mgt) {
631 pmc->dt_power_mgt(pnv, fdt);
632 }
633
634 return fdt;
635 }
636
637 static void pnv_powerdown_notify(Notifier *n, void *opaque)
638 {
639 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier);
640
641 if (pnv->bmc) {
642 pnv_bmc_powerdown(pnv->bmc);
643 }
644 }
645
646 static void pnv_reset(MachineState *machine, ShutdownCause reason)
647 {
648 PnvMachineState *pnv = PNV_MACHINE(machine);
649 IPMIBmc *bmc;
650 void *fdt;
651
652 qemu_devices_reset(reason);
653
654 /*
655 * The machine should provide by default an internal BMC simulator.
656 * If not, try to use the BMC device that was provided on the command
657 * line.
658 */
659 bmc = pnv_bmc_find(&error_fatal);
660 if (!pnv->bmc) {
661 if (!bmc) {
662 if (!qtest_enabled()) {
663 warn_report("machine has no BMC device. Use '-device "
664 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' "
665 "to define one");
666 }
667 } else {
668 pnv_bmc_set_pnor(bmc, pnv->pnor);
669 pnv->bmc = bmc;
670 }
671 }
672
673 fdt = pnv_dt_create(machine);
674
675 /* Pack resulting tree */
676 _FDT((fdt_pack(fdt)));
677
678 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
679 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
680
681 /*
682 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free
683 * the existing machine->fdt to avoid leaking it during
684 * a reset.
685 */
686 g_free(machine->fdt);
687 machine->fdt = fdt;
688 }
689
690 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
691 {
692 Pnv8Chip *chip8 = PNV8_CHIP(chip);
693 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL);
694
695 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq);
696 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
697 }
698
699 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
700 {
701 Pnv8Chip *chip8 = PNV8_CHIP(chip);
702 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C);
703
704 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq);
705 return pnv_lpc_isa_create(&chip8->lpc, false, errp);
706 }
707
708 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
709 {
710 Pnv9Chip *chip9 = PNV9_CHIP(chip);
711 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC);
712
713 qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq);
714 return pnv_lpc_isa_create(&chip9->lpc, false, errp);
715 }
716
717 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
718 {
719 Pnv10Chip *chip10 = PNV10_CHIP(chip);
720 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC);
721
722 qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq);
723 return pnv_lpc_isa_create(&chip10->lpc, false, errp);
724 }
725
726 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
727 {
728 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
729 }
730
731 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
732 {
733 Pnv8Chip *chip8 = PNV8_CHIP(chip);
734 int i;
735
736 ics_pic_print_info(&chip8->psi.ics, mon);
737
738 for (i = 0; i < chip8->num_phbs; i++) {
739 PnvPHB *phb = chip8->phbs[i];
740 PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
741
742 pnv_phb3_msi_pic_print_info(&phb3->msis, mon);
743 ics_pic_print_info(&phb3->lsis, mon);
744 }
745 }
746
747 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque)
748 {
749 Monitor *mon = opaque;
750 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB);
751
752 if (!phb) {
753 return 0;
754 }
755
756 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), mon);
757
758 return 0;
759 }
760
761 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
762 {
763 Pnv9Chip *chip9 = PNV9_CHIP(chip);
764
765 pnv_xive_pic_print_info(&chip9->xive, mon);
766 pnv_psi_pic_print_info(&chip9->psi, mon);
767
768 object_child_foreach_recursive(OBJECT(chip),
769 pnv_chip_power9_pic_print_info_child, mon);
770 }
771
772 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip,
773 uint32_t core_id)
774 {
775 return PNV_XSCOM_EX_BASE(core_id);
776 }
777
778 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip,
779 uint32_t core_id)
780 {
781 return PNV9_XSCOM_EC_BASE(core_id);
782 }
783
784 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip,
785 uint32_t core_id)
786 {
787 return PNV10_XSCOM_EC_BASE(core_id);
788 }
789
790 static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
791 {
792 PowerPCCPUClass *ppc_default =
793 POWERPC_CPU_CLASS(object_class_by_name(default_type));
794 PowerPCCPUClass *ppc =
795 POWERPC_CPU_CLASS(object_class_by_name(cpu_type));
796
797 return ppc_default->pvr_match(ppc_default, ppc->pvr, false);
798 }
799
800 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
801 {
802 ISADevice *dev = isa_new("isa-ipmi-bt");
803
804 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal);
805 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal);
806 isa_realize_and_unref(dev, bus, &error_fatal);
807 }
808
809 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
810 {
811 Pnv10Chip *chip10 = PNV10_CHIP(chip);
812
813 pnv_xive2_pic_print_info(&chip10->xive, mon);
814 pnv_psi_pic_print_info(&chip10->psi, mon);
815
816 object_child_foreach_recursive(OBJECT(chip),
817 pnv_chip_power9_pic_print_info_child, mon);
818 }
819
820 /* Always give the first 1GB to chip 0 else we won't boot */
821 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id)
822 {
823 MachineState *machine = MACHINE(pnv);
824 uint64_t ram_per_chip;
825
826 assert(machine->ram_size >= 1 * GiB);
827
828 ram_per_chip = machine->ram_size / pnv->num_chips;
829 if (ram_per_chip >= 1 * GiB) {
830 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
831 }
832
833 assert(pnv->num_chips > 1);
834
835 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1);
836 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
837 }
838
839 static void pnv_init(MachineState *machine)
840 {
841 const char *bios_name = machine->firmware ?: FW_FILE_NAME;
842 PnvMachineState *pnv = PNV_MACHINE(machine);
843 MachineClass *mc = MACHINE_GET_CLASS(machine);
844 char *fw_filename;
845 long fw_size;
846 uint64_t chip_ram_start = 0;
847 int i;
848 char *chip_typename;
849 DriveInfo *pnor = drive_get(IF_MTD, 0, 0);
850 DeviceState *dev;
851
852 if (kvm_enabled()) {
853 error_report("The powernv machine does not work with KVM acceleration");
854 exit(EXIT_FAILURE);
855 }
856
857 /* allocate RAM */
858 if (machine->ram_size < mc->default_ram_size) {
859 char *sz = size_to_str(mc->default_ram_size);
860 error_report("Invalid RAM size, should be bigger than %s", sz);
861 g_free(sz);
862 exit(EXIT_FAILURE);
863 }
864 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
865
866 /*
867 * Create our simple PNOR device
868 */
869 dev = qdev_new(TYPE_PNV_PNOR);
870 if (pnor) {
871 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor));
872 }
873 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
874 pnv->pnor = PNV_PNOR(dev);
875
876 /* load skiboot firmware */
877 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
878 if (!fw_filename) {
879 error_report("Could not find OPAL firmware '%s'", bios_name);
880 exit(1);
881 }
882
883 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE);
884 if (fw_size < 0) {
885 error_report("Could not load OPAL firmware '%s'", fw_filename);
886 exit(1);
887 }
888 g_free(fw_filename);
889
890 /* load kernel */
891 if (machine->kernel_filename) {
892 long kernel_size;
893
894 kernel_size = load_image_targphys(machine->kernel_filename,
895 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE);
896 if (kernel_size < 0) {
897 error_report("Could not load kernel '%s'",
898 machine->kernel_filename);
899 exit(1);
900 }
901 }
902
903 /* load initrd */
904 if (machine->initrd_filename) {
905 pnv->initrd_base = INITRD_LOAD_ADDR;
906 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
907 pnv->initrd_base, INITRD_MAX_SIZE);
908 if (pnv->initrd_size < 0) {
909 error_report("Could not load initial ram disk '%s'",
910 machine->initrd_filename);
911 exit(1);
912 }
913 }
914
915 /* MSIs are supported on this platform */
916 msi_nonbroken = true;
917
918 /*
919 * Check compatibility of the specified CPU with the machine
920 * default.
921 */
922 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) {
923 error_report("invalid CPU model '%s' for %s machine",
924 machine->cpu_type, mc->name);
925 exit(1);
926 }
927
928 /* Create the processor chips */
929 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
930 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
931 i, machine->cpu_type);
932 if (!object_class_by_name(chip_typename)) {
933 error_report("invalid chip model '%.*s' for %s machine",
934 i, machine->cpu_type, mc->name);
935 exit(1);
936 }
937
938 pnv->num_chips =
939 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
940 /*
941 * TODO: should we decide on how many chips we can create based
942 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
943 */
944 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) {
945 error_report("invalid number of chips: '%d'", pnv->num_chips);
946 error_printf(
947 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n");
948 exit(1);
949 }
950
951 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
952 for (i = 0; i < pnv->num_chips; i++) {
953 char chip_name[32];
954 Object *chip = OBJECT(qdev_new(chip_typename));
955 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i);
956
957 pnv->chips[i] = PNV_CHIP(chip);
958
959 /* Distribute RAM among the chips */
960 object_property_set_int(chip, "ram-start", chip_ram_start,
961 &error_fatal);
962 object_property_set_int(chip, "ram-size", chip_ram_size,
963 &error_fatal);
964 chip_ram_start += chip_ram_size;
965
966 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i);
967 object_property_add_child(OBJECT(pnv), chip_name, chip);
968 object_property_set_int(chip, "chip-id", i, &error_fatal);
969 object_property_set_int(chip, "nr-cores", machine->smp.cores,
970 &error_fatal);
971 object_property_set_int(chip, "nr-threads", machine->smp.threads,
972 &error_fatal);
973 /*
974 * The POWER8 machine use the XICS interrupt interface.
975 * Propagate the XICS fabric to the chip and its controllers.
976 */
977 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) {
978 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort);
979 }
980 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) {
981 object_property_set_link(chip, "xive-fabric", OBJECT(pnv),
982 &error_abort);
983 }
984 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal);
985 }
986 g_free(chip_typename);
987
988 /* Instantiate ISA bus on chip 0 */
989 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
990
991 /* Create serial port */
992 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
993
994 /* Create an RTC ISA device too */
995 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
996
997 /*
998 * Create the machine BMC simulator and the IPMI BT device for
999 * communication with the BMC
1000 */
1001 if (defaults_enabled()) {
1002 pnv->bmc = pnv_bmc_create(pnv->pnor);
1003 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10);
1004 }
1005
1006 /*
1007 * The PNOR is mapped on the LPC FW address space by the BMC.
1008 * Since we can not reach the remote BMC machine with LPC memops,
1009 * map it always for now.
1010 */
1011 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET,
1012 &pnv->pnor->mmio);
1013
1014 /*
1015 * OpenPOWER systems use a IPMI SEL Event message to notify the
1016 * host to powerdown
1017 */
1018 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
1019 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
1020 }
1021
1022 /*
1023 * 0:21 Reserved - Read as zeros
1024 * 22:24 Chip ID
1025 * 25:28 Core number
1026 * 29:31 Thread ID
1027 */
1028 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
1029 {
1030 return (chip->chip_id << 7) | (core_id << 3);
1031 }
1032
1033 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1034 Error **errp)
1035 {
1036 Pnv8Chip *chip8 = PNV8_CHIP(chip);
1037 Error *local_err = NULL;
1038 Object *obj;
1039 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1040
1041 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err);
1042 if (local_err) {
1043 error_propagate(errp, local_err);
1044 return;
1045 }
1046
1047 pnv_cpu->intc = obj;
1048 }
1049
1050
1051 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1052 {
1053 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1054
1055 icp_reset(ICP(pnv_cpu->intc));
1056 }
1057
1058 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1059 {
1060 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1061
1062 icp_destroy(ICP(pnv_cpu->intc));
1063 pnv_cpu->intc = NULL;
1064 }
1065
1066 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1067 Monitor *mon)
1068 {
1069 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
1070 }
1071
1072 /*
1073 * 0:48 Reserved - Read as zeroes
1074 * 49:52 Node ID
1075 * 53:55 Chip ID
1076 * 56 Reserved - Read as zero
1077 * 57:61 Core number
1078 * 62:63 Thread ID
1079 *
1080 * We only care about the lower bits. uint32_t is fine for the moment.
1081 */
1082 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
1083 {
1084 return (chip->chip_id << 8) | (core_id << 2);
1085 }
1086
1087 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id)
1088 {
1089 return (chip->chip_id << 8) | (core_id << 2);
1090 }
1091
1092 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1093 Error **errp)
1094 {
1095 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1096 Error *local_err = NULL;
1097 Object *obj;
1098 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1099
1100 /*
1101 * The core creates its interrupt presenter but the XIVE interrupt
1102 * controller object is initialized afterwards. Hopefully, it's
1103 * only used at runtime.
1104 */
1105 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive),
1106 &local_err);
1107 if (local_err) {
1108 error_propagate(errp, local_err);
1109 return;
1110 }
1111
1112 pnv_cpu->intc = obj;
1113 }
1114
1115 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1116 {
1117 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1118
1119 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
1120 }
1121
1122 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1123 {
1124 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1125
1126 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
1127 pnv_cpu->intc = NULL;
1128 }
1129
1130 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1131 Monitor *mon)
1132 {
1133 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
1134 }
1135
1136 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1137 Error **errp)
1138 {
1139 Pnv10Chip *chip10 = PNV10_CHIP(chip);
1140 Error *local_err = NULL;
1141 Object *obj;
1142 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1143
1144 /*
1145 * The core creates its interrupt presenter but the XIVE2 interrupt
1146 * controller object is initialized afterwards. Hopefully, it's
1147 * only used at runtime.
1148 */
1149 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive),
1150 &local_err);
1151 if (local_err) {
1152 error_propagate(errp, local_err);
1153 return;
1154 }
1155
1156 pnv_cpu->intc = obj;
1157 }
1158
1159 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1160 {
1161 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1162
1163 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
1164 }
1165
1166 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1167 {
1168 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1169
1170 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
1171 pnv_cpu->intc = NULL;
1172 }
1173
1174 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1175 Monitor *mon)
1176 {
1177 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
1178 }
1179
1180 /*
1181 * Allowed core identifiers on a POWER8 Processor Chip :
1182 *
1183 * <EX0 reserved>
1184 * EX1 - Venice only
1185 * EX2 - Venice only
1186 * EX3 - Venice only
1187 * EX4
1188 * EX5
1189 * EX6
1190 * <EX7,8 reserved> <reserved>
1191 * EX9 - Venice only
1192 * EX10 - Venice only
1193 * EX11 - Venice only
1194 * EX12
1195 * EX13
1196 * EX14
1197 * <EX15 reserved>
1198 */
1199 #define POWER8E_CORE_MASK (0x7070ull)
1200 #define POWER8_CORE_MASK (0x7e7eull)
1201
1202 /*
1203 * POWER9 has 24 cores, ids starting at 0x0
1204 */
1205 #define POWER9_CORE_MASK (0xffffffffffffffull)
1206
1207
1208 #define POWER10_CORE_MASK (0xffffffffffffffull)
1209
1210 static void pnv_chip_power8_instance_init(Object *obj)
1211 {
1212 Pnv8Chip *chip8 = PNV8_CHIP(obj);
1213 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1214 int i;
1215
1216 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC,
1217 (Object **)&chip8->xics,
1218 object_property_allow_set_link,
1219 OBJ_PROP_LINK_STRONG);
1220
1221 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI);
1222
1223 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC);
1224
1225 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC);
1226
1227 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER);
1228
1229 if (defaults_enabled()) {
1230 chip8->num_phbs = pcc->num_phbs;
1231
1232 for (i = 0; i < chip8->num_phbs; i++) {
1233 Object *phb = object_new(TYPE_PNV_PHB);
1234
1235 /*
1236 * We need the chip to parent the PHB to allow the DT
1237 * to build correctly (via pnv_xscom_dt()).
1238 *
1239 * TODO: the PHB should be parented by a PEC device that, at
1240 * this moment, is not modelled powernv8/phb3.
1241 */
1242 object_property_add_child(obj, "phb[*]", phb);
1243 chip8->phbs[i] = PNV_PHB(phb);
1244 }
1245 }
1246
1247 }
1248
1249 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
1250 {
1251 PnvChip *chip = PNV_CHIP(chip8);
1252 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1253 int i, j;
1254 char *name;
1255
1256 name = g_strdup_printf("icp-%x", chip->chip_id);
1257 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
1258 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio);
1259 g_free(name);
1260
1261 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
1262
1263 /* Map the ICP registers for each thread */
1264 for (i = 0; i < chip->nr_cores; i++) {
1265 PnvCore *pnv_core = chip->cores[i];
1266 int core_hwid = CPU_CORE(pnv_core)->core_id;
1267
1268 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
1269 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
1270 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
1271
1272 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
1273 &icp->mmio);
1274 }
1275 }
1276 }
1277
1278 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
1279 {
1280 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1281 PnvChip *chip = PNV_CHIP(dev);
1282 Pnv8Chip *chip8 = PNV8_CHIP(dev);
1283 Pnv8Psi *psi8 = &chip8->psi;
1284 Error *local_err = NULL;
1285 int i;
1286
1287 assert(chip8->xics);
1288
1289 /* XSCOM bridge is first */
1290 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err);
1291 if (local_err) {
1292 error_propagate(errp, local_err);
1293 return;
1294 }
1295 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
1296
1297 pcc->parent_realize(dev, &local_err);
1298 if (local_err) {
1299 error_propagate(errp, local_err);
1300 return;
1301 }
1302
1303 /* Processor Service Interface (PSI) Host Bridge */
1304 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip),
1305 &error_fatal);
1306 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS,
1307 OBJECT(chip8->xics), &error_abort);
1308 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) {
1309 return;
1310 }
1311 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
1312 &PNV_PSI(psi8)->xscom_regs);
1313
1314 /* Create LPC controller */
1315 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal);
1316 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
1317
1318 chip->fw_mr = &chip8->lpc.isa_fw;
1319 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
1320 (uint64_t) PNV_XSCOM_BASE(chip),
1321 PNV_XSCOM_LPC_BASE);
1322
1323 /*
1324 * Interrupt Management Area. This is the memory region holding
1325 * all the Interrupt Control Presenter (ICP) registers
1326 */
1327 pnv_chip_icp_realize(chip8, &local_err);
1328 if (local_err) {
1329 error_propagate(errp, local_err);
1330 return;
1331 }
1332
1333 /* Create the simplified OCC model */
1334 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) {
1335 return;
1336 }
1337 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
1338 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0,
1339 qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_OCC));
1340
1341 /* OCC SRAM model */
1342 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
1343 &chip8->occ.sram_regs);
1344
1345 /* HOMER */
1346 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip),
1347 &error_abort);
1348 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) {
1349 return;
1350 }
1351 /* Homer Xscom region */
1352 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
1353
1354 /* Homer mmio region */
1355 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
1356 &chip8->homer.regs);
1357
1358 /* PHB controllers */
1359 for (i = 0; i < chip8->num_phbs; i++) {
1360 PnvPHB *phb = chip8->phbs[i];
1361
1362 object_property_set_int(OBJECT(phb), "index", i, &error_fatal);
1363 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id,
1364 &error_fatal);
1365 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip),
1366 &error_fatal);
1367 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) {
1368 return;
1369 }
1370 }
1371 }
1372
1373 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr)
1374 {
1375 addr &= (PNV_XSCOM_SIZE - 1);
1376 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
1377 }
1378
1379 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
1380 {
1381 DeviceClass *dc = DEVICE_CLASS(klass);
1382 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1383
1384 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
1385 k->cores_mask = POWER8E_CORE_MASK;
1386 k->num_phbs = 3;
1387 k->core_pir = pnv_chip_core_pir_p8;
1388 k->intc_create = pnv_chip_power8_intc_create;
1389 k->intc_reset = pnv_chip_power8_intc_reset;
1390 k->intc_destroy = pnv_chip_power8_intc_destroy;
1391 k->intc_print_info = pnv_chip_power8_intc_print_info;
1392 k->isa_create = pnv_chip_power8_isa_create;
1393 k->dt_populate = pnv_chip_power8_dt_populate;
1394 k->pic_print_info = pnv_chip_power8_pic_print_info;
1395 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1396 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1397 dc->desc = "PowerNV Chip POWER8E";
1398
1399 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1400 &k->parent_realize);
1401 }
1402
1403 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
1404 {
1405 DeviceClass *dc = DEVICE_CLASS(klass);
1406 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1407
1408 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
1409 k->cores_mask = POWER8_CORE_MASK;
1410 k->num_phbs = 3;
1411 k->core_pir = pnv_chip_core_pir_p8;
1412 k->intc_create = pnv_chip_power8_intc_create;
1413 k->intc_reset = pnv_chip_power8_intc_reset;
1414 k->intc_destroy = pnv_chip_power8_intc_destroy;
1415 k->intc_print_info = pnv_chip_power8_intc_print_info;
1416 k->isa_create = pnv_chip_power8_isa_create;
1417 k->dt_populate = pnv_chip_power8_dt_populate;
1418 k->pic_print_info = pnv_chip_power8_pic_print_info;
1419 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1420 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1421 dc->desc = "PowerNV Chip POWER8";
1422
1423 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1424 &k->parent_realize);
1425 }
1426
1427 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
1428 {
1429 DeviceClass *dc = DEVICE_CLASS(klass);
1430 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1431
1432 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
1433 k->cores_mask = POWER8_CORE_MASK;
1434 k->num_phbs = 4;
1435 k->core_pir = pnv_chip_core_pir_p8;
1436 k->intc_create = pnv_chip_power8_intc_create;
1437 k->intc_reset = pnv_chip_power8_intc_reset;
1438 k->intc_destroy = pnv_chip_power8_intc_destroy;
1439 k->intc_print_info = pnv_chip_power8_intc_print_info;
1440 k->isa_create = pnv_chip_power8nvl_isa_create;
1441 k->dt_populate = pnv_chip_power8_dt_populate;
1442 k->pic_print_info = pnv_chip_power8_pic_print_info;
1443 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1444 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1445 dc->desc = "PowerNV Chip POWER8NVL";
1446
1447 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1448 &k->parent_realize);
1449 }
1450
1451 static void pnv_chip_power9_instance_init(Object *obj)
1452 {
1453 PnvChip *chip = PNV_CHIP(obj);
1454 Pnv9Chip *chip9 = PNV9_CHIP(obj);
1455 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1456 int i;
1457
1458 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE);
1459 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive),
1460 "xive-fabric");
1461
1462 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI);
1463
1464 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC);
1465
1466 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC);
1467
1468 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE);
1469
1470 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER);
1471
1472 /* Number of PECs is the chip default */
1473 chip->num_pecs = pcc->num_pecs;
1474
1475 for (i = 0; i < chip->num_pecs; i++) {
1476 object_initialize_child(obj, "pec[*]", &chip9->pecs[i],
1477 TYPE_PNV_PHB4_PEC);
1478 }
1479 }
1480
1481 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq,
1482 PnvCore *pnv_core)
1483 {
1484 char eq_name[32];
1485 int core_id = CPU_CORE(pnv_core)->core_id;
1486
1487 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
1488 object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
1489 sizeof(*eq), TYPE_PNV_QUAD,
1490 &error_fatal, NULL);
1491
1492 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
1493 qdev_realize(DEVICE(eq), NULL, &error_fatal);
1494 }
1495
1496 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
1497 {
1498 PnvChip *chip = PNV_CHIP(chip9);
1499 int i;
1500
1501 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1502 chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
1503
1504 for (i = 0; i < chip9->nr_quads; i++) {
1505 PnvQuad *eq = &chip9->quads[i];
1506
1507 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
1508
1509 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id),
1510 &eq->xscom_regs);
1511 }
1512 }
1513
1514 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp)
1515 {
1516 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1517 int i;
1518
1519 for (i = 0; i < chip->num_pecs; i++) {
1520 PnvPhb4PecState *pec = &chip9->pecs[i];
1521 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1522 uint32_t pec_nest_base;
1523 uint32_t pec_pci_base;
1524
1525 object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
1526 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
1527 &error_fatal);
1528 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
1529 &error_fatal);
1530 if (!qdev_realize(DEVICE(pec), NULL, errp)) {
1531 return;
1532 }
1533
1534 pec_nest_base = pecc->xscom_nest_base(pec);
1535 pec_pci_base = pecc->xscom_pci_base(pec);
1536
1537 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
1538 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
1539 }
1540 }
1541
1542 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
1543 {
1544 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1545 Pnv9Chip *chip9 = PNV9_CHIP(dev);
1546 PnvChip *chip = PNV_CHIP(dev);
1547 Pnv9Psi *psi9 = &chip9->psi;
1548 Error *local_err = NULL;
1549
1550 /* XSCOM bridge is first */
1551 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err);
1552 if (local_err) {
1553 error_propagate(errp, local_err);
1554 return;
1555 }
1556 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip));
1557
1558 pcc->parent_realize(dev, &local_err);
1559 if (local_err) {
1560 error_propagate(errp, local_err);
1561 return;
1562 }
1563
1564 pnv_chip_quad_realize(chip9, &local_err);
1565 if (local_err) {
1566 error_propagate(errp, local_err);
1567 return;
1568 }
1569
1570 /* XIVE interrupt controller (POWER9) */
1571 object_property_set_int(OBJECT(&chip9->xive), "ic-bar",
1572 PNV9_XIVE_IC_BASE(chip), &error_fatal);
1573 object_property_set_int(OBJECT(&chip9->xive), "vc-bar",
1574 PNV9_XIVE_VC_BASE(chip), &error_fatal);
1575 object_property_set_int(OBJECT(&chip9->xive), "pc-bar",
1576 PNV9_XIVE_PC_BASE(chip), &error_fatal);
1577 object_property_set_int(OBJECT(&chip9->xive), "tm-bar",
1578 PNV9_XIVE_TM_BASE(chip), &error_fatal);
1579 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip),
1580 &error_abort);
1581 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) {
1582 return;
1583 }
1584 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE,
1585 &chip9->xive.xscom_regs);
1586
1587 /* Processor Service Interface (PSI) Host Bridge */
1588 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip),
1589 &error_fatal);
1590 /* This is the only device with 4k ESB pages */
1591 object_property_set_int(OBJECT(&chip9->psi), "shift", XIVE_ESB_4K,
1592 &error_fatal);
1593 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) {
1594 return;
1595 }
1596 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
1597 &PNV_PSI(psi9)->xscom_regs);
1598
1599 /* LPC */
1600 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) {
1601 return;
1602 }
1603 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
1604 &chip9->lpc.xscom_regs);
1605
1606 chip->fw_mr = &chip9->lpc.isa_fw;
1607 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1608 (uint64_t) PNV9_LPCM_BASE(chip));
1609
1610 /* Create the simplified OCC model */
1611 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) {
1612 return;
1613 }
1614 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
1615 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in(
1616 DEVICE(&chip9->psi), PSIHB9_IRQ_OCC));
1617
1618 /* OCC SRAM model */
1619 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
1620 &chip9->occ.sram_regs);
1621
1622 /* SBE */
1623 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) {
1624 return;
1625 }
1626 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE,
1627 &chip9->sbe.xscom_ctrl_regs);
1628 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE,
1629 &chip9->sbe.xscom_mbox_regs);
1630 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in(
1631 DEVICE(&chip9->psi), PSIHB9_IRQ_PSU));
1632
1633 /* HOMER */
1634 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip),
1635 &error_abort);
1636 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) {
1637 return;
1638 }
1639 /* Homer Xscom region */
1640 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs);
1641
1642 /* Homer mmio region */
1643 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
1644 &chip9->homer.regs);
1645
1646 /* PEC PHBs */
1647 pnv_chip_power9_pec_realize(chip, &local_err);
1648 if (local_err) {
1649 error_propagate(errp, local_err);
1650 return;
1651 }
1652 }
1653
1654 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr)
1655 {
1656 addr &= (PNV9_XSCOM_SIZE - 1);
1657 return addr >> 3;
1658 }
1659
1660 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
1661 {
1662 DeviceClass *dc = DEVICE_CLASS(klass);
1663 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1664
1665 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
1666 k->cores_mask = POWER9_CORE_MASK;
1667 k->core_pir = pnv_chip_core_pir_p9;
1668 k->intc_create = pnv_chip_power9_intc_create;
1669 k->intc_reset = pnv_chip_power9_intc_reset;
1670 k->intc_destroy = pnv_chip_power9_intc_destroy;
1671 k->intc_print_info = pnv_chip_power9_intc_print_info;
1672 k->isa_create = pnv_chip_power9_isa_create;
1673 k->dt_populate = pnv_chip_power9_dt_populate;
1674 k->pic_print_info = pnv_chip_power9_pic_print_info;
1675 k->xscom_core_base = pnv_chip_power9_xscom_core_base;
1676 k->xscom_pcba = pnv_chip_power9_xscom_pcba;
1677 dc->desc = "PowerNV Chip POWER9";
1678 k->num_pecs = PNV9_CHIP_MAX_PEC;
1679
1680 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
1681 &k->parent_realize);
1682 }
1683
1684 static void pnv_chip_power10_instance_init(Object *obj)
1685 {
1686 PnvChip *chip = PNV_CHIP(obj);
1687 Pnv10Chip *chip10 = PNV10_CHIP(obj);
1688 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1689 int i;
1690
1691 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2);
1692 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive),
1693 "xive-fabric");
1694 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI);
1695 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC);
1696 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC);
1697 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE);
1698 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER);
1699
1700 chip->num_pecs = pcc->num_pecs;
1701
1702 for (i = 0; i < chip->num_pecs; i++) {
1703 object_initialize_child(obj, "pec[*]", &chip10->pecs[i],
1704 TYPE_PNV_PHB5_PEC);
1705 }
1706 }
1707
1708 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
1709 {
1710 PnvChip *chip = PNV_CHIP(chip10);
1711 int i;
1712
1713 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1714 chip10->quads = g_new0(PnvQuad, chip10->nr_quads);
1715
1716 for (i = 0; i < chip10->nr_quads; i++) {
1717 PnvQuad *eq = &chip10->quads[i];
1718
1719 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
1720
1721 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
1722 &eq->xscom_regs);
1723 }
1724 }
1725
1726 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp)
1727 {
1728 Pnv10Chip *chip10 = PNV10_CHIP(chip);
1729 int i;
1730
1731 for (i = 0; i < chip->num_pecs; i++) {
1732 PnvPhb4PecState *pec = &chip10->pecs[i];
1733 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1734 uint32_t pec_nest_base;
1735 uint32_t pec_pci_base;
1736
1737 object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
1738 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
1739 &error_fatal);
1740 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
1741 &error_fatal);
1742 if (!qdev_realize(DEVICE(pec), NULL, errp)) {
1743 return;
1744 }
1745
1746 pec_nest_base = pecc->xscom_nest_base(pec);
1747 pec_pci_base = pecc->xscom_pci_base(pec);
1748
1749 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
1750 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
1751 }
1752 }
1753
1754 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
1755 {
1756 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1757 PnvChip *chip = PNV_CHIP(dev);
1758 Pnv10Chip *chip10 = PNV10_CHIP(dev);
1759 Error *local_err = NULL;
1760
1761 /* XSCOM bridge is first */
1762 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err);
1763 if (local_err) {
1764 error_propagate(errp, local_err);
1765 return;
1766 }
1767 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip));
1768
1769 pcc->parent_realize(dev, &local_err);
1770 if (local_err) {
1771 error_propagate(errp, local_err);
1772 return;
1773 }
1774
1775 pnv_chip_power10_quad_realize(chip10, &local_err);
1776 if (local_err) {
1777 error_propagate(errp, local_err);
1778 return;
1779 }
1780
1781 /* XIVE2 interrupt controller (POWER10) */
1782 object_property_set_int(OBJECT(&chip10->xive), "ic-bar",
1783 PNV10_XIVE2_IC_BASE(chip), &error_fatal);
1784 object_property_set_int(OBJECT(&chip10->xive), "esb-bar",
1785 PNV10_XIVE2_ESB_BASE(chip), &error_fatal);
1786 object_property_set_int(OBJECT(&chip10->xive), "end-bar",
1787 PNV10_XIVE2_END_BASE(chip), &error_fatal);
1788 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar",
1789 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal);
1790 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar",
1791 PNV10_XIVE2_NVC_BASE(chip), &error_fatal);
1792 object_property_set_int(OBJECT(&chip10->xive), "tm-bar",
1793 PNV10_XIVE2_TM_BASE(chip), &error_fatal);
1794 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip),
1795 &error_abort);
1796 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) {
1797 return;
1798 }
1799 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE,
1800 &chip10->xive.xscom_regs);
1801
1802 /* Processor Service Interface (PSI) Host Bridge */
1803 object_property_set_int(OBJECT(&chip10->psi), "bar",
1804 PNV10_PSIHB_BASE(chip), &error_fatal);
1805 /* PSI can now be configured to use 64k ESB pages on POWER10 */
1806 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K,
1807 &error_fatal);
1808 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) {
1809 return;
1810 }
1811 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE,
1812 &PNV_PSI(&chip10->psi)->xscom_regs);
1813
1814 /* LPC */
1815 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) {
1816 return;
1817 }
1818 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
1819 &chip10->lpc.xscom_regs);
1820
1821 chip->fw_mr = &chip10->lpc.isa_fw;
1822 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1823 (uint64_t) PNV10_LPCM_BASE(chip));
1824
1825 /* Create the simplified OCC model */
1826 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) {
1827 return;
1828 }
1829 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE,
1830 &chip10->occ.xscom_regs);
1831 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in(
1832 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC));
1833
1834 /* OCC SRAM model */
1835 memory_region_add_subregion(get_system_memory(),
1836 PNV10_OCC_SENSOR_BASE(chip),
1837 &chip10->occ.sram_regs);
1838
1839 /* SBE */
1840 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) {
1841 return;
1842 }
1843 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE,
1844 &chip10->sbe.xscom_ctrl_regs);
1845 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE,
1846 &chip10->sbe.xscom_mbox_regs);
1847 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in(
1848 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU));
1849
1850 /* HOMER */
1851 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip),
1852 &error_abort);
1853 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) {
1854 return;
1855 }
1856 /* Homer Xscom region */
1857 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE,
1858 &chip10->homer.pba_regs);
1859
1860 /* Homer mmio region */
1861 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip),
1862 &chip10->homer.regs);
1863
1864 /* PHBs */
1865 pnv_chip_power10_phb_realize(chip, &local_err);
1866 if (local_err) {
1867 error_propagate(errp, local_err);
1868 return;
1869 }
1870 }
1871
1872 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
1873 {
1874 addr &= (PNV10_XSCOM_SIZE - 1);
1875 return addr >> 3;
1876 }
1877
1878 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
1879 {
1880 DeviceClass *dc = DEVICE_CLASS(klass);
1881 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1882
1883 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
1884 k->cores_mask = POWER10_CORE_MASK;
1885 k->core_pir = pnv_chip_core_pir_p10;
1886 k->intc_create = pnv_chip_power10_intc_create;
1887 k->intc_reset = pnv_chip_power10_intc_reset;
1888 k->intc_destroy = pnv_chip_power10_intc_destroy;
1889 k->intc_print_info = pnv_chip_power10_intc_print_info;
1890 k->isa_create = pnv_chip_power10_isa_create;
1891 k->dt_populate = pnv_chip_power10_dt_populate;
1892 k->pic_print_info = pnv_chip_power10_pic_print_info;
1893 k->xscom_core_base = pnv_chip_power10_xscom_core_base;
1894 k->xscom_pcba = pnv_chip_power10_xscom_pcba;
1895 dc->desc = "PowerNV Chip POWER10";
1896 k->num_pecs = PNV10_CHIP_MAX_PEC;
1897
1898 device_class_set_parent_realize(dc, pnv_chip_power10_realize,
1899 &k->parent_realize);
1900 }
1901
1902 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
1903 {
1904 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1905 int cores_max;
1906
1907 /*
1908 * No custom mask for this chip, let's use the default one from *
1909 * the chip class
1910 */
1911 if (!chip->cores_mask) {
1912 chip->cores_mask = pcc->cores_mask;
1913 }
1914
1915 /* filter alien core ids ! some are reserved */
1916 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
1917 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
1918 chip->cores_mask);
1919 return;
1920 }
1921 chip->cores_mask &= pcc->cores_mask;
1922
1923 /* now that we have a sane layout, let check the number of cores */
1924 cores_max = ctpop64(chip->cores_mask);
1925 if (chip->nr_cores > cores_max) {
1926 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
1927 cores_max);
1928 return;
1929 }
1930 }
1931
1932 static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
1933 {
1934 Error *error = NULL;
1935 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1936 const char *typename = pnv_chip_core_typename(chip);
1937 int i, core_hwid;
1938 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
1939
1940 if (!object_class_by_name(typename)) {
1941 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
1942 return;
1943 }
1944
1945 /* Cores */
1946 pnv_chip_core_sanitize(chip, &error);
1947 if (error) {
1948 error_propagate(errp, error);
1949 return;
1950 }
1951
1952 chip->cores = g_new0(PnvCore *, chip->nr_cores);
1953
1954 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
1955 && (i < chip->nr_cores); core_hwid++) {
1956 char core_name[32];
1957 PnvCore *pnv_core;
1958 uint64_t xscom_core_base;
1959
1960 if (!(chip->cores_mask & (1ull << core_hwid))) {
1961 continue;
1962 }
1963
1964 pnv_core = PNV_CORE(object_new(typename));
1965
1966 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
1967 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core));
1968 chip->cores[i] = pnv_core;
1969 object_property_set_int(OBJECT(pnv_core), "nr-threads",
1970 chip->nr_threads, &error_fatal);
1971 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID,
1972 core_hwid, &error_fatal);
1973 object_property_set_int(OBJECT(pnv_core), "pir",
1974 pcc->core_pir(chip, core_hwid), &error_fatal);
1975 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr,
1976 &error_fatal);
1977 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip),
1978 &error_abort);
1979 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal);
1980
1981 /* Each core has an XSCOM MMIO region */
1982 xscom_core_base = pcc->xscom_core_base(chip, core_hwid);
1983
1984 pnv_xscom_add_subregion(chip, xscom_core_base,
1985 &pnv_core->xscom_regs);
1986 i++;
1987 }
1988 }
1989
1990 static void pnv_chip_realize(DeviceState *dev, Error **errp)
1991 {
1992 PnvChip *chip = PNV_CHIP(dev);
1993 Error *error = NULL;
1994
1995 /* Cores */
1996 pnv_chip_core_realize(chip, &error);
1997 if (error) {
1998 error_propagate(errp, error);
1999 return;
2000 }
2001 }
2002
2003 static Property pnv_chip_properties[] = {
2004 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
2005 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
2006 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
2007 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
2008 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
2009 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1),
2010 DEFINE_PROP_END_OF_LIST(),
2011 };
2012
2013 static void pnv_chip_class_init(ObjectClass *klass, void *data)
2014 {
2015 DeviceClass *dc = DEVICE_CLASS(klass);
2016
2017 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
2018 dc->realize = pnv_chip_realize;
2019 device_class_set_props(dc, pnv_chip_properties);
2020 dc->desc = "PowerNV Chip";
2021 }
2022
2023 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
2024 {
2025 int i, j;
2026
2027 for (i = 0; i < chip->nr_cores; i++) {
2028 PnvCore *pc = chip->cores[i];
2029 CPUCore *cc = CPU_CORE(pc);
2030
2031 for (j = 0; j < cc->nr_threads; j++) {
2032 if (ppc_cpu_pir(pc->threads[j]) == pir) {
2033 return pc->threads[j];
2034 }
2035 }
2036 }
2037 return NULL;
2038 }
2039
2040 static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
2041 {
2042 PnvMachineState *pnv = PNV_MACHINE(xi);
2043 int i, j;
2044
2045 for (i = 0; i < pnv->num_chips; i++) {
2046 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
2047
2048 if (ics_valid_irq(&chip8->psi.ics, irq)) {
2049 return &chip8->psi.ics;
2050 }
2051
2052 for (j = 0; j < chip8->num_phbs; j++) {
2053 PnvPHB *phb = chip8->phbs[j];
2054 PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
2055
2056 if (ics_valid_irq(&phb3->lsis, irq)) {
2057 return &phb3->lsis;
2058 }
2059
2060 if (ics_valid_irq(ICS(&phb3->msis), irq)) {
2061 return ICS(&phb3->msis);
2062 }
2063 }
2064 }
2065 return NULL;
2066 }
2067
2068 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id)
2069 {
2070 int i;
2071
2072 for (i = 0; i < pnv->num_chips; i++) {
2073 PnvChip *chip = pnv->chips[i];
2074 if (chip->chip_id == chip_id) {
2075 return chip;
2076 }
2077 }
2078 return NULL;
2079 }
2080
2081 static void pnv_ics_resend(XICSFabric *xi)
2082 {
2083 PnvMachineState *pnv = PNV_MACHINE(xi);
2084 int i, j;
2085
2086 for (i = 0; i < pnv->num_chips; i++) {
2087 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
2088
2089 ics_resend(&chip8->psi.ics);
2090
2091 for (j = 0; j < chip8->num_phbs; j++) {
2092 PnvPHB *phb = chip8->phbs[j];
2093 PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
2094
2095 ics_resend(&phb3->lsis);
2096 ics_resend(ICS(&phb3->msis));
2097 }
2098 }
2099 }
2100
2101 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
2102 {
2103 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
2104
2105 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
2106 }
2107
2108 static void pnv_pic_print_info(InterruptStatsProvider *obj,
2109 Monitor *mon)
2110 {
2111 PnvMachineState *pnv = PNV_MACHINE(obj);
2112 int i;
2113 CPUState *cs;
2114
2115 CPU_FOREACH(cs) {
2116 PowerPCCPU *cpu = POWERPC_CPU(cs);
2117
2118 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */
2119 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu,
2120 mon);
2121 }
2122
2123 for (i = 0; i < pnv->num_chips; i++) {
2124 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon);
2125 }
2126 }
2127
2128 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
2129 uint8_t nvt_blk, uint32_t nvt_idx,
2130 bool cam_ignore, uint8_t priority,
2131 uint32_t logic_serv,
2132 XiveTCTXMatch *match)
2133 {
2134 PnvMachineState *pnv = PNV_MACHINE(xfb);
2135 int total_count = 0;
2136 int i;
2137
2138 for (i = 0; i < pnv->num_chips; i++) {
2139 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
2140 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive);
2141 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
2142 int count;
2143
2144 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
2145 priority, logic_serv, match);
2146
2147 if (count < 0) {
2148 return count;
2149 }
2150
2151 total_count += count;
2152 }
2153
2154 return total_count;
2155 }
2156
2157 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format,
2158 uint8_t nvt_blk, uint32_t nvt_idx,
2159 bool cam_ignore, uint8_t priority,
2160 uint32_t logic_serv,
2161 XiveTCTXMatch *match)
2162 {
2163 PnvMachineState *pnv = PNV_MACHINE(xfb);
2164 int total_count = 0;
2165 int i;
2166
2167 for (i = 0; i < pnv->num_chips; i++) {
2168 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]);
2169 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive);
2170 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
2171 int count;
2172
2173 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
2174 priority, logic_serv, match);
2175
2176 if (count < 0) {
2177 return count;
2178 }
2179
2180 total_count += count;
2181 }
2182
2183 return total_count;
2184 }
2185
2186 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
2187 {
2188 MachineClass *mc = MACHINE_CLASS(oc);
2189 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
2190 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2191 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
2192
2193 static GlobalProperty phb_compat[] = {
2194 { TYPE_PNV_PHB, "version", "3" },
2195 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" },
2196 };
2197
2198 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
2199 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
2200 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
2201
2202 xic->icp_get = pnv_icp_get;
2203 xic->ics_get = pnv_ics_get;
2204 xic->ics_resend = pnv_ics_resend;
2205
2206 pmc->compat = compat;
2207 pmc->compat_size = sizeof(compat);
2208
2209 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
2210 }
2211
2212 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
2213 {
2214 MachineClass *mc = MACHINE_CLASS(oc);
2215 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
2216 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2217 static const char compat[] = "qemu,powernv9\0ibm,powernv";
2218
2219 static GlobalProperty phb_compat[] = {
2220 { TYPE_PNV_PHB, "version", "4" },
2221 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" },
2222 };
2223
2224 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
2225 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
2226 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
2227
2228 xfc->match_nvt = pnv_match_nvt;
2229
2230 mc->alias = "powernv";
2231
2232 pmc->compat = compat;
2233 pmc->compat_size = sizeof(compat);
2234 pmc->dt_power_mgt = pnv_dt_power_mgt;
2235
2236 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
2237 }
2238
2239 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
2240 {
2241 MachineClass *mc = MACHINE_CLASS(oc);
2242 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2243 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
2244 static const char compat[] = "qemu,powernv10\0ibm,powernv";
2245
2246 static GlobalProperty phb_compat[] = {
2247 { TYPE_PNV_PHB, "version", "5" },
2248 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" },
2249 };
2250
2251 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
2252 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
2253 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
2254
2255 pmc->compat = compat;
2256 pmc->compat_size = sizeof(compat);
2257 pmc->dt_power_mgt = pnv_dt_power_mgt;
2258
2259 xfc->match_nvt = pnv10_xive_match_nvt;
2260
2261 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
2262 }
2263
2264 static bool pnv_machine_get_hb(Object *obj, Error **errp)
2265 {
2266 PnvMachineState *pnv = PNV_MACHINE(obj);
2267
2268 return !!pnv->fw_load_addr;
2269 }
2270
2271 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp)
2272 {
2273 PnvMachineState *pnv = PNV_MACHINE(obj);
2274
2275 if (value) {
2276 pnv->fw_load_addr = 0x8000000;
2277 }
2278 }
2279
2280 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
2281 {
2282 PowerPCCPU *cpu = POWERPC_CPU(cs);
2283 CPUPPCState *env = &cpu->env;
2284
2285 cpu_synchronize_state(cs);
2286 ppc_cpu_do_system_reset(cs);
2287 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) {
2288 /*
2289 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the
2290 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100
2291 * (PPC_BIT(43)).
2292 */
2293 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) {
2294 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason");
2295 env->spr[SPR_SRR1] |= SRR1_WAKERESET;
2296 }
2297 } else {
2298 /*
2299 * For non-powersave system resets, SRR1[42:45] are defined to be
2300 * implementation-dependent. The POWER9 User Manual specifies that
2301 * an external (SCOM driven, which may come from a BMC nmi command or
2302 * another CPU requesting a NMI IPI) system reset exception should be
2303 * 0b0010 (PPC_BIT(44)).
2304 */
2305 env->spr[SPR_SRR1] |= SRR1_WAKESCOM;
2306 }
2307 }
2308
2309 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
2310 {
2311 CPUState *cs;
2312
2313 CPU_FOREACH(cs) {
2314 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
2315 }
2316 }
2317
2318 static void pnv_machine_class_init(ObjectClass *oc, void *data)
2319 {
2320 MachineClass *mc = MACHINE_CLASS(oc);
2321 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
2322 NMIClass *nc = NMI_CLASS(oc);
2323
2324 mc->desc = "IBM PowerNV (Non-Virtualized)";
2325 mc->init = pnv_init;
2326 mc->reset = pnv_reset;
2327 mc->max_cpus = MAX_CPUS;
2328 /* Pnv provides a AHCI device for storage */
2329 mc->block_default_type = IF_IDE;
2330 mc->no_parallel = 1;
2331 mc->default_boot_order = NULL;
2332 /*
2333 * RAM defaults to less than 2048 for 32-bit hosts, and large
2334 * enough to fit the maximum initrd size at it's load address
2335 */
2336 mc->default_ram_size = 1 * GiB;
2337 mc->default_ram_id = "pnv.ram";
2338 ispc->print_info = pnv_pic_print_info;
2339 nc->nmi_monitor_handler = pnv_nmi;
2340
2341 object_class_property_add_bool(oc, "hb-mode",
2342 pnv_machine_get_hb, pnv_machine_set_hb);
2343 object_class_property_set_description(oc, "hb-mode",
2344 "Use a hostboot like boot loader");
2345 }
2346
2347 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
2348 { \
2349 .name = type, \
2350 .class_init = class_initfn, \
2351 .parent = TYPE_PNV8_CHIP, \
2352 }
2353
2354 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
2355 { \
2356 .name = type, \
2357 .class_init = class_initfn, \
2358 .parent = TYPE_PNV9_CHIP, \
2359 }
2360
2361 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
2362 { \
2363 .name = type, \
2364 .class_init = class_initfn, \
2365 .parent = TYPE_PNV10_CHIP, \
2366 }
2367
2368 static const TypeInfo types[] = {
2369 {
2370 .name = MACHINE_TYPE_NAME("powernv10"),
2371 .parent = TYPE_PNV_MACHINE,
2372 .class_init = pnv_machine_power10_class_init,
2373 .interfaces = (InterfaceInfo[]) {
2374 { TYPE_XIVE_FABRIC },
2375 { },
2376 },
2377 },
2378 {
2379 .name = MACHINE_TYPE_NAME("powernv9"),
2380 .parent = TYPE_PNV_MACHINE,
2381 .class_init = pnv_machine_power9_class_init,
2382 .interfaces = (InterfaceInfo[]) {
2383 { TYPE_XIVE_FABRIC },
2384 { },
2385 },
2386 },
2387 {
2388 .name = MACHINE_TYPE_NAME("powernv8"),
2389 .parent = TYPE_PNV_MACHINE,
2390 .class_init = pnv_machine_power8_class_init,
2391 .interfaces = (InterfaceInfo[]) {
2392 { TYPE_XICS_FABRIC },
2393 { },
2394 },
2395 },
2396 {
2397 .name = TYPE_PNV_MACHINE,
2398 .parent = TYPE_MACHINE,
2399 .abstract = true,
2400 .instance_size = sizeof(PnvMachineState),
2401 .class_init = pnv_machine_class_init,
2402 .class_size = sizeof(PnvMachineClass),
2403 .interfaces = (InterfaceInfo[]) {
2404 { TYPE_INTERRUPT_STATS_PROVIDER },
2405 { TYPE_NMI },
2406 { },
2407 },
2408 },
2409 {
2410 .name = TYPE_PNV_CHIP,
2411 .parent = TYPE_SYS_BUS_DEVICE,
2412 .class_init = pnv_chip_class_init,
2413 .instance_size = sizeof(PnvChip),
2414 .class_size = sizeof(PnvChipClass),
2415 .abstract = true,
2416 },
2417
2418 /*
2419 * P10 chip and variants
2420 */
2421 {
2422 .name = TYPE_PNV10_CHIP,
2423 .parent = TYPE_PNV_CHIP,
2424 .instance_init = pnv_chip_power10_instance_init,
2425 .instance_size = sizeof(Pnv10Chip),
2426 },
2427 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init),
2428
2429 /*
2430 * P9 chip and variants
2431 */
2432 {
2433 .name = TYPE_PNV9_CHIP,
2434 .parent = TYPE_PNV_CHIP,
2435 .instance_init = pnv_chip_power9_instance_init,
2436 .instance_size = sizeof(Pnv9Chip),
2437 },
2438 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
2439
2440 /*
2441 * P8 chip and variants
2442 */
2443 {
2444 .name = TYPE_PNV8_CHIP,
2445 .parent = TYPE_PNV_CHIP,
2446 .instance_init = pnv_chip_power8_instance_init,
2447 .instance_size = sizeof(Pnv8Chip),
2448 },
2449 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
2450 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
2451 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
2452 pnv_chip_power8nvl_class_init),
2453 };
2454
2455 DEFINE_TYPES(types)
AR7 emulation for QEMU