hw/timer/etraxfs_timer.c

   1 /*
   2  * QEMU ETRAX Timers
   3  *
   4  * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/sysbus.h"
  27 #include "sysemu/reset.h"
  28 #include "sysemu/runstate.h"
  29 #include "qemu/module.h"
  30 #include "qemu/timer.h"
  31 #include "hw/irq.h"
  32 #include "hw/ptimer.h"
  33 #include "qom/object.h"
  34
  35 #define D(x)
  36
  37 #define RW_TMR0_DIV   0x00
  38 #define R_TMR0_DATA   0x04
  39 #define RW_TMR0_CTRL  0x08
  40 #define RW_TMR1_DIV   0x10
  41 #define R_TMR1_DATA   0x14
  42 #define RW_TMR1_CTRL  0x18
  43 #define R_TIME        0x38
  44 #define RW_WD_CTRL    0x40
  45 #define R_WD_STAT     0x44
  46 #define RW_INTR_MASK  0x48
  47 #define RW_ACK_INTR   0x4c
  48 #define R_INTR        0x50
  49 #define R_MASKED_INTR 0x54
  50
  51 #define TYPE_ETRAX_FS_TIMER "etraxfs,timer"
  52 typedef struct ETRAXTimerState ETRAXTimerState;
  53 DECLARE_INSTANCE_CHECKER(ETRAXTimerState, ETRAX_TIMER,
  54                          TYPE_ETRAX_FS_TIMER)
  55
  56 struct ETRAXTimerState {
  57     SysBusDevice parent_obj;
  58
  59     MemoryRegion mmio;
  60     qemu_irq irq;
  61     qemu_irq nmi;
  62
  63     ptimer_state *ptimer_t0;
  64     ptimer_state *ptimer_t1;
  65     ptimer_state *ptimer_wd;
  66
  67     int wd_hits;
  68
  69     /* Control registers.  */
  70     uint32_t rw_tmr0_div;
  71     uint32_t r_tmr0_data;
  72     uint32_t rw_tmr0_ctrl;
  73
  74     uint32_t rw_tmr1_div;
  75     uint32_t r_tmr1_data;
  76     uint32_t rw_tmr1_ctrl;
  77
  78     uint32_t rw_wd_ctrl;
  79
  80     uint32_t rw_intr_mask;
  81     uint32_t rw_ack_intr;
  82     uint32_t r_intr;
  83     uint32_t r_masked_intr;
  84 };
  85
  86 static uint64_t
  87 timer_read(void *opaque, hwaddr addr, unsigned int size)
  88 {
  89     ETRAXTimerState *t = opaque;
  90     uint32_t r = 0;
  91
  92     switch (addr) {
  93     case R_TMR0_DATA:
  94         r = ptimer_get_count(t->ptimer_t0);
  95         break;
  96     case R_TMR1_DATA:
  97         r = ptimer_get_count(t->ptimer_t1);
  98         break;
  99     case R_TIME:
 100         r = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 10;
 101         break;
 102     case RW_INTR_MASK:
 103         r = t->rw_intr_mask;
 104         break;
 105     case R_MASKED_INTR:
 106         r = t->r_intr & t->rw_intr_mask;
 107         break;
 108     default:
 109         D(printf ("%s %x\n", __func__, addr));
 110         break;
 111     }
 112     return r;
 113 }
 114
 115 static void update_ctrl(ETRAXTimerState *t, int tnum)
 116 {
 117     unsigned int op;
 118     unsigned int freq;
 119     unsigned int freq_hz;
 120     unsigned int div;
 121     uint32_t ctrl;
 122
 123     ptimer_state *timer;
 124
 125     if (tnum == 0) {
 126         ctrl = t->rw_tmr0_ctrl;
 127         div = t->rw_tmr0_div;
 128         timer = t->ptimer_t0;
 129     } else {
 130         ctrl = t->rw_tmr1_ctrl;
 131         div = t->rw_tmr1_div;
 132         timer = t->ptimer_t1;
 133     }
 134
 135
 136     op = ctrl & 3;
 137     freq = ctrl >> 2;
 138     freq_hz = 32000000;
 139
 140     switch (freq)
 141     {
 142     case 0:
 143     case 1:
 144         D(printf ("extern or disabled timer clock?\n"));
 145         break;
 146     case 4: freq_hz =  29493000; break;
 147     case 5: freq_hz =  32000000; break;
 148     case 6: freq_hz =  32768000; break;
 149     case 7: freq_hz = 100000000; break;
 150     default:
 151         abort();
 152         break;
 153     }
 154
 155     D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
 156     ptimer_transaction_begin(timer);
 157     ptimer_set_freq(timer, freq_hz);
 158     ptimer_set_limit(timer, div, 0);
 159
 160     switch (op)
 161     {
 162         case 0:
 163             /* Load.  */
 164             ptimer_set_limit(timer, div, 1);
 165             break;
 166         case 1:
 167             /* Hold.  */
 168             ptimer_stop(timer);
 169             break;
 170         case 2:
 171             /* Run.  */
 172             ptimer_run(timer, 0);
 173             break;
 174         default:
 175             abort();
 176             break;
 177     }
 178     ptimer_transaction_commit(timer);
 179 }
 180
 181 static void timer_update_irq(ETRAXTimerState *t)
 182 {
 183     t->r_intr &= ~(t->rw_ack_intr);
 184     t->r_masked_intr = t->r_intr & t->rw_intr_mask;
 185
 186     D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
 187     qemu_set_irq(t->irq, !!t->r_masked_intr);
 188 }
 189
 190 static void timer0_hit(void *opaque)
 191 {
 192     ETRAXTimerState *t = opaque;
 193     t->r_intr |= 1;
 194     timer_update_irq(t);
 195 }
 196
 197 static void timer1_hit(void *opaque)
 198 {
 199     ETRAXTimerState *t = opaque;
 200     t->r_intr |= 2;
 201     timer_update_irq(t);
 202 }
 203
 204 static void watchdog_hit(void *opaque)
 205 {
 206     ETRAXTimerState *t = opaque;
 207     if (t->wd_hits == 0) {
 208         /* real hw gives a single tick before reseting but we are
 209            a bit friendlier to compensate for our slower execution.  */
 210         ptimer_set_count(t->ptimer_wd, 10);
 211         ptimer_run(t->ptimer_wd, 1);
 212         qemu_irq_raise(t->nmi);
 213     }
 214     else
 215         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 216
 217     t->wd_hits++;
 218 }
 219
 220 static inline void timer_watchdog_update(ETRAXTimerState *t, uint32_t value)
 221 {
 222     unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
 223     unsigned int wd_key = t->rw_wd_ctrl >> 9;
 224     unsigned int wd_cnt = t->rw_wd_ctrl & 511;
 225     unsigned int new_key = value >> 9 & ((1 << 7) - 1);
 226     unsigned int new_cmd = (value >> 8) & 1;
 227
 228     /* If the watchdog is enabled, they written key must match the
 229        complement of the previous.  */
 230     wd_key = ~wd_key & ((1 << 7) - 1);
 231
 232     if (wd_en && wd_key != new_key)
 233         return;
 234
 235     D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
 236          wd_en, new_key, wd_key, new_cmd, wd_cnt));
 237
 238     if (t->wd_hits)
 239         qemu_irq_lower(t->nmi);
 240
 241     t->wd_hits = 0;
 242
 243     ptimer_transaction_begin(t->ptimer_wd);
 244     ptimer_set_freq(t->ptimer_wd, 760);
 245     if (wd_cnt == 0)
 246         wd_cnt = 256;
 247     ptimer_set_count(t->ptimer_wd, wd_cnt);
 248     if (new_cmd)
 249         ptimer_run(t->ptimer_wd, 1);
 250     else
 251         ptimer_stop(t->ptimer_wd);
 252
 253     t->rw_wd_ctrl = value;
 254     ptimer_transaction_commit(t->ptimer_wd);
 255 }
 256
 257 static void
 258 timer_write(void *opaque, hwaddr addr,
 259             uint64_t val64, unsigned int size)
 260 {
 261     ETRAXTimerState *t = opaque;
 262     uint32_t value = val64;
 263
 264     switch (addr)
 265     {
 266         case RW_TMR0_DIV:
 267             t->rw_tmr0_div = value;
 268             break;
 269         case RW_TMR0_CTRL:
 270             D(printf ("RW_TMR0_CTRL=%x\n", value));
 271             t->rw_tmr0_ctrl = value;
 272             update_ctrl(t, 0);
 273             break;
 274         case RW_TMR1_DIV:
 275             t->rw_tmr1_div = value;
 276             break;
 277         case RW_TMR1_CTRL:
 278             D(printf ("RW_TMR1_CTRL=%x\n", value));
 279             t->rw_tmr1_ctrl = value;
 280             update_ctrl(t, 1);
 281             break;
 282         case RW_INTR_MASK:
 283             D(printf ("RW_INTR_MASK=%x\n", value));
 284             t->rw_intr_mask = value;
 285             timer_update_irq(t);
 286             break;
 287         case RW_WD_CTRL:
 288             timer_watchdog_update(t, value);
 289             break;
 290         case RW_ACK_INTR:
 291             t->rw_ack_intr = value;
 292             timer_update_irq(t);
 293             t->rw_ack_intr = 0;
 294             break;
 295         default:
 296             printf ("%s " TARGET_FMT_plx " %x\n",
 297                 __func__, addr, value);
 298             break;
 299     }
 300 }
 301
 302 static const MemoryRegionOps timer_ops = {
 303     .read = timer_read,
 304     .write = timer_write,
 305     .endianness = DEVICE_LITTLE_ENDIAN,
 306     .valid = {
 307         .min_access_size = 4,
 308         .max_access_size = 4
 309     }
 310 };
 311
 312 static void etraxfs_timer_reset(void *opaque)
 313 {
 314     ETRAXTimerState *t = opaque;
 315
 316     ptimer_transaction_begin(t->ptimer_t0);
 317     ptimer_stop(t->ptimer_t0);
 318     ptimer_transaction_commit(t->ptimer_t0);
 319     ptimer_transaction_begin(t->ptimer_t1);
 320     ptimer_stop(t->ptimer_t1);
 321     ptimer_transaction_commit(t->ptimer_t1);
 322     ptimer_transaction_begin(t->ptimer_wd);
 323     ptimer_stop(t->ptimer_wd);
 324     ptimer_transaction_commit(t->ptimer_wd);
 325     t->rw_wd_ctrl = 0;
 326     t->r_intr = 0;
 327     t->rw_intr_mask = 0;
 328     qemu_irq_lower(t->irq);
 329 }
 330
 331 static void etraxfs_timer_realize(DeviceState *dev, Error **errp)
 332 {
 333     ETRAXTimerState *t = ETRAX_TIMER(dev);
 334     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 335
 336     t->ptimer_t0 = ptimer_init(timer0_hit, t, PTIMER_POLICY_DEFAULT);
 337     t->ptimer_t1 = ptimer_init(timer1_hit, t, PTIMER_POLICY_DEFAULT);
 338     t->ptimer_wd = ptimer_init(watchdog_hit, t, PTIMER_POLICY_DEFAULT);
 339
 340     sysbus_init_irq(sbd, &t->irq);
 341     sysbus_init_irq(sbd, &t->nmi);
 342
 343     memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
 344                           "etraxfs-timer", 0x5c);
 345     sysbus_init_mmio(sbd, &t->mmio);
 346     qemu_register_reset(etraxfs_timer_reset, t);
 347 }
 348
 349 static void etraxfs_timer_class_init(ObjectClass *klass, void *data)
 350 {
 351     DeviceClass *dc = DEVICE_CLASS(klass);
 352
 353     dc->realize = etraxfs_timer_realize;
 354 }
 355
 356 static const TypeInfo etraxfs_timer_info = {
 357     .name          = TYPE_ETRAX_FS_TIMER,
 358     .parent        = TYPE_SYS_BUS_DEVICE,
 359     .instance_size = sizeof(ETRAXTimerState),
 360     .class_init    = etraxfs_timer_class_init,
 361 };
 362
 363 static void etraxfs_timer_register_types(void)
 364 {
 365     type_register_static(&etraxfs_timer_info);
 366 }
 367
 368 type_init(etraxfs_timer_register_types)