hw/elf_ops: Fix a typo
[qemu/ar7.git] / hw / core / cpu.c
blob00330ba07dee0393f864872eb3c7f9396ed93196
1 /*
2 * QEMU CPU model
4 * Copyright (c) 2012-2014 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "hw/core/cpu.h"
24 #include "sysemu/hw_accel.h"
25 #include "qemu/notify.h"
26 #include "qemu/log.h"
27 #include "qemu/main-loop.h"
28 #include "exec/log.h"
29 #include "exec/cpu-common.h"
30 #include "qemu/error-report.h"
31 #include "qemu/qemu-print.h"
32 #include "sysemu/tcg.h"
33 #include "hw/boards.h"
34 #include "hw/qdev-properties.h"
35 #include "trace/trace-root.h"
36 #include "qemu/plugin.h"
37 #include "sysemu/hw_accel.h"
39 CPUState *cpu_by_arch_id(int64_t id)
41 CPUState *cpu;
43 CPU_FOREACH(cpu) {
44 CPUClass *cc = CPU_GET_CLASS(cpu);
46 if (cc->get_arch_id(cpu) == id) {
47 return cpu;
50 return NULL;
53 bool cpu_exists(int64_t id)
55 return !!cpu_by_arch_id(id);
58 CPUState *cpu_create(const char *typename)
60 Error *err = NULL;
61 CPUState *cpu = CPU(object_new(typename));
62 if (!qdev_realize(DEVICE(cpu), NULL, &err)) {
63 error_report_err(err);
64 object_unref(OBJECT(cpu));
65 exit(EXIT_FAILURE);
67 return cpu;
70 bool cpu_paging_enabled(const CPUState *cpu)
72 CPUClass *cc = CPU_GET_CLASS(cpu);
74 return cc->get_paging_enabled(cpu);
77 static bool cpu_common_get_paging_enabled(const CPUState *cpu)
79 return false;
82 void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
83 Error **errp)
85 CPUClass *cc = CPU_GET_CLASS(cpu);
87 cc->get_memory_mapping(cpu, list, errp);
90 static void cpu_common_get_memory_mapping(CPUState *cpu,
91 MemoryMappingList *list,
92 Error **errp)
94 error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
97 /* Resetting the IRQ comes from across the code base so we take the
98 * BQL here if we need to. cpu_interrupt assumes it is held.*/
99 void cpu_reset_interrupt(CPUState *cpu, int mask)
101 bool need_lock = !qemu_mutex_iothread_locked();
103 if (need_lock) {
104 qemu_mutex_lock_iothread();
106 cpu->interrupt_request &= ~mask;
107 if (need_lock) {
108 qemu_mutex_unlock_iothread();
112 void cpu_exit(CPUState *cpu)
114 qatomic_set(&cpu->exit_request, 1);
115 /* Ensure cpu_exec will see the exit request after TCG has exited. */
116 smp_wmb();
117 qatomic_set(&cpu->icount_decr_ptr->u16.high, -1);
120 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
121 void *opaque)
123 CPUClass *cc = CPU_GET_CLASS(cpu);
125 return (*cc->write_elf32_qemunote)(f, cpu, opaque);
128 static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f,
129 CPUState *cpu, void *opaque)
131 return 0;
134 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
135 int cpuid, void *opaque)
137 CPUClass *cc = CPU_GET_CLASS(cpu);
139 return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
142 static int cpu_common_write_elf32_note(WriteCoreDumpFunction f,
143 CPUState *cpu, int cpuid,
144 void *opaque)
146 return -1;
149 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
150 void *opaque)
152 CPUClass *cc = CPU_GET_CLASS(cpu);
154 return (*cc->write_elf64_qemunote)(f, cpu, opaque);
157 static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f,
158 CPUState *cpu, void *opaque)
160 return 0;
163 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
164 int cpuid, void *opaque)
166 CPUClass *cc = CPU_GET_CLASS(cpu);
168 return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
171 static int cpu_common_write_elf64_note(WriteCoreDumpFunction f,
172 CPUState *cpu, int cpuid,
173 void *opaque)
175 return -1;
179 static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)
181 return 0;
184 static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
186 return 0;
189 static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
191 return target_words_bigendian();
195 * XXX the following #if is always true because this is a common_ss
196 * module, so target CONFIG_* is never defined.
198 #if !defined(CONFIG_USER_ONLY)
199 GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
201 CPUClass *cc = CPU_GET_CLASS(cpu);
202 GuestPanicInformation *res = NULL;
204 if (cc->get_crash_info) {
205 res = cc->get_crash_info(cpu);
207 return res;
209 #endif
211 void cpu_dump_state(CPUState *cpu, FILE *f, int flags)
213 CPUClass *cc = CPU_GET_CLASS(cpu);
215 if (cc->dump_state) {
216 cpu_synchronize_state(cpu);
217 cc->dump_state(cpu, f, flags);
221 void cpu_dump_statistics(CPUState *cpu, int flags)
223 CPUClass *cc = CPU_GET_CLASS(cpu);
225 if (cc->dump_statistics) {
226 cc->dump_statistics(cpu, flags);
230 void cpu_reset(CPUState *cpu)
232 device_cold_reset(DEVICE(cpu));
234 trace_guest_cpu_reset(cpu);
237 static void cpu_common_reset(DeviceState *dev)
239 CPUState *cpu = CPU(dev);
240 CPUClass *cc = CPU_GET_CLASS(cpu);
242 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
243 qemu_log("CPU Reset (CPU %d)\n", cpu->cpu_index);
244 log_cpu_state(cpu, cc->reset_dump_flags);
247 cpu->interrupt_request = 0;
248 cpu->halted = cpu->start_powered_off;
249 cpu->mem_io_pc = 0;
250 cpu->icount_extra = 0;
251 qatomic_set(&cpu->icount_decr_ptr->u32, 0);
252 cpu->can_do_io = 1;
253 cpu->exception_index = -1;
254 cpu->crash_occurred = false;
255 cpu->cflags_next_tb = -1;
257 if (tcg_enabled()) {
258 cpu_tb_jmp_cache_clear(cpu);
260 tcg_flush_softmmu_tlb(cpu);
264 static bool cpu_common_has_work(CPUState *cs)
266 return false;
269 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
271 CPUClass *cc = CPU_CLASS(object_class_by_name(typename));
273 assert(cpu_model && cc->class_by_name);
274 return cc->class_by_name(cpu_model);
277 static void cpu_common_parse_features(const char *typename, char *features,
278 Error **errp)
280 char *val;
281 static bool cpu_globals_initialized;
282 /* Single "key=value" string being parsed */
283 char *featurestr = features ? strtok(features, ",") : NULL;
285 /* should be called only once, catch invalid users */
286 assert(!cpu_globals_initialized);
287 cpu_globals_initialized = true;
289 while (featurestr) {
290 val = strchr(featurestr, '=');
291 if (val) {
292 GlobalProperty *prop = g_new0(typeof(*prop), 1);
293 *val = 0;
294 val++;
295 prop->driver = typename;
296 prop->property = g_strdup(featurestr);
297 prop->value = g_strdup(val);
298 qdev_prop_register_global(prop);
299 } else {
300 error_setg(errp, "Expected key=value format, found %s.",
301 featurestr);
302 return;
304 featurestr = strtok(NULL, ",");
308 static void cpu_common_realizefn(DeviceState *dev, Error **errp)
310 CPUState *cpu = CPU(dev);
311 Object *machine = qdev_get_machine();
313 /* qdev_get_machine() can return something that's not TYPE_MACHINE
314 * if this is one of the user-only emulators; in that case there's
315 * no need to check the ignore_memory_transaction_failures board flag.
317 if (object_dynamic_cast(machine, TYPE_MACHINE)) {
318 ObjectClass *oc = object_get_class(machine);
319 MachineClass *mc = MACHINE_CLASS(oc);
321 if (mc) {
322 cpu->ignore_memory_transaction_failures =
323 mc->ignore_memory_transaction_failures;
327 if (dev->hotplugged) {
328 cpu_synchronize_post_init(cpu);
329 cpu_resume(cpu);
332 /* NOTE: latest generic point where the cpu is fully realized */
333 trace_init_vcpu(cpu);
336 static void cpu_common_unrealizefn(DeviceState *dev)
338 CPUState *cpu = CPU(dev);
340 /* NOTE: latest generic point before the cpu is fully unrealized */
341 trace_fini_vcpu(cpu);
342 cpu_exec_unrealizefn(cpu);
345 static void cpu_common_initfn(Object *obj)
347 CPUState *cpu = CPU(obj);
348 CPUClass *cc = CPU_GET_CLASS(obj);
350 cpu->cpu_index = UNASSIGNED_CPU_INDEX;
351 cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX;
352 cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;
353 /* *-user doesn't have configurable SMP topology */
354 /* the default value is changed by qemu_init_vcpu() for softmmu */
355 cpu->nr_cores = 1;
356 cpu->nr_threads = 1;
358 qemu_mutex_init(&cpu->work_mutex);
359 QSIMPLEQ_INIT(&cpu->work_list);
360 QTAILQ_INIT(&cpu->breakpoints);
361 QTAILQ_INIT(&cpu->watchpoints);
363 cpu_exec_initfn(cpu);
366 static void cpu_common_finalize(Object *obj)
368 CPUState *cpu = CPU(obj);
370 qemu_mutex_destroy(&cpu->work_mutex);
373 static int64_t cpu_common_get_arch_id(CPUState *cpu)
375 return cpu->cpu_index;
378 static Property cpu_common_props[] = {
379 #ifndef CONFIG_USER_ONLY
380 /* Create a memory property for softmmu CPU object,
381 * so users can wire up its memory. (This can't go in hw/core/cpu.c
382 * because that file is compiled only once for both user-mode
383 * and system builds.) The default if no link is set up is to use
384 * the system address space.
386 DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
387 MemoryRegion *),
388 #endif
389 DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
390 DEFINE_PROP_END_OF_LIST(),
393 static void cpu_class_init(ObjectClass *klass, void *data)
395 DeviceClass *dc = DEVICE_CLASS(klass);
396 CPUClass *k = CPU_CLASS(klass);
398 k->parse_features = cpu_common_parse_features;
399 k->get_arch_id = cpu_common_get_arch_id;
400 k->has_work = cpu_common_has_work;
401 k->get_paging_enabled = cpu_common_get_paging_enabled;
402 k->get_memory_mapping = cpu_common_get_memory_mapping;
403 k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
404 k->write_elf32_note = cpu_common_write_elf32_note;
405 k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
406 k->write_elf64_note = cpu_common_write_elf64_note;
407 k->gdb_read_register = cpu_common_gdb_read_register;
408 k->gdb_write_register = cpu_common_gdb_write_register;
409 k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
410 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
411 dc->realize = cpu_common_realizefn;
412 dc->unrealize = cpu_common_unrealizefn;
413 dc->reset = cpu_common_reset;
414 device_class_set_props(dc, cpu_common_props);
416 * Reason: CPUs still need special care by board code: wiring up
417 * IRQs, adding reset handlers, halting non-first CPUs, ...
419 dc->user_creatable = false;
422 static const TypeInfo cpu_type_info = {
423 .name = TYPE_CPU,
424 .parent = TYPE_DEVICE,
425 .instance_size = sizeof(CPUState),
426 .instance_init = cpu_common_initfn,
427 .instance_finalize = cpu_common_finalize,
428 .abstract = true,
429 .class_size = sizeof(CPUClass),
430 .class_init = cpu_class_init,
433 static void cpu_register_types(void)
435 type_register_static(&cpu_type_info);
438 type_init(cpu_register_types)