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cirrus: replace debug printf with trace points
[qemu/ar7.git] / hw / display / cirrus_vga.c
blobb272a70d60d14ee0b7bb6c84c3e909073183dd6a
1 /*
2 * QEMU Cirrus CLGD 54xx VGA Emulator.
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
29 #include "qemu/osdep.h"
30 #include "qapi/error.h"
31 #include "trace.h"
32 #include "hw/hw.h"
33 #include "hw/pci/pci.h"
34 #include "ui/console.h"
35 #include "ui/pixel_ops.h"
36 #include "vga_int.h"
37 #include "hw/loader.h"
38
39 /*
40 * TODO:
41 * - destination write mask support not complete (bits 5..7)
42 * - optimize linear mappings
43 * - optimize bitblt functions
44 */
45
46 //#define DEBUG_CIRRUS
47 //#define DEBUG_BITBLT
48
49 /***************************************
50 *
51 * definitions
52 *
53 ***************************************/
54
55 // ID
56 #define CIRRUS_ID_CLGD5422 (0x23<<2)
57 #define CIRRUS_ID_CLGD5426 (0x24<<2)
58 #define CIRRUS_ID_CLGD5424 (0x25<<2)
59 #define CIRRUS_ID_CLGD5428 (0x26<<2)
60 #define CIRRUS_ID_CLGD5430 (0x28<<2)
61 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
62 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
63 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
64
65 // sequencer 0x07
66 #define CIRRUS_SR7_BPP_VGA 0x00
67 #define CIRRUS_SR7_BPP_SVGA 0x01
68 #define CIRRUS_SR7_BPP_MASK 0x0e
69 #define CIRRUS_SR7_BPP_8 0x00
70 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
71 #define CIRRUS_SR7_BPP_24 0x04
72 #define CIRRUS_SR7_BPP_16 0x06
73 #define CIRRUS_SR7_BPP_32 0x08
74 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
75
76 // sequencer 0x0f
77 #define CIRRUS_MEMSIZE_512k 0x08
78 #define CIRRUS_MEMSIZE_1M 0x10
79 #define CIRRUS_MEMSIZE_2M 0x18
80 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
81
82 // sequencer 0x12
83 #define CIRRUS_CURSOR_SHOW 0x01
84 #define CIRRUS_CURSOR_HIDDENPEL 0x02
85 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
86
87 // sequencer 0x17
88 #define CIRRUS_BUSTYPE_VLBFAST 0x10
89 #define CIRRUS_BUSTYPE_PCI 0x20
90 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
91 #define CIRRUS_BUSTYPE_ISA 0x38
92 #define CIRRUS_MMIO_ENABLE 0x04
93 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
94 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
95
96 // control 0x0b
97 #define CIRRUS_BANKING_DUAL 0x01
98 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
99
100 // control 0x30
101 #define CIRRUS_BLTMODE_BACKWARDS 0x01
102 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
103 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
104 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
105 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
106 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
107 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
108 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
109 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
110 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
111 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
112
113 // control 0x31
114 #define CIRRUS_BLT_BUSY 0x01
115 #define CIRRUS_BLT_START 0x02
116 #define CIRRUS_BLT_RESET 0x04
117 #define CIRRUS_BLT_FIFOUSED 0x10
118 #define CIRRUS_BLT_AUTOSTART 0x80
119
120 // control 0x32
121 #define CIRRUS_ROP_0 0x00
122 #define CIRRUS_ROP_SRC_AND_DST 0x05
123 #define CIRRUS_ROP_NOP 0x06
124 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
125 #define CIRRUS_ROP_NOTDST 0x0b
126 #define CIRRUS_ROP_SRC 0x0d
127 #define CIRRUS_ROP_1 0x0e
128 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
129 #define CIRRUS_ROP_SRC_XOR_DST 0x59
130 #define CIRRUS_ROP_SRC_OR_DST 0x6d
131 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
132 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
133 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
134 #define CIRRUS_ROP_NOTSRC 0xd0
135 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
136 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
137
138 #define CIRRUS_ROP_NOP_INDEX 2
139 #define CIRRUS_ROP_SRC_INDEX 5
140
141 // control 0x33
142 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
143 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
144 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
145
146 // memory-mapped IO
147 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
148 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
149 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
150 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
151 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
152 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
153 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
154 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
155 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
156 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
157 #define CIRRUS_MMIO_BLTROP 0x1a // byte
158 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
159 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
160 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
161 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
162 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
163 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
164 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
166 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
167 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
168 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
169 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
170 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
171 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
172 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
173 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
174 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
175 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
176
177 #define CIRRUS_PNPMMIO_SIZE 0x1000
178
179 struct CirrusVGAState;
180 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
181 uint8_t * dst, const uint8_t * src,
182 int dstpitch, int srcpitch,
183 int bltwidth, int bltheight);
184 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
185 uint8_t *dst, int dst_pitch, int width, int height);
186
187 typedef struct CirrusVGAState {
188 VGACommonState vga;
189
190 MemoryRegion cirrus_vga_io;
191 MemoryRegion cirrus_linear_io;
192 MemoryRegion cirrus_linear_bitblt_io;
193 MemoryRegion cirrus_mmio_io;
194 MemoryRegion pci_bar;
195 bool linear_vram; /* vga.vram mapped over cirrus_linear_io */
196 MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */
197 MemoryRegion low_mem; /* always mapped, overridden by: */
198 MemoryRegion cirrus_bank[2]; /* aliases at 0xa0000-0xb0000 */
199 uint32_t cirrus_addr_mask;
200 uint32_t linear_mmio_mask;
201 uint8_t cirrus_shadow_gr0;
202 uint8_t cirrus_shadow_gr1;
203 uint8_t cirrus_hidden_dac_lockindex;
204 uint8_t cirrus_hidden_dac_data;
205 uint32_t cirrus_bank_base[2];
206 uint32_t cirrus_bank_limit[2];
207 uint8_t cirrus_hidden_palette[48];
208 int cirrus_blt_pixelwidth;
209 int cirrus_blt_width;
210 int cirrus_blt_height;
211 int cirrus_blt_dstpitch;
212 int cirrus_blt_srcpitch;
213 uint32_t cirrus_blt_fgcol;
214 uint32_t cirrus_blt_bgcol;
215 uint32_t cirrus_blt_dstaddr;
216 uint32_t cirrus_blt_srcaddr;
217 uint8_t cirrus_blt_mode;
218 uint8_t cirrus_blt_modeext;
219 cirrus_bitblt_rop_t cirrus_rop;
220 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
221 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
222 uint8_t *cirrus_srcptr;
223 uint8_t *cirrus_srcptr_end;
224 uint32_t cirrus_srccounter;
225 /* hwcursor display state */
226 int last_hw_cursor_size;
227 int last_hw_cursor_x;
228 int last_hw_cursor_y;
229 int last_hw_cursor_y_start;
230 int last_hw_cursor_y_end;
231 int real_vram_size; /* XXX: suppress that */
232 int device_id;
233 int bustype;
234 } CirrusVGAState;
235
236 typedef struct PCICirrusVGAState {
237 PCIDevice dev;
238 CirrusVGAState cirrus_vga;
239 } PCICirrusVGAState;
240
241 #define TYPE_PCI_CIRRUS_VGA "cirrus-vga"
242 #define PCI_CIRRUS_VGA(obj) \
243 OBJECT_CHECK(PCICirrusVGAState, (obj), TYPE_PCI_CIRRUS_VGA)
244
245 #define TYPE_ISA_CIRRUS_VGA "isa-cirrus-vga"
246 #define ISA_CIRRUS_VGA(obj) \
247 OBJECT_CHECK(ISACirrusVGAState, (obj), TYPE_ISA_CIRRUS_VGA)
248
249 typedef struct ISACirrusVGAState {
250 ISADevice parent_obj;
251
252 CirrusVGAState cirrus_vga;
253 } ISACirrusVGAState;
254
255 static uint8_t rop_to_index[256];
256
257 /***************************************
258 *
259 * prototypes.
260 *
261 ***************************************/
262
263
264 static void cirrus_bitblt_reset(CirrusVGAState *s);
265 static void cirrus_update_memory_access(CirrusVGAState *s);
266
267 /***************************************
268 *
269 * raster operations
270 *
271 ***************************************/
272
273 static bool blit_region_is_unsafe(struct CirrusVGAState *s,
274 int32_t pitch, int32_t addr)
275 {
276 if (pitch < 0) {
277 int64_t min = addr
278 + ((int64_t)s->cirrus_blt_height - 1) * pitch
279 - s->cirrus_blt_width;
280 if (min < -1 || addr >= s->vga.vram_size) {
281 return true;
282 }
283 } else {
284 int64_t max = addr
285 + ((int64_t)s->cirrus_blt_height-1) * pitch
286 + s->cirrus_blt_width;
287 if (max > s->vga.vram_size) {
288 return true;
289 }
290 }
291 return false;
292 }
293
294 static bool blit_is_unsafe(struct CirrusVGAState *s, bool dst_only,
295 bool zero_src_pitch_ok)
296 {
297 int32_t check_pitch;
298
299 /* should be the case, see cirrus_bitblt_start */
300 assert(s->cirrus_blt_width > 0);
301 assert(s->cirrus_blt_height > 0);
302
303 if (s->cirrus_blt_width > CIRRUS_BLTBUFSIZE) {
304 return true;
305 }
306
307 if (!s->cirrus_blt_dstpitch) {
308 return true;
309 }
310
311 if (blit_region_is_unsafe(s, s->cirrus_blt_dstpitch,
312 s->cirrus_blt_dstaddr)) {
313 return true;
314 }
315 if (dst_only) {
316 return false;
317 }
318
319 check_pitch = s->cirrus_blt_srcpitch;
320 if (!zero_src_pitch_ok && !check_pitch) {
321 check_pitch = s->cirrus_blt_width;
322 }
323
324 if (blit_region_is_unsafe(s, check_pitch,
325 s->cirrus_blt_srcaddr)) {
326 return true;
327 }
328
329 return false;
330 }
331
332 static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
333 uint8_t *dst,const uint8_t *src,
334 int dstpitch,int srcpitch,
335 int bltwidth,int bltheight)
336 {
337 }
338
339 static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
340 uint8_t *dst,
341 int dstpitch, int bltwidth,int bltheight)
342 {
343 }
344
345 #define ROP_NAME 0
346 #define ROP_FN(d, s) 0
347 #include "cirrus_vga_rop.h"
348
349 #define ROP_NAME src_and_dst
350 #define ROP_FN(d, s) (s) & (d)
351 #include "cirrus_vga_rop.h"
352
353 #define ROP_NAME src_and_notdst
354 #define ROP_FN(d, s) (s) & (~(d))
355 #include "cirrus_vga_rop.h"
356
357 #define ROP_NAME notdst
358 #define ROP_FN(d, s) ~(d)
359 #include "cirrus_vga_rop.h"
360
361 #define ROP_NAME src
362 #define ROP_FN(d, s) s
363 #include "cirrus_vga_rop.h"
364
365 #define ROP_NAME 1
366 #define ROP_FN(d, s) ~0
367 #include "cirrus_vga_rop.h"
368
369 #define ROP_NAME notsrc_and_dst
370 #define ROP_FN(d, s) (~(s)) & (d)
371 #include "cirrus_vga_rop.h"
372
373 #define ROP_NAME src_xor_dst
374 #define ROP_FN(d, s) (s) ^ (d)
375 #include "cirrus_vga_rop.h"
376
377 #define ROP_NAME src_or_dst
378 #define ROP_FN(d, s) (s) | (d)
379 #include "cirrus_vga_rop.h"
380
381 #define ROP_NAME notsrc_or_notdst
382 #define ROP_FN(d, s) (~(s)) | (~(d))
383 #include "cirrus_vga_rop.h"
384
385 #define ROP_NAME src_notxor_dst
386 #define ROP_FN(d, s) ~((s) ^ (d))
387 #include "cirrus_vga_rop.h"
388
389 #define ROP_NAME src_or_notdst
390 #define ROP_FN(d, s) (s) | (~(d))
391 #include "cirrus_vga_rop.h"
392
393 #define ROP_NAME notsrc
394 #define ROP_FN(d, s) (~(s))
395 #include "cirrus_vga_rop.h"
396
397 #define ROP_NAME notsrc_or_dst
398 #define ROP_FN(d, s) (~(s)) | (d)
399 #include "cirrus_vga_rop.h"
400
401 #define ROP_NAME notsrc_and_notdst
402 #define ROP_FN(d, s) (~(s)) & (~(d))
403 #include "cirrus_vga_rop.h"
404
405 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
406 cirrus_bitblt_rop_fwd_0,
407 cirrus_bitblt_rop_fwd_src_and_dst,
408 cirrus_bitblt_rop_nop,
409 cirrus_bitblt_rop_fwd_src_and_notdst,
410 cirrus_bitblt_rop_fwd_notdst,
411 cirrus_bitblt_rop_fwd_src,
412 cirrus_bitblt_rop_fwd_1,
413 cirrus_bitblt_rop_fwd_notsrc_and_dst,
414 cirrus_bitblt_rop_fwd_src_xor_dst,
415 cirrus_bitblt_rop_fwd_src_or_dst,
416 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
417 cirrus_bitblt_rop_fwd_src_notxor_dst,
418 cirrus_bitblt_rop_fwd_src_or_notdst,
419 cirrus_bitblt_rop_fwd_notsrc,
420 cirrus_bitblt_rop_fwd_notsrc_or_dst,
421 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
422 };
423
424 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
425 cirrus_bitblt_rop_bkwd_0,
426 cirrus_bitblt_rop_bkwd_src_and_dst,
427 cirrus_bitblt_rop_nop,
428 cirrus_bitblt_rop_bkwd_src_and_notdst,
429 cirrus_bitblt_rop_bkwd_notdst,
430 cirrus_bitblt_rop_bkwd_src,
431 cirrus_bitblt_rop_bkwd_1,
432 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
433 cirrus_bitblt_rop_bkwd_src_xor_dst,
434 cirrus_bitblt_rop_bkwd_src_or_dst,
435 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
436 cirrus_bitblt_rop_bkwd_src_notxor_dst,
437 cirrus_bitblt_rop_bkwd_src_or_notdst,
438 cirrus_bitblt_rop_bkwd_notsrc,
439 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
440 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
441 };
442
443 #define TRANSP_ROP(name) {\
444 name ## _8,\
445 name ## _16,\
446 }
447 #define TRANSP_NOP(func) {\
448 func,\
449 func,\
450 }
451
452 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
453 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
454 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
455 TRANSP_NOP(cirrus_bitblt_rop_nop),
456 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
457 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
458 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
459 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
460 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
461 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
462 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
463 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
464 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
465 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
466 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
467 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
468 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
469 };
470
471 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
472 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
473 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
474 TRANSP_NOP(cirrus_bitblt_rop_nop),
475 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
476 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
477 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
478 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
479 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
480 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
481 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
482 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
483 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
484 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
485 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
486 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
487 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
488 };
489
490 #define ROP2(name) {\
491 name ## _8,\
492 name ## _16,\
493 name ## _24,\
494 name ## _32,\
495 }
496
497 #define ROP_NOP2(func) {\
498 func,\
499 func,\
500 func,\
501 func,\
502 }
503
504 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
505 ROP2(cirrus_patternfill_0),
506 ROP2(cirrus_patternfill_src_and_dst),
507 ROP_NOP2(cirrus_bitblt_rop_nop),
508 ROP2(cirrus_patternfill_src_and_notdst),
509 ROP2(cirrus_patternfill_notdst),
510 ROP2(cirrus_patternfill_src),
511 ROP2(cirrus_patternfill_1),
512 ROP2(cirrus_patternfill_notsrc_and_dst),
513 ROP2(cirrus_patternfill_src_xor_dst),
514 ROP2(cirrus_patternfill_src_or_dst),
515 ROP2(cirrus_patternfill_notsrc_or_notdst),
516 ROP2(cirrus_patternfill_src_notxor_dst),
517 ROP2(cirrus_patternfill_src_or_notdst),
518 ROP2(cirrus_patternfill_notsrc),
519 ROP2(cirrus_patternfill_notsrc_or_dst),
520 ROP2(cirrus_patternfill_notsrc_and_notdst),
521 };
522
523 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
524 ROP2(cirrus_colorexpand_transp_0),
525 ROP2(cirrus_colorexpand_transp_src_and_dst),
526 ROP_NOP2(cirrus_bitblt_rop_nop),
527 ROP2(cirrus_colorexpand_transp_src_and_notdst),
528 ROP2(cirrus_colorexpand_transp_notdst),
529 ROP2(cirrus_colorexpand_transp_src),
530 ROP2(cirrus_colorexpand_transp_1),
531 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
532 ROP2(cirrus_colorexpand_transp_src_xor_dst),
533 ROP2(cirrus_colorexpand_transp_src_or_dst),
534 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
535 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
536 ROP2(cirrus_colorexpand_transp_src_or_notdst),
537 ROP2(cirrus_colorexpand_transp_notsrc),
538 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
539 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
540 };
541
542 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
543 ROP2(cirrus_colorexpand_0),
544 ROP2(cirrus_colorexpand_src_and_dst),
545 ROP_NOP2(cirrus_bitblt_rop_nop),
546 ROP2(cirrus_colorexpand_src_and_notdst),
547 ROP2(cirrus_colorexpand_notdst),
548 ROP2(cirrus_colorexpand_src),
549 ROP2(cirrus_colorexpand_1),
550 ROP2(cirrus_colorexpand_notsrc_and_dst),
551 ROP2(cirrus_colorexpand_src_xor_dst),
552 ROP2(cirrus_colorexpand_src_or_dst),
553 ROP2(cirrus_colorexpand_notsrc_or_notdst),
554 ROP2(cirrus_colorexpand_src_notxor_dst),
555 ROP2(cirrus_colorexpand_src_or_notdst),
556 ROP2(cirrus_colorexpand_notsrc),
557 ROP2(cirrus_colorexpand_notsrc_or_dst),
558 ROP2(cirrus_colorexpand_notsrc_and_notdst),
559 };
560
561 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
562 ROP2(cirrus_colorexpand_pattern_transp_0),
563 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
564 ROP_NOP2(cirrus_bitblt_rop_nop),
565 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
566 ROP2(cirrus_colorexpand_pattern_transp_notdst),
567 ROP2(cirrus_colorexpand_pattern_transp_src),
568 ROP2(cirrus_colorexpand_pattern_transp_1),
569 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
570 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
571 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
572 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
573 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
574 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
575 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
576 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
577 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
578 };
579
580 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
581 ROP2(cirrus_colorexpand_pattern_0),
582 ROP2(cirrus_colorexpand_pattern_src_and_dst),
583 ROP_NOP2(cirrus_bitblt_rop_nop),
584 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
585 ROP2(cirrus_colorexpand_pattern_notdst),
586 ROP2(cirrus_colorexpand_pattern_src),
587 ROP2(cirrus_colorexpand_pattern_1),
588 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
589 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
590 ROP2(cirrus_colorexpand_pattern_src_or_dst),
591 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
592 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
593 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
594 ROP2(cirrus_colorexpand_pattern_notsrc),
595 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
596 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
597 };
598
599 static const cirrus_fill_t cirrus_fill[16][4] = {
600 ROP2(cirrus_fill_0),
601 ROP2(cirrus_fill_src_and_dst),
602 ROP_NOP2(cirrus_bitblt_fill_nop),
603 ROP2(cirrus_fill_src_and_notdst),
604 ROP2(cirrus_fill_notdst),
605 ROP2(cirrus_fill_src),
606 ROP2(cirrus_fill_1),
607 ROP2(cirrus_fill_notsrc_and_dst),
608 ROP2(cirrus_fill_src_xor_dst),
609 ROP2(cirrus_fill_src_or_dst),
610 ROP2(cirrus_fill_notsrc_or_notdst),
611 ROP2(cirrus_fill_src_notxor_dst),
612 ROP2(cirrus_fill_src_or_notdst),
613 ROP2(cirrus_fill_notsrc),
614 ROP2(cirrus_fill_notsrc_or_dst),
615 ROP2(cirrus_fill_notsrc_and_notdst),
616 };
617
618 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
619 {
620 unsigned int color;
621 switch (s->cirrus_blt_pixelwidth) {
622 case 1:
623 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
624 break;
625 case 2:
626 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8);
627 s->cirrus_blt_fgcol = le16_to_cpu(color);
628 break;
629 case 3:
630 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
631 (s->vga.gr[0x11] << 8) | (s->vga.gr[0x13] << 16);
632 break;
633 default:
634 case 4:
635 color = s->cirrus_shadow_gr1 | (s->vga.gr[0x11] << 8) |
636 (s->vga.gr[0x13] << 16) | (s->vga.gr[0x15] << 24);
637 s->cirrus_blt_fgcol = le32_to_cpu(color);
638 break;
639 }
640 }
641
642 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
643 {
644 unsigned int color;
645 switch (s->cirrus_blt_pixelwidth) {
646 case 1:
647 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
648 break;
649 case 2:
650 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8);
651 s->cirrus_blt_bgcol = le16_to_cpu(color);
652 break;
653 case 3:
654 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
655 (s->vga.gr[0x10] << 8) | (s->vga.gr[0x12] << 16);
656 break;
657 default:
658 case 4:
659 color = s->cirrus_shadow_gr0 | (s->vga.gr[0x10] << 8) |
660 (s->vga.gr[0x12] << 16) | (s->vga.gr[0x14] << 24);
661 s->cirrus_blt_bgcol = le32_to_cpu(color);
662 break;
663 }
664 }
665
666 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
667 int off_pitch, int bytesperline,
668 int lines)
669 {
670 int y;
671 int off_cur;
672 int off_cur_end;
673
674 if (off_pitch < 0) {
675 off_begin -= bytesperline - 1;
676 }
677
678 for (y = 0; y < lines; y++) {
679 off_cur = off_begin;
680 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
681 assert(off_cur_end >= off_cur);
682 memory_region_set_dirty(&s->vga.vram, off_cur, off_cur_end - off_cur);
683 off_begin += off_pitch;
684 }
685 }
686
687 static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
688 const uint8_t * src)
689 {
690 uint8_t *dst;
691
692 dst = s->vga.vram_ptr + s->cirrus_blt_dstaddr;
693
694 if (blit_is_unsafe(s, false, true)) {
695 return 0;
696 }
697
698 (*s->cirrus_rop) (s, dst, src,
699 s->cirrus_blt_dstpitch, 0,
700 s->cirrus_blt_width, s->cirrus_blt_height);
701 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
702 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
703 s->cirrus_blt_height);
704 return 1;
705 }
706
707 /* fill */
708
709 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
710 {
711 cirrus_fill_t rop_func;
712
713 if (blit_is_unsafe(s, true, true)) {
714 return 0;
715 }
716 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
717 rop_func(s, s->vga.vram_ptr + s->cirrus_blt_dstaddr,
718 s->cirrus_blt_dstpitch,
719 s->cirrus_blt_width, s->cirrus_blt_height);
720 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
721 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
722 s->cirrus_blt_height);
723 cirrus_bitblt_reset(s);
724 return 1;
725 }
726
727 /***************************************
728 *
729 * bitblt (video-to-video)
730 *
731 ***************************************/
732
733 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
734 {
735 return cirrus_bitblt_common_patterncopy(s, s->vga.vram_ptr +
736 (s->cirrus_blt_srcaddr & ~7));
737 }
738
739 static int cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
740 {
741 int sx = 0, sy = 0;
742 int dx = 0, dy = 0;
743 int depth = 0;
744 int notify = 0;
745
746 /* make sure to only copy if it's a plain copy ROP */
747 if (*s->cirrus_rop == cirrus_bitblt_rop_fwd_src ||
748 *s->cirrus_rop == cirrus_bitblt_rop_bkwd_src) {
749
750 int width, height;
751
752 depth = s->vga.get_bpp(&s->vga) / 8;
753 if (!depth) {
754 return 0;
755 }
756 s->vga.get_resolution(&s->vga, &width, &height);
757
758 /* extra x, y */
759 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
760 sy = (src / ABS(s->cirrus_blt_srcpitch));
761 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
762 dy = (dst / ABS(s->cirrus_blt_dstpitch));
763
764 /* normalize width */
765 w /= depth;
766
767 /* if we're doing a backward copy, we have to adjust
768 our x/y to be the upper left corner (instead of the lower
769 right corner) */
770 if (s->cirrus_blt_dstpitch < 0) {
771 sx -= (s->cirrus_blt_width / depth) - 1;
772 dx -= (s->cirrus_blt_width / depth) - 1;
773 sy -= s->cirrus_blt_height - 1;
774 dy -= s->cirrus_blt_height - 1;
775 }
776
777 /* are we in the visible portion of memory? */
778 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
779 (sx + w) <= width && (sy + h) <= height &&
780 (dx + w) <= width && (dy + h) <= height) {
781 notify = 1;
782 }
783 }
784
785 /* we have to flush all pending changes so that the copy
786 is generated at the appropriate moment in time */
787 if (notify)
788 graphic_hw_update(s->vga.con);
789
790 (*s->cirrus_rop) (s, s->vga.vram_ptr + s->cirrus_blt_dstaddr,
791 s->vga.vram_ptr + s->cirrus_blt_srcaddr,
792 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
793 s->cirrus_blt_width, s->cirrus_blt_height);
794
795 if (notify) {
796 qemu_console_copy(s->vga.con,
797 sx, sy, dx, dy,
798 s->cirrus_blt_width / depth,
799 s->cirrus_blt_height);
800 }
801
802 /* we don't have to notify the display that this portion has
803 changed since qemu_console_copy implies this */
804
805 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
806 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
807 s->cirrus_blt_height);
808
809 return 1;
810 }
811
812 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
813 {
814 if (blit_is_unsafe(s, false, false))
815 return 0;
816
817 return cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->vga.start_addr,
818 s->cirrus_blt_srcaddr - s->vga.start_addr,
819 s->cirrus_blt_width, s->cirrus_blt_height);
820 }
821
822 /***************************************
823 *
824 * bitblt (cpu-to-video)
825 *
826 ***************************************/
827
828 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
829 {
830 int copy_count;
831 uint8_t *end_ptr;
832
833 if (s->cirrus_srccounter > 0) {
834 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
835 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
836 the_end:
837 s->cirrus_srccounter = 0;
838 cirrus_bitblt_reset(s);
839 } else {
840 /* at least one scan line */
841 do {
842 (*s->cirrus_rop)(s, s->vga.vram_ptr + s->cirrus_blt_dstaddr,
843 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
844 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
845 s->cirrus_blt_width, 1);
846 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
847 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
848 if (s->cirrus_srccounter <= 0)
849 goto the_end;
850 /* more bytes than needed can be transferred because of
851 word alignment, so we keep them for the next line */
852 /* XXX: keep alignment to speed up transfer */
853 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
854 copy_count = s->cirrus_srcptr_end - end_ptr;
855 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
856 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
857 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
858 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
859 }
860 }
861 }
862
863 /***************************************
864 *
865 * bitblt wrapper
866 *
867 ***************************************/
868
869 static void cirrus_bitblt_reset(CirrusVGAState * s)
870 {
871 int need_update;
872
873 s->vga.gr[0x31] &=
874 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
875 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
876 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
877 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
878 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
879 s->cirrus_srccounter = 0;
880 if (!need_update)
881 return;
882 cirrus_update_memory_access(s);
883 }
884
885 static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
886 {
887 int w;
888
889 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
890 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
891 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
892
893 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
894 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
895 s->cirrus_blt_srcpitch = 8;
896 } else {
897 /* XXX: check for 24 bpp */
898 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
899 }
900 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
901 } else {
902 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
903 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
904 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
905 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
906 else
907 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
908 } else {
909 /* always align input size to 32 bits */
910 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
911 }
912 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
913 }
914 s->cirrus_srcptr = s->cirrus_bltbuf;
915 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
916 cirrus_update_memory_access(s);
917 return 1;
918 }
919
920 static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
921 {
922 /* XXX */
923 #ifdef DEBUG_BITBLT
924 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
925 #endif
926 return 0;
927 }
928
929 static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
930 {
931 int ret;
932
933 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
934 ret = cirrus_bitblt_videotovideo_patterncopy(s);
935 } else {
936 ret = cirrus_bitblt_videotovideo_copy(s);
937 }
938 if (ret)
939 cirrus_bitblt_reset(s);
940 return ret;
941 }
942
943 static void cirrus_bitblt_start(CirrusVGAState * s)
944 {
945 uint8_t blt_rop;
946
947 s->vga.gr[0x31] |= CIRRUS_BLT_BUSY;
948
949 s->cirrus_blt_width = (s->vga.gr[0x20] | (s->vga.gr[0x21] << 8)) + 1;
950 s->cirrus_blt_height = (s->vga.gr[0x22] | (s->vga.gr[0x23] << 8)) + 1;
951 s->cirrus_blt_dstpitch = (s->vga.gr[0x24] | (s->vga.gr[0x25] << 8));
952 s->cirrus_blt_srcpitch = (s->vga.gr[0x26] | (s->vga.gr[0x27] << 8));
953 s->cirrus_blt_dstaddr =
954 (s->vga.gr[0x28] | (s->vga.gr[0x29] << 8) | (s->vga.gr[0x2a] << 16));
955 s->cirrus_blt_srcaddr =
956 (s->vga.gr[0x2c] | (s->vga.gr[0x2d] << 8) | (s->vga.gr[0x2e] << 16));
957 s->cirrus_blt_mode = s->vga.gr[0x30];
958 s->cirrus_blt_modeext = s->vga.gr[0x33];
959 blt_rop = s->vga.gr[0x32];
960
961 s->cirrus_blt_dstaddr &= s->cirrus_addr_mask;
962 s->cirrus_blt_srcaddr &= s->cirrus_addr_mask;
963
964 #ifdef DEBUG_BITBLT
965 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
966 blt_rop,
967 s->cirrus_blt_mode,
968 s->cirrus_blt_modeext,
969 s->cirrus_blt_width,
970 s->cirrus_blt_height,
971 s->cirrus_blt_dstpitch,
972 s->cirrus_blt_srcpitch,
973 s->cirrus_blt_dstaddr,
974 s->cirrus_blt_srcaddr,
975 s->vga.gr[0x2f]);
976 #endif
977
978 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
979 case CIRRUS_BLTMODE_PIXELWIDTH8:
980 s->cirrus_blt_pixelwidth = 1;
981 break;
982 case CIRRUS_BLTMODE_PIXELWIDTH16:
983 s->cirrus_blt_pixelwidth = 2;
984 break;
985 case CIRRUS_BLTMODE_PIXELWIDTH24:
986 s->cirrus_blt_pixelwidth = 3;
987 break;
988 case CIRRUS_BLTMODE_PIXELWIDTH32:
989 s->cirrus_blt_pixelwidth = 4;
990 break;
991 default:
992 #ifdef DEBUG_BITBLT
993 printf("cirrus: bitblt - pixel width is unknown\n");
994 #endif
995 goto bitblt_ignore;
996 }
997 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
998
999 if ((s->
1000 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
1001 CIRRUS_BLTMODE_MEMSYSDEST))
1002 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
1003 #ifdef DEBUG_BITBLT
1004 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
1005 #endif
1006 goto bitblt_ignore;
1007 }
1008
1009 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
1010 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
1011 CIRRUS_BLTMODE_TRANSPARENTCOMP |
1012 CIRRUS_BLTMODE_PATTERNCOPY |
1013 CIRRUS_BLTMODE_COLOREXPAND)) ==
1014 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
1015 cirrus_bitblt_fgcol(s);
1016 cirrus_bitblt_solidfill(s, blt_rop);
1017 } else {
1018 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
1019 CIRRUS_BLTMODE_PATTERNCOPY)) ==
1020 CIRRUS_BLTMODE_COLOREXPAND) {
1021
1022 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1023 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1024 cirrus_bitblt_bgcol(s);
1025 else
1026 cirrus_bitblt_fgcol(s);
1027 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1028 } else {
1029 cirrus_bitblt_fgcol(s);
1030 cirrus_bitblt_bgcol(s);
1031 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1032 }
1033 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
1034 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
1035 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1036 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1037 cirrus_bitblt_bgcol(s);
1038 else
1039 cirrus_bitblt_fgcol(s);
1040 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1041 } else {
1042 cirrus_bitblt_fgcol(s);
1043 cirrus_bitblt_bgcol(s);
1044 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1045 }
1046 } else {
1047 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1048 }
1049 } else {
1050 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1051 if (s->cirrus_blt_pixelwidth > 2) {
1052 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1053 goto bitblt_ignore;
1054 }
1055 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1056 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1057 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1058 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1059 } else {
1060 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1061 }
1062 } else {
1063 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1064 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1065 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1066 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1067 } else {
1068 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1069 }
1070 }
1071 }
1072 // setup bitblt engine.
1073 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1074 if (!cirrus_bitblt_cputovideo(s))
1075 goto bitblt_ignore;
1076 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1077 if (!cirrus_bitblt_videotocpu(s))
1078 goto bitblt_ignore;
1079 } else {
1080 if (!cirrus_bitblt_videotovideo(s))
1081 goto bitblt_ignore;
1082 }
1083 }
1084 return;
1085 bitblt_ignore:;
1086 cirrus_bitblt_reset(s);
1087 }
1088
1089 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1090 {
1091 unsigned old_value;
1092
1093 old_value = s->vga.gr[0x31];
1094 s->vga.gr[0x31] = reg_value;
1095
1096 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1097 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1098 cirrus_bitblt_reset(s);
1099 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1100 ((reg_value & CIRRUS_BLT_START) != 0)) {
1101 cirrus_bitblt_start(s);
1102 }
1103 }
1104
1105
1106 /***************************************
1107 *
1108 * basic parameters
1109 *
1110 ***************************************/
1111
1112 static void cirrus_get_offsets(VGACommonState *s1,
1113 uint32_t *pline_offset,
1114 uint32_t *pstart_addr,
1115 uint32_t *pline_compare)
1116 {
1117 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1118 uint32_t start_addr, line_offset, line_compare;
1119
1120 line_offset = s->vga.cr[0x13]
1121 | ((s->vga.cr[0x1b] & 0x10) << 4);
1122 line_offset <<= 3;
1123 *pline_offset = line_offset;
1124
1125 start_addr = (s->vga.cr[0x0c] << 8)
1126 | s->vga.cr[0x0d]
1127 | ((s->vga.cr[0x1b] & 0x01) << 16)
1128 | ((s->vga.cr[0x1b] & 0x0c) << 15)
1129 | ((s->vga.cr[0x1d] & 0x80) << 12);
1130 *pstart_addr = start_addr;
1131
1132 line_compare = s->vga.cr[0x18] |
1133 ((s->vga.cr[0x07] & 0x10) << 4) |
1134 ((s->vga.cr[0x09] & 0x40) << 3);
1135 *pline_compare = line_compare;
1136 }
1137
1138 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1139 {
1140 uint32_t ret = 16;
1141
1142 switch (s->cirrus_hidden_dac_data & 0xf) {
1143 case 0:
1144 ret = 15;
1145 break; /* Sierra HiColor */
1146 case 1:
1147 ret = 16;
1148 break; /* XGA HiColor */
1149 default:
1150 #ifdef DEBUG_CIRRUS
1151 printf("cirrus: invalid DAC value %x in 16bpp\n",
1152 (s->cirrus_hidden_dac_data & 0xf));
1153 #endif
1154 ret = 15; /* XXX */
1155 break;
1156 }
1157 return ret;
1158 }
1159
1160 static int cirrus_get_bpp(VGACommonState *s1)
1161 {
1162 CirrusVGAState * s = container_of(s1, CirrusVGAState, vga);
1163 uint32_t ret = 8;
1164
1165 if ((s->vga.sr[0x07] & 0x01) != 0) {
1166 /* Cirrus SVGA */
1167 switch (s->vga.sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1168 case CIRRUS_SR7_BPP_8:
1169 ret = 8;
1170 break;
1171 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1172 ret = cirrus_get_bpp16_depth(s);
1173 break;
1174 case CIRRUS_SR7_BPP_24:
1175 ret = 24;
1176 break;
1177 case CIRRUS_SR7_BPP_16:
1178 ret = cirrus_get_bpp16_depth(s);
1179 break;
1180 case CIRRUS_SR7_BPP_32:
1181 ret = 32;
1182 break;
1183 default:
1184 #ifdef DEBUG_CIRRUS
1185 printf("cirrus: unknown bpp - sr7=%x\n", s->vga.sr[0x7]);
1186 #endif
1187 ret = 8;
1188 break;
1189 }
1190 } else {
1191 /* VGA */
1192 ret = 0;
1193 }
1194
1195 return ret;
1196 }
1197
1198 static void cirrus_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
1199 {
1200 int width, height;
1201
1202 width = (s->cr[0x01] + 1) * 8;
1203 height = s->cr[0x12] |
1204 ((s->cr[0x07] & 0x02) << 7) |
1205 ((s->cr[0x07] & 0x40) << 3);
1206 height = (height + 1);
1207 /* interlace support */
1208 if (s->cr[0x1a] & 0x01)
1209 height = height * 2;
1210 *pwidth = width;
1211 *pheight = height;
1212 }
1213
1214 /***************************************
1215 *
1216 * bank memory
1217 *
1218 ***************************************/
1219
1220 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1221 {
1222 unsigned offset;
1223 unsigned limit;
1224
1225 if ((s->vga.gr[0x0b] & 0x01) != 0) /* dual bank */
1226 offset = s->vga.gr[0x09 + bank_index];
1227 else /* single bank */
1228 offset = s->vga.gr[0x09];
1229
1230 if ((s->vga.gr[0x0b] & 0x20) != 0)
1231 offset <<= 14;
1232 else
1233 offset <<= 12;
1234
1235 if (s->real_vram_size <= offset)
1236 limit = 0;
1237 else
1238 limit = s->real_vram_size - offset;
1239
1240 if (((s->vga.gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1241 if (limit > 0x8000) {
1242 offset += 0x8000;
1243 limit -= 0x8000;
1244 } else {
1245 limit = 0;
1246 }
1247 }
1248
1249 if (limit > 0) {
1250 s->cirrus_bank_base[bank_index] = offset;
1251 s->cirrus_bank_limit[bank_index] = limit;
1252 } else {
1253 s->cirrus_bank_base[bank_index] = 0;
1254 s->cirrus_bank_limit[bank_index] = 0;
1255 }
1256 }
1257
1258 /***************************************
1259 *
1260 * I/O access between 0x3c4-0x3c5
1261 *
1262 ***************************************/
1263
1264 static int cirrus_vga_read_sr(CirrusVGAState * s)
1265 {
1266 switch (s->vga.sr_index) {
1267 case 0x00: // Standard VGA
1268 case 0x01: // Standard VGA
1269 case 0x02: // Standard VGA
1270 case 0x03: // Standard VGA
1271 case 0x04: // Standard VGA
1272 return s->vga.sr[s->vga.sr_index];
1273 case 0x06: // Unlock Cirrus extensions
1274 return s->vga.sr[s->vga.sr_index];
1275 case 0x10:
1276 case 0x30:
1277 case 0x50:
1278 case 0x70: // Graphics Cursor X
1279 case 0x90:
1280 case 0xb0:
1281 case 0xd0:
1282 case 0xf0: // Graphics Cursor X
1283 return s->vga.sr[0x10];
1284 case 0x11:
1285 case 0x31:
1286 case 0x51:
1287 case 0x71: // Graphics Cursor Y
1288 case 0x91:
1289 case 0xb1:
1290 case 0xd1:
1291 case 0xf1: // Graphics Cursor Y
1292 return s->vga.sr[0x11];
1293 case 0x05: // ???
1294 case 0x07: // Extended Sequencer Mode
1295 case 0x08: // EEPROM Control
1296 case 0x09: // Scratch Register 0
1297 case 0x0a: // Scratch Register 1
1298 case 0x0b: // VCLK 0
1299 case 0x0c: // VCLK 1
1300 case 0x0d: // VCLK 2
1301 case 0x0e: // VCLK 3
1302 case 0x0f: // DRAM Control
1303 case 0x12: // Graphics Cursor Attribute
1304 case 0x13: // Graphics Cursor Pattern Address
1305 case 0x14: // Scratch Register 2
1306 case 0x15: // Scratch Register 3
1307 case 0x16: // Performance Tuning Register
1308 case 0x17: // Configuration Readback and Extended Control
1309 case 0x18: // Signature Generator Control
1310 case 0x19: // Signal Generator Result
1311 case 0x1a: // Signal Generator Result
1312 case 0x1b: // VCLK 0 Denominator & Post
1313 case 0x1c: // VCLK 1 Denominator & Post
1314 case 0x1d: // VCLK 2 Denominator & Post
1315 case 0x1e: // VCLK 3 Denominator & Post
1316 case 0x1f: // BIOS Write Enable and MCLK select
1317 #ifdef DEBUG_CIRRUS
1318 printf("cirrus: handled inport sr_index %02x\n", s->vga.sr_index);
1319 #endif
1320 return s->vga.sr[s->vga.sr_index];
1321 default:
1322 #ifdef DEBUG_CIRRUS
1323 printf("cirrus: inport sr_index %02x\n", s->vga.sr_index);
1324 #endif
1325 return 0xff;
1326 break;
1327 }
1328 }
1329
1330 static void cirrus_vga_write_sr(CirrusVGAState * s, uint32_t val)
1331 {
1332 switch (s->vga.sr_index) {
1333 case 0x00: // Standard VGA
1334 case 0x01: // Standard VGA
1335 case 0x02: // Standard VGA
1336 case 0x03: // Standard VGA
1337 case 0x04: // Standard VGA
1338 s->vga.sr[s->vga.sr_index] = val & sr_mask[s->vga.sr_index];
1339 if (s->vga.sr_index == 1)
1340 s->vga.update_retrace_info(&s->vga);
1341 break;
1342 case 0x06: // Unlock Cirrus extensions
1343 val &= 0x17;
1344 if (val == 0x12) {
1345 s->vga.sr[s->vga.sr_index] = 0x12;
1346 } else {
1347 s->vga.sr[s->vga.sr_index] = 0x0f;
1348 }
1349 break;
1350 case 0x10:
1351 case 0x30:
1352 case 0x50:
1353 case 0x70: // Graphics Cursor X
1354 case 0x90:
1355 case 0xb0:
1356 case 0xd0:
1357 case 0xf0: // Graphics Cursor X
1358 s->vga.sr[0x10] = val;
1359 s->vga.hw_cursor_x = (val << 3) | (s->vga.sr_index >> 5);
1360 break;
1361 case 0x11:
1362 case 0x31:
1363 case 0x51:
1364 case 0x71: // Graphics Cursor Y
1365 case 0x91:
1366 case 0xb1:
1367 case 0xd1:
1368 case 0xf1: // Graphics Cursor Y
1369 s->vga.sr[0x11] = val;
1370 s->vga.hw_cursor_y = (val << 3) | (s->vga.sr_index >> 5);
1371 break;
1372 case 0x07: // Extended Sequencer Mode
1373 cirrus_update_memory_access(s);
1374 case 0x08: // EEPROM Control
1375 case 0x09: // Scratch Register 0
1376 case 0x0a: // Scratch Register 1
1377 case 0x0b: // VCLK 0
1378 case 0x0c: // VCLK 1
1379 case 0x0d: // VCLK 2
1380 case 0x0e: // VCLK 3
1381 case 0x0f: // DRAM Control
1382 case 0x13: // Graphics Cursor Pattern Address
1383 case 0x14: // Scratch Register 2
1384 case 0x15: // Scratch Register 3
1385 case 0x16: // Performance Tuning Register
1386 case 0x18: // Signature Generator Control
1387 case 0x19: // Signature Generator Result
1388 case 0x1a: // Signature Generator Result
1389 case 0x1b: // VCLK 0 Denominator & Post
1390 case 0x1c: // VCLK 1 Denominator & Post
1391 case 0x1d: // VCLK 2 Denominator & Post
1392 case 0x1e: // VCLK 3 Denominator & Post
1393 case 0x1f: // BIOS Write Enable and MCLK select
1394 s->vga.sr[s->vga.sr_index] = val;
1395 #ifdef DEBUG_CIRRUS
1396 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1397 s->vga.sr_index, val);
1398 #endif
1399 break;
1400 case 0x12: // Graphics Cursor Attribute
1401 s->vga.sr[0x12] = val;
1402 s->vga.force_shadow = !!(val & CIRRUS_CURSOR_SHOW);
1403 #ifdef DEBUG_CIRRUS
1404 printf("cirrus: cursor ctl SR12=%02x (force shadow: %d)\n",
1405 val, s->vga.force_shadow);
1406 #endif
1407 break;
1408 case 0x17: // Configuration Readback and Extended Control
1409 s->vga.sr[s->vga.sr_index] = (s->vga.sr[s->vga.sr_index] & 0x38)
1410 | (val & 0xc7);
1411 cirrus_update_memory_access(s);
1412 break;
1413 default:
1414 #ifdef DEBUG_CIRRUS
1415 printf("cirrus: outport sr_index %02x, sr_value %02x\n",
1416 s->vga.sr_index, val);
1417 #endif
1418 break;
1419 }
1420 }
1421
1422 /***************************************
1423 *
1424 * I/O access at 0x3c6
1425 *
1426 ***************************************/
1427
1428 static int cirrus_read_hidden_dac(CirrusVGAState * s)
1429 {
1430 if (++s->cirrus_hidden_dac_lockindex == 5) {
1431 s->cirrus_hidden_dac_lockindex = 0;
1432 return s->cirrus_hidden_dac_data;
1433 }
1434 return 0xff;
1435 }
1436
1437 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1438 {
1439 if (s->cirrus_hidden_dac_lockindex == 4) {
1440 s->cirrus_hidden_dac_data = reg_value;
1441 #if defined(DEBUG_CIRRUS)
1442 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1443 #endif
1444 }
1445 s->cirrus_hidden_dac_lockindex = 0;
1446 }
1447
1448 /***************************************
1449 *
1450 * I/O access at 0x3c9
1451 *
1452 ***************************************/
1453
1454 static int cirrus_vga_read_palette(CirrusVGAState * s)
1455 {
1456 int val;
1457
1458 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1459 val = s->cirrus_hidden_palette[(s->vga.dac_read_index & 0x0f) * 3 +
1460 s->vga.dac_sub_index];
1461 } else {
1462 val = s->vga.palette[s->vga.dac_read_index * 3 + s->vga.dac_sub_index];
1463 }
1464 if (++s->vga.dac_sub_index == 3) {
1465 s->vga.dac_sub_index = 0;
1466 s->vga.dac_read_index++;
1467 }
1468 return val;
1469 }
1470
1471 static void cirrus_vga_write_palette(CirrusVGAState * s, int reg_value)
1472 {
1473 s->vga.dac_cache[s->vga.dac_sub_index] = reg_value;
1474 if (++s->vga.dac_sub_index == 3) {
1475 if ((s->vga.sr[0x12] & CIRRUS_CURSOR_HIDDENPEL)) {
1476 memcpy(&s->cirrus_hidden_palette[(s->vga.dac_write_index & 0x0f) * 3],
1477 s->vga.dac_cache, 3);
1478 } else {
1479 memcpy(&s->vga.palette[s->vga.dac_write_index * 3], s->vga.dac_cache, 3);
1480 }
1481 /* XXX update cursor */
1482 s->vga.dac_sub_index = 0;
1483 s->vga.dac_write_index++;
1484 }
1485 }
1486
1487 /***************************************
1488 *
1489 * I/O access between 0x3ce-0x3cf
1490 *
1491 ***************************************/
1492
1493 static int cirrus_vga_read_gr(CirrusVGAState * s, unsigned reg_index)
1494 {
1495 switch (reg_index) {
1496 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1497 return s->cirrus_shadow_gr0;
1498 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1499 return s->cirrus_shadow_gr1;
1500 case 0x02: // Standard VGA
1501 case 0x03: // Standard VGA
1502 case 0x04: // Standard VGA
1503 case 0x06: // Standard VGA
1504 case 0x07: // Standard VGA
1505 case 0x08: // Standard VGA
1506 return s->vga.gr[s->vga.gr_index];
1507 case 0x05: // Standard VGA, Cirrus extended mode
1508 default:
1509 break;
1510 }
1511
1512 if (reg_index < 0x3a) {
1513 return s->vga.gr[reg_index];
1514 } else {
1515 #ifdef DEBUG_CIRRUS
1516 printf("cirrus: inport gr_index %02x\n", reg_index);
1517 #endif
1518 return 0xff;
1519 }
1520 }
1521
1522 static void
1523 cirrus_vga_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1524 {
1525 #if defined(DEBUG_BITBLT) && 0
1526 printf("gr%02x: %02x\n", reg_index, reg_value);
1527 #endif
1528 switch (reg_index) {
1529 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1530 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1531 s->cirrus_shadow_gr0 = reg_value;
1532 break;
1533 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1534 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1535 s->cirrus_shadow_gr1 = reg_value;
1536 break;
1537 case 0x02: // Standard VGA
1538 case 0x03: // Standard VGA
1539 case 0x04: // Standard VGA
1540 case 0x06: // Standard VGA
1541 case 0x07: // Standard VGA
1542 case 0x08: // Standard VGA
1543 s->vga.gr[reg_index] = reg_value & gr_mask[reg_index];
1544 break;
1545 case 0x05: // Standard VGA, Cirrus extended mode
1546 s->vga.gr[reg_index] = reg_value & 0x7f;
1547 cirrus_update_memory_access(s);
1548 break;
1549 case 0x09: // bank offset #0
1550 case 0x0A: // bank offset #1
1551 s->vga.gr[reg_index] = reg_value;
1552 cirrus_update_bank_ptr(s, 0);
1553 cirrus_update_bank_ptr(s, 1);
1554 cirrus_update_memory_access(s);
1555 break;
1556 case 0x0B:
1557 s->vga.gr[reg_index] = reg_value;
1558 cirrus_update_bank_ptr(s, 0);
1559 cirrus_update_bank_ptr(s, 1);
1560 cirrus_update_memory_access(s);
1561 break;
1562 case 0x10: // BGCOLOR 0x0000ff00
1563 case 0x11: // FGCOLOR 0x0000ff00
1564 case 0x12: // BGCOLOR 0x00ff0000
1565 case 0x13: // FGCOLOR 0x00ff0000
1566 case 0x14: // BGCOLOR 0xff000000
1567 case 0x15: // FGCOLOR 0xff000000
1568 case 0x20: // BLT WIDTH 0x0000ff
1569 case 0x22: // BLT HEIGHT 0x0000ff
1570 case 0x24: // BLT DEST PITCH 0x0000ff
1571 case 0x26: // BLT SRC PITCH 0x0000ff
1572 case 0x28: // BLT DEST ADDR 0x0000ff
1573 case 0x29: // BLT DEST ADDR 0x00ff00
1574 case 0x2c: // BLT SRC ADDR 0x0000ff
1575 case 0x2d: // BLT SRC ADDR 0x00ff00
1576 case 0x2f: // BLT WRITEMASK
1577 case 0x30: // BLT MODE
1578 case 0x32: // RASTER OP
1579 case 0x33: // BLT MODEEXT
1580 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1581 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1582 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1583 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1584 s->vga.gr[reg_index] = reg_value;
1585 break;
1586 case 0x21: // BLT WIDTH 0x001f00
1587 case 0x23: // BLT HEIGHT 0x001f00
1588 case 0x25: // BLT DEST PITCH 0x001f00
1589 case 0x27: // BLT SRC PITCH 0x001f00
1590 s->vga.gr[reg_index] = reg_value & 0x1f;
1591 break;
1592 case 0x2a: // BLT DEST ADDR 0x3f0000
1593 s->vga.gr[reg_index] = reg_value & 0x3f;
1594 /* if auto start mode, starts bit blt now */
1595 if (s->vga.gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1596 cirrus_bitblt_start(s);
1597 }
1598 break;
1599 case 0x2e: // BLT SRC ADDR 0x3f0000
1600 s->vga.gr[reg_index] = reg_value & 0x3f;
1601 break;
1602 case 0x31: // BLT STATUS/START
1603 cirrus_write_bitblt(s, reg_value);
1604 break;
1605 default:
1606 #ifdef DEBUG_CIRRUS
1607 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1608 reg_value);
1609 #endif
1610 break;
1611 }
1612 }
1613
1614 /***************************************
1615 *
1616 * I/O access between 0x3d4-0x3d5
1617 *
1618 ***************************************/
1619
1620 static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
1621 {
1622 switch (reg_index) {
1623 case 0x00: // Standard VGA
1624 case 0x01: // Standard VGA
1625 case 0x02: // Standard VGA
1626 case 0x03: // Standard VGA
1627 case 0x04: // Standard VGA
1628 case 0x05: // Standard VGA
1629 case 0x06: // Standard VGA
1630 case 0x07: // Standard VGA
1631 case 0x08: // Standard VGA
1632 case 0x09: // Standard VGA
1633 case 0x0a: // Standard VGA
1634 case 0x0b: // Standard VGA
1635 case 0x0c: // Standard VGA
1636 case 0x0d: // Standard VGA
1637 case 0x0e: // Standard VGA
1638 case 0x0f: // Standard VGA
1639 case 0x10: // Standard VGA
1640 case 0x11: // Standard VGA
1641 case 0x12: // Standard VGA
1642 case 0x13: // Standard VGA
1643 case 0x14: // Standard VGA
1644 case 0x15: // Standard VGA
1645 case 0x16: // Standard VGA
1646 case 0x17: // Standard VGA
1647 case 0x18: // Standard VGA
1648 return s->vga.cr[s->vga.cr_index];
1649 case 0x24: // Attribute Controller Toggle Readback (R)
1650 return (s->vga.ar_flip_flop << 7);
1651 case 0x19: // Interlace End
1652 case 0x1a: // Miscellaneous Control
1653 case 0x1b: // Extended Display Control
1654 case 0x1c: // Sync Adjust and Genlock
1655 case 0x1d: // Overlay Extended Control
1656 case 0x22: // Graphics Data Latches Readback (R)
1657 case 0x25: // Part Status
1658 case 0x27: // Part ID (R)
1659 return s->vga.cr[s->vga.cr_index];
1660 case 0x26: // Attribute Controller Index Readback (R)
1661 return s->vga.ar_index & 0x3f;
1662 break;
1663 default:
1664 #ifdef DEBUG_CIRRUS
1665 printf("cirrus: inport cr_index %02x\n", reg_index);
1666 #endif
1667 return 0xff;
1668 }
1669 }
1670
1671 static void cirrus_vga_write_cr(CirrusVGAState * s, int reg_value)
1672 {
1673 switch (s->vga.cr_index) {
1674 case 0x00: // Standard VGA
1675 case 0x01: // Standard VGA
1676 case 0x02: // Standard VGA
1677 case 0x03: // Standard VGA
1678 case 0x04: // Standard VGA
1679 case 0x05: // Standard VGA
1680 case 0x06: // Standard VGA
1681 case 0x07: // Standard VGA
1682 case 0x08: // Standard VGA
1683 case 0x09: // Standard VGA
1684 case 0x0a: // Standard VGA
1685 case 0x0b: // Standard VGA
1686 case 0x0c: // Standard VGA
1687 case 0x0d: // Standard VGA
1688 case 0x0e: // Standard VGA
1689 case 0x0f: // Standard VGA
1690 case 0x10: // Standard VGA
1691 case 0x11: // Standard VGA
1692 case 0x12: // Standard VGA
1693 case 0x13: // Standard VGA
1694 case 0x14: // Standard VGA
1695 case 0x15: // Standard VGA
1696 case 0x16: // Standard VGA
1697 case 0x17: // Standard VGA
1698 case 0x18: // Standard VGA
1699 /* handle CR0-7 protection */
1700 if ((s->vga.cr[0x11] & 0x80) && s->vga.cr_index <= 7) {
1701 /* can always write bit 4 of CR7 */
1702 if (s->vga.cr_index == 7)
1703 s->vga.cr[7] = (s->vga.cr[7] & ~0x10) | (reg_value & 0x10);
1704 return;
1705 }
1706 s->vga.cr[s->vga.cr_index] = reg_value;
1707 switch(s->vga.cr_index) {
1708 case 0x00:
1709 case 0x04:
1710 case 0x05:
1711 case 0x06:
1712 case 0x07:
1713 case 0x11:
1714 case 0x17:
1715 s->vga.update_retrace_info(&s->vga);
1716 break;
1717 }
1718 break;
1719 case 0x19: // Interlace End
1720 case 0x1a: // Miscellaneous Control
1721 case 0x1b: // Extended Display Control
1722 case 0x1c: // Sync Adjust and Genlock
1723 case 0x1d: // Overlay Extended Control
1724 s->vga.cr[s->vga.cr_index] = reg_value;
1725 #ifdef DEBUG_CIRRUS
1726 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1727 s->vga.cr_index, reg_value);
1728 #endif
1729 break;
1730 case 0x22: // Graphics Data Latches Readback (R)
1731 case 0x24: // Attribute Controller Toggle Readback (R)
1732 case 0x26: // Attribute Controller Index Readback (R)
1733 case 0x27: // Part ID (R)
1734 break;
1735 case 0x25: // Part Status
1736 default:
1737 #ifdef DEBUG_CIRRUS
1738 printf("cirrus: outport cr_index %02x, cr_value %02x\n",
1739 s->vga.cr_index, reg_value);
1740 #endif
1741 break;
1742 }
1743 }
1744
1745 /***************************************
1746 *
1747 * memory-mapped I/O (bitblt)
1748 *
1749 ***************************************/
1750
1751 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1752 {
1753 int value = 0xff;
1754
1755 switch (address) {
1756 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1757 value = cirrus_vga_read_gr(s, 0x00);
1758 break;
1759 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1760 value = cirrus_vga_read_gr(s, 0x10);
1761 break;
1762 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1763 value = cirrus_vga_read_gr(s, 0x12);
1764 break;
1765 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1766 value = cirrus_vga_read_gr(s, 0x14);
1767 break;
1768 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1769 value = cirrus_vga_read_gr(s, 0x01);
1770 break;
1771 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1772 value = cirrus_vga_read_gr(s, 0x11);
1773 break;
1774 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1775 value = cirrus_vga_read_gr(s, 0x13);
1776 break;
1777 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1778 value = cirrus_vga_read_gr(s, 0x15);
1779 break;
1780 case (CIRRUS_MMIO_BLTWIDTH + 0):
1781 value = cirrus_vga_read_gr(s, 0x20);
1782 break;
1783 case (CIRRUS_MMIO_BLTWIDTH + 1):
1784 value = cirrus_vga_read_gr(s, 0x21);
1785 break;
1786 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1787 value = cirrus_vga_read_gr(s, 0x22);
1788 break;
1789 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1790 value = cirrus_vga_read_gr(s, 0x23);
1791 break;
1792 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1793 value = cirrus_vga_read_gr(s, 0x24);
1794 break;
1795 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1796 value = cirrus_vga_read_gr(s, 0x25);
1797 break;
1798 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1799 value = cirrus_vga_read_gr(s, 0x26);
1800 break;
1801 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1802 value = cirrus_vga_read_gr(s, 0x27);
1803 break;
1804 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1805 value = cirrus_vga_read_gr(s, 0x28);
1806 break;
1807 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1808 value = cirrus_vga_read_gr(s, 0x29);
1809 break;
1810 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1811 value = cirrus_vga_read_gr(s, 0x2a);
1812 break;
1813 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1814 value = cirrus_vga_read_gr(s, 0x2c);
1815 break;
1816 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1817 value = cirrus_vga_read_gr(s, 0x2d);
1818 break;
1819 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1820 value = cirrus_vga_read_gr(s, 0x2e);
1821 break;
1822 case CIRRUS_MMIO_BLTWRITEMASK:
1823 value = cirrus_vga_read_gr(s, 0x2f);
1824 break;
1825 case CIRRUS_MMIO_BLTMODE:
1826 value = cirrus_vga_read_gr(s, 0x30);
1827 break;
1828 case CIRRUS_MMIO_BLTROP:
1829 value = cirrus_vga_read_gr(s, 0x32);
1830 break;
1831 case CIRRUS_MMIO_BLTMODEEXT:
1832 value = cirrus_vga_read_gr(s, 0x33);
1833 break;
1834 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1835 value = cirrus_vga_read_gr(s, 0x34);
1836 break;
1837 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1838 value = cirrus_vga_read_gr(s, 0x35);
1839 break;
1840 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1841 value = cirrus_vga_read_gr(s, 0x38);
1842 break;
1843 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1844 value = cirrus_vga_read_gr(s, 0x39);
1845 break;
1846 case CIRRUS_MMIO_BLTSTATUS:
1847 value = cirrus_vga_read_gr(s, 0x31);
1848 break;
1849 default:
1850 #ifdef DEBUG_CIRRUS
1851 printf("cirrus: mmio read - address 0x%04x\n", address);
1852 #endif
1853 break;
1854 }
1855
1856 trace_vga_cirrus_write_blt(address, value);
1857 return (uint8_t) value;
1858 }
1859
1860 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1861 uint8_t value)
1862 {
1863 trace_vga_cirrus_write_blt(address, value);
1864 switch (address) {
1865 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1866 cirrus_vga_write_gr(s, 0x00, value);
1867 break;
1868 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1869 cirrus_vga_write_gr(s, 0x10, value);
1870 break;
1871 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1872 cirrus_vga_write_gr(s, 0x12, value);
1873 break;
1874 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1875 cirrus_vga_write_gr(s, 0x14, value);
1876 break;
1877 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1878 cirrus_vga_write_gr(s, 0x01, value);
1879 break;
1880 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1881 cirrus_vga_write_gr(s, 0x11, value);
1882 break;
1883 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1884 cirrus_vga_write_gr(s, 0x13, value);
1885 break;
1886 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1887 cirrus_vga_write_gr(s, 0x15, value);
1888 break;
1889 case (CIRRUS_MMIO_BLTWIDTH + 0):
1890 cirrus_vga_write_gr(s, 0x20, value);
1891 break;
1892 case (CIRRUS_MMIO_BLTWIDTH + 1):
1893 cirrus_vga_write_gr(s, 0x21, value);
1894 break;
1895 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1896 cirrus_vga_write_gr(s, 0x22, value);
1897 break;
1898 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1899 cirrus_vga_write_gr(s, 0x23, value);
1900 break;
1901 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1902 cirrus_vga_write_gr(s, 0x24, value);
1903 break;
1904 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1905 cirrus_vga_write_gr(s, 0x25, value);
1906 break;
1907 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1908 cirrus_vga_write_gr(s, 0x26, value);
1909 break;
1910 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1911 cirrus_vga_write_gr(s, 0x27, value);
1912 break;
1913 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1914 cirrus_vga_write_gr(s, 0x28, value);
1915 break;
1916 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1917 cirrus_vga_write_gr(s, 0x29, value);
1918 break;
1919 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1920 cirrus_vga_write_gr(s, 0x2a, value);
1921 break;
1922 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1923 /* ignored */
1924 break;
1925 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1926 cirrus_vga_write_gr(s, 0x2c, value);
1927 break;
1928 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1929 cirrus_vga_write_gr(s, 0x2d, value);
1930 break;
1931 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1932 cirrus_vga_write_gr(s, 0x2e, value);
1933 break;
1934 case CIRRUS_MMIO_BLTWRITEMASK:
1935 cirrus_vga_write_gr(s, 0x2f, value);
1936 break;
1937 case CIRRUS_MMIO_BLTMODE:
1938 cirrus_vga_write_gr(s, 0x30, value);
1939 break;
1940 case CIRRUS_MMIO_BLTROP:
1941 cirrus_vga_write_gr(s, 0x32, value);
1942 break;
1943 case CIRRUS_MMIO_BLTMODEEXT:
1944 cirrus_vga_write_gr(s, 0x33, value);
1945 break;
1946 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1947 cirrus_vga_write_gr(s, 0x34, value);
1948 break;
1949 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1950 cirrus_vga_write_gr(s, 0x35, value);
1951 break;
1952 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1953 cirrus_vga_write_gr(s, 0x38, value);
1954 break;
1955 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1956 cirrus_vga_write_gr(s, 0x39, value);
1957 break;
1958 case CIRRUS_MMIO_BLTSTATUS:
1959 cirrus_vga_write_gr(s, 0x31, value);
1960 break;
1961 default:
1962 #ifdef DEBUG_CIRRUS
1963 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1964 address, value);
1965 #endif
1966 break;
1967 }
1968 }
1969
1970 /***************************************
1971 *
1972 * write mode 4/5
1973 *
1974 ***************************************/
1975
1976 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1977 unsigned mode,
1978 unsigned offset,
1979 uint32_t mem_value)
1980 {
1981 int x;
1982 unsigned val = mem_value;
1983 uint8_t *dst;
1984
1985 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
1986 for (x = 0; x < 8; x++) {
1987 if (val & 0x80) {
1988 *dst = s->cirrus_shadow_gr1;
1989 } else if (mode == 5) {
1990 *dst = s->cirrus_shadow_gr0;
1991 }
1992 val <<= 1;
1993 dst++;
1994 }
1995 memory_region_set_dirty(&s->vga.vram, offset, 8);
1996 }
1997
1998 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1999 unsigned mode,
2000 unsigned offset,
2001 uint32_t mem_value)
2002 {
2003 int x;
2004 unsigned val = mem_value;
2005 uint8_t *dst;
2006
2007 dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
2008 for (x = 0; x < 8; x++) {
2009 if (val & 0x80) {
2010 *dst = s->cirrus_shadow_gr1;
2011 *(dst + 1) = s->vga.gr[0x11];
2012 } else if (mode == 5) {
2013 *dst = s->cirrus_shadow_gr0;
2014 *(dst + 1) = s->vga.gr[0x10];
2015 }
2016 val <<= 1;
2017 dst += 2;
2018 }
2019 memory_region_set_dirty(&s->vga.vram, offset, 16);
2020 }
2021
2022 /***************************************
2023 *
2024 * memory access between 0xa0000-0xbffff
2025 *
2026 ***************************************/
2027
2028 static uint64_t cirrus_vga_mem_read(void *opaque,
2029 hwaddr addr,
2030 uint32_t size)
2031 {
2032 CirrusVGAState *s = opaque;
2033 unsigned bank_index;
2034 unsigned bank_offset;
2035 uint32_t val;
2036
2037 if ((s->vga.sr[0x07] & 0x01) == 0) {
2038 return vga_mem_readb(&s->vga, addr);
2039 }
2040
2041 if (addr < 0x10000) {
2042 /* XXX handle bitblt */
2043 /* video memory */
2044 bank_index = addr >> 15;
2045 bank_offset = addr & 0x7fff;
2046 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2047 bank_offset += s->cirrus_bank_base[bank_index];
2048 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2049 bank_offset <<= 4;
2050 } else if (s->vga.gr[0x0B] & 0x02) {
2051 bank_offset <<= 3;
2052 }
2053 bank_offset &= s->cirrus_addr_mask;
2054 val = *(s->vga.vram_ptr + bank_offset);
2055 } else
2056 val = 0xff;
2057 } else if (addr >= 0x18000 && addr < 0x18100) {
2058 /* memory-mapped I/O */
2059 val = 0xff;
2060 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
2061 val = cirrus_mmio_blt_read(s, addr & 0xff);
2062 }
2063 } else {
2064 val = 0xff;
2065 #ifdef DEBUG_CIRRUS
2066 printf("cirrus: mem_readb " TARGET_FMT_plx "\n", addr);
2067 #endif
2068 }
2069 return val;
2070 }
2071
2072 static void cirrus_vga_mem_write(void *opaque,
2073 hwaddr addr,
2074 uint64_t mem_value,
2075 uint32_t size)
2076 {
2077 CirrusVGAState *s = opaque;
2078 unsigned bank_index;
2079 unsigned bank_offset;
2080 unsigned mode;
2081
2082 if ((s->vga.sr[0x07] & 0x01) == 0) {
2083 vga_mem_writeb(&s->vga, addr, mem_value);
2084 return;
2085 }
2086
2087 if (addr < 0x10000) {
2088 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2089 /* bitblt */
2090 *s->cirrus_srcptr++ = (uint8_t) mem_value;
2091 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2092 cirrus_bitblt_cputovideo_next(s);
2093 }
2094 } else {
2095 /* video memory */
2096 bank_index = addr >> 15;
2097 bank_offset = addr & 0x7fff;
2098 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2099 bank_offset += s->cirrus_bank_base[bank_index];
2100 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2101 bank_offset <<= 4;
2102 } else if (s->vga.gr[0x0B] & 0x02) {
2103 bank_offset <<= 3;
2104 }
2105 bank_offset &= s->cirrus_addr_mask;
2106 mode = s->vga.gr[0x05] & 0x7;
2107 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2108 *(s->vga.vram_ptr + bank_offset) = mem_value;
2109 memory_region_set_dirty(&s->vga.vram, bank_offset,
2110 sizeof(mem_value));
2111 } else {
2112 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2113 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2114 bank_offset,
2115 mem_value);
2116 } else {
2117 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2118 bank_offset,
2119 mem_value);
2120 }
2121 }
2122 }
2123 }
2124 } else if (addr >= 0x18000 && addr < 0x18100) {
2125 /* memory-mapped I/O */
2126 if ((s->vga.sr[0x17] & 0x44) == 0x04) {
2127 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2128 }
2129 } else {
2130 #ifdef DEBUG_CIRRUS
2131 printf("cirrus: mem_writeb " TARGET_FMT_plx " value 0x%02" PRIu64 "\n", addr,
2132 mem_value);
2133 #endif
2134 }
2135 }
2136
2137 static const MemoryRegionOps cirrus_vga_mem_ops = {
2138 .read = cirrus_vga_mem_read,
2139 .write = cirrus_vga_mem_write,
2140 .endianness = DEVICE_LITTLE_ENDIAN,
2141 .impl = {
2142 .min_access_size = 1,
2143 .max_access_size = 1,
2144 },
2145 };
2146
2147 /***************************************
2148 *
2149 * hardware cursor
2150 *
2151 ***************************************/
2152
2153 static inline void invalidate_cursor1(CirrusVGAState *s)
2154 {
2155 if (s->last_hw_cursor_size) {
2156 vga_invalidate_scanlines(&s->vga,
2157 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2158 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2159 }
2160 }
2161
2162 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2163 {
2164 const uint8_t *src;
2165 uint32_t content;
2166 int y, y_min, y_max;
2167
2168 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2169 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2170 src += (s->vga.sr[0x13] & 0x3c) * 256;
2171 y_min = 64;
2172 y_max = -1;
2173 for(y = 0; y < 64; y++) {
2174 content = ((uint32_t *)src)[0] |
2175 ((uint32_t *)src)[1] |
2176 ((uint32_t *)src)[2] |
2177 ((uint32_t *)src)[3];
2178 if (content) {
2179 if (y < y_min)
2180 y_min = y;
2181 if (y > y_max)
2182 y_max = y;
2183 }
2184 src += 16;
2185 }
2186 } else {
2187 src += (s->vga.sr[0x13] & 0x3f) * 256;
2188 y_min = 32;
2189 y_max = -1;
2190 for(y = 0; y < 32; y++) {
2191 content = ((uint32_t *)src)[0] |
2192 ((uint32_t *)(src + 128))[0];
2193 if (content) {
2194 if (y < y_min)
2195 y_min = y;
2196 if (y > y_max)
2197 y_max = y;
2198 }
2199 src += 4;
2200 }
2201 }
2202 if (y_min > y_max) {
2203 s->last_hw_cursor_y_start = 0;
2204 s->last_hw_cursor_y_end = 0;
2205 } else {
2206 s->last_hw_cursor_y_start = y_min;
2207 s->last_hw_cursor_y_end = y_max + 1;
2208 }
2209 }
2210
2211 /* NOTE: we do not currently handle the cursor bitmap change, so we
2212 update the cursor only if it moves. */
2213 static void cirrus_cursor_invalidate(VGACommonState *s1)
2214 {
2215 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2216 int size;
2217
2218 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW)) {
2219 size = 0;
2220 } else {
2221 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE)
2222 size = 64;
2223 else
2224 size = 32;
2225 }
2226 /* invalidate last cursor and new cursor if any change */
2227 if (s->last_hw_cursor_size != size ||
2228 s->last_hw_cursor_x != s->vga.hw_cursor_x ||
2229 s->last_hw_cursor_y != s->vga.hw_cursor_y) {
2230
2231 invalidate_cursor1(s);
2232
2233 s->last_hw_cursor_size = size;
2234 s->last_hw_cursor_x = s->vga.hw_cursor_x;
2235 s->last_hw_cursor_y = s->vga.hw_cursor_y;
2236 /* compute the real cursor min and max y */
2237 cirrus_cursor_compute_yrange(s);
2238 invalidate_cursor1(s);
2239 }
2240 }
2241
2242 static void vga_draw_cursor_line(uint8_t *d1,
2243 const uint8_t *src1,
2244 int poffset, int w,
2245 unsigned int color0,
2246 unsigned int color1,
2247 unsigned int color_xor)
2248 {
2249 const uint8_t *plane0, *plane1;
2250 int x, b0, b1;
2251 uint8_t *d;
2252
2253 d = d1;
2254 plane0 = src1;
2255 plane1 = src1 + poffset;
2256 for (x = 0; x < w; x++) {
2257 b0 = (plane0[x >> 3] >> (7 - (x & 7))) & 1;
2258 b1 = (plane1[x >> 3] >> (7 - (x & 7))) & 1;
2259 switch (b0 | (b1 << 1)) {
2260 case 0:
2261 break;
2262 case 1:
2263 ((uint32_t *)d)[0] ^= color_xor;
2264 break;
2265 case 2:
2266 ((uint32_t *)d)[0] = color0;
2267 break;
2268 case 3:
2269 ((uint32_t *)d)[0] = color1;
2270 break;
2271 }
2272 d += 4;
2273 }
2274 }
2275
2276 static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)
2277 {
2278 CirrusVGAState *s = container_of(s1, CirrusVGAState, vga);
2279 int w, h, x1, x2, poffset;
2280 unsigned int color0, color1;
2281 const uint8_t *palette, *src;
2282 uint32_t content;
2283
2284 if (!(s->vga.sr[0x12] & CIRRUS_CURSOR_SHOW))
2285 return;
2286 /* fast test to see if the cursor intersects with the scan line */
2287 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2288 h = 64;
2289 } else {
2290 h = 32;
2291 }
2292 if (scr_y < s->vga.hw_cursor_y ||
2293 scr_y >= (s->vga.hw_cursor_y + h)) {
2294 return;
2295 }
2296
2297 src = s->vga.vram_ptr + s->real_vram_size - 16 * 1024;
2298 if (s->vga.sr[0x12] & CIRRUS_CURSOR_LARGE) {
2299 src += (s->vga.sr[0x13] & 0x3c) * 256;
2300 src += (scr_y - s->vga.hw_cursor_y) * 16;
2301 poffset = 8;
2302 content = ((uint32_t *)src)[0] |
2303 ((uint32_t *)src)[1] |
2304 ((uint32_t *)src)[2] |
2305 ((uint32_t *)src)[3];
2306 } else {
2307 src += (s->vga.sr[0x13] & 0x3f) * 256;
2308 src += (scr_y - s->vga.hw_cursor_y) * 4;
2309
2310
2311 poffset = 128;
2312 content = ((uint32_t *)src)[0] |
2313 ((uint32_t *)(src + 128))[0];
2314 }
2315 /* if nothing to draw, no need to continue */
2316 if (!content)
2317 return;
2318 w = h;
2319
2320 x1 = s->vga.hw_cursor_x;
2321 if (x1 >= s->vga.last_scr_width)
2322 return;
2323 x2 = s->vga.hw_cursor_x + w;
2324 if (x2 > s->vga.last_scr_width)
2325 x2 = s->vga.last_scr_width;
2326 w = x2 - x1;
2327 palette = s->cirrus_hidden_palette;
2328 color0 = rgb_to_pixel32(c6_to_8(palette[0x0 * 3]),
2329 c6_to_8(palette[0x0 * 3 + 1]),
2330 c6_to_8(palette[0x0 * 3 + 2]));
2331 color1 = rgb_to_pixel32(c6_to_8(palette[0xf * 3]),
2332 c6_to_8(palette[0xf * 3 + 1]),
2333 c6_to_8(palette[0xf * 3 + 2]));
2334 d1 += x1 * 4;
2335 vga_draw_cursor_line(d1, src, poffset, w, color0, color1, 0xffffff);
2336 }
2337
2338 /***************************************
2339 *
2340 * LFB memory access
2341 *
2342 ***************************************/
2343
2344 static uint64_t cirrus_linear_read(void *opaque, hwaddr addr,
2345 unsigned size)
2346 {
2347 CirrusVGAState *s = opaque;
2348 uint32_t ret;
2349
2350 addr &= s->cirrus_addr_mask;
2351
2352 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2353 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2354 /* memory-mapped I/O */
2355 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2356 } else if (0) {
2357 /* XXX handle bitblt */
2358 ret = 0xff;
2359 } else {
2360 /* video memory */
2361 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2362 addr <<= 4;
2363 } else if (s->vga.gr[0x0B] & 0x02) {
2364 addr <<= 3;
2365 }
2366 addr &= s->cirrus_addr_mask;
2367 ret = *(s->vga.vram_ptr + addr);
2368 }
2369
2370 return ret;
2371 }
2372
2373 static void cirrus_linear_write(void *opaque, hwaddr addr,
2374 uint64_t val, unsigned size)
2375 {
2376 CirrusVGAState *s = opaque;
2377 unsigned mode;
2378
2379 addr &= s->cirrus_addr_mask;
2380
2381 if (((s->vga.sr[0x17] & 0x44) == 0x44) &&
2382 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2383 /* memory-mapped I/O */
2384 cirrus_mmio_blt_write(s, addr & 0xff, val);
2385 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2386 /* bitblt */
2387 *s->cirrus_srcptr++ = (uint8_t) val;
2388 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2389 cirrus_bitblt_cputovideo_next(s);
2390 }
2391 } else {
2392 /* video memory */
2393 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2394 addr <<= 4;
2395 } else if (s->vga.gr[0x0B] & 0x02) {
2396 addr <<= 3;
2397 }
2398 addr &= s->cirrus_addr_mask;
2399
2400 mode = s->vga.gr[0x05] & 0x7;
2401 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2402 *(s->vga.vram_ptr + addr) = (uint8_t) val;
2403 memory_region_set_dirty(&s->vga.vram, addr, 1);
2404 } else {
2405 if ((s->vga.gr[0x0B] & 0x14) != 0x14) {
2406 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2407 } else {
2408 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2409 }
2410 }
2411 }
2412 }
2413
2414 /***************************************
2415 *
2416 * system to screen memory access
2417 *
2418 ***************************************/
2419
2420
2421 static uint64_t cirrus_linear_bitblt_read(void *opaque,
2422 hwaddr addr,
2423 unsigned size)
2424 {
2425 CirrusVGAState *s = opaque;
2426 uint32_t ret;
2427
2428 /* XXX handle bitblt */
2429 (void)s;
2430 ret = 0xff;
2431 return ret;
2432 }
2433
2434 static void cirrus_linear_bitblt_write(void *opaque,
2435 hwaddr addr,
2436 uint64_t val,
2437 unsigned size)
2438 {
2439 CirrusVGAState *s = opaque;
2440
2441 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2442 /* bitblt */
2443 *s->cirrus_srcptr++ = (uint8_t) val;
2444 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2445 cirrus_bitblt_cputovideo_next(s);
2446 }
2447 }
2448 }
2449
2450 static const MemoryRegionOps cirrus_linear_bitblt_io_ops = {
2451 .read = cirrus_linear_bitblt_read,
2452 .write = cirrus_linear_bitblt_write,
2453 .endianness = DEVICE_LITTLE_ENDIAN,
2454 .impl = {
2455 .min_access_size = 1,
2456 .max_access_size = 1,
2457 },
2458 };
2459
2460 static void map_linear_vram_bank(CirrusVGAState *s, unsigned bank)
2461 {
2462 MemoryRegion *mr = &s->cirrus_bank[bank];
2463 bool enabled = !(s->cirrus_srcptr != s->cirrus_srcptr_end)
2464 && !((s->vga.sr[0x07] & 0x01) == 0)
2465 && !((s->vga.gr[0x0B] & 0x14) == 0x14)
2466 && !(s->vga.gr[0x0B] & 0x02);
2467
2468 memory_region_set_enabled(mr, enabled);
2469 memory_region_set_alias_offset(mr, s->cirrus_bank_base[bank]);
2470 }
2471
2472 static void map_linear_vram(CirrusVGAState *s)
2473 {
2474 if (s->bustype == CIRRUS_BUSTYPE_PCI && !s->linear_vram) {
2475 s->linear_vram = true;
2476 memory_region_add_subregion_overlap(&s->pci_bar, 0, &s->vga.vram, 1);
2477 }
2478 map_linear_vram_bank(s, 0);
2479 map_linear_vram_bank(s, 1);
2480 }
2481
2482 static void unmap_linear_vram(CirrusVGAState *s)
2483 {
2484 if (s->bustype == CIRRUS_BUSTYPE_PCI && s->linear_vram) {
2485 s->linear_vram = false;
2486 memory_region_del_subregion(&s->pci_bar, &s->vga.vram);
2487 }
2488 memory_region_set_enabled(&s->cirrus_bank[0], false);
2489 memory_region_set_enabled(&s->cirrus_bank[1], false);
2490 }
2491
2492 /* Compute the memory access functions */
2493 static void cirrus_update_memory_access(CirrusVGAState *s)
2494 {
2495 unsigned mode;
2496
2497 memory_region_transaction_begin();
2498 if ((s->vga.sr[0x17] & 0x44) == 0x44) {
2499 goto generic_io;
2500 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2501 goto generic_io;
2502 } else {
2503 if ((s->vga.gr[0x0B] & 0x14) == 0x14) {
2504 goto generic_io;
2505 } else if (s->vga.gr[0x0B] & 0x02) {
2506 goto generic_io;
2507 }
2508
2509 mode = s->vga.gr[0x05] & 0x7;
2510 if (mode < 4 || mode > 5 || ((s->vga.gr[0x0B] & 0x4) == 0)) {
2511 map_linear_vram(s);
2512 } else {
2513 generic_io:
2514 unmap_linear_vram(s);
2515 }
2516 }
2517 memory_region_transaction_commit();
2518 }
2519
2520
2521 /* I/O ports */
2522
2523 static uint64_t cirrus_vga_ioport_read(void *opaque, hwaddr addr,
2524 unsigned size)
2525 {
2526 CirrusVGAState *c = opaque;
2527 VGACommonState *s = &c->vga;
2528 int val, index;
2529
2530 addr += 0x3b0;
2531
2532 if (vga_ioport_invalid(s, addr)) {
2533 val = 0xff;
2534 } else {
2535 switch (addr) {
2536 case 0x3c0:
2537 if (s->ar_flip_flop == 0) {
2538 val = s->ar_index;
2539 } else {
2540 val = 0;
2541 }
2542 break;
2543 case 0x3c1:
2544 index = s->ar_index & 0x1f;
2545 if (index < 21)
2546 val = s->ar[index];
2547 else
2548 val = 0;
2549 break;
2550 case 0x3c2:
2551 val = s->st00;
2552 break;
2553 case 0x3c4:
2554 val = s->sr_index;
2555 break;
2556 case 0x3c5:
2557 val = cirrus_vga_read_sr(c);
2558 break;
2559 #ifdef DEBUG_VGA_REG
2560 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2561 #endif
2562 break;
2563 case 0x3c6:
2564 val = cirrus_read_hidden_dac(c);
2565 break;
2566 case 0x3c7:
2567 val = s->dac_state;
2568 break;
2569 case 0x3c8:
2570 val = s->dac_write_index;
2571 c->cirrus_hidden_dac_lockindex = 0;
2572 break;
2573 case 0x3c9:
2574 val = cirrus_vga_read_palette(c);
2575 break;
2576 case 0x3ca:
2577 val = s->fcr;
2578 break;
2579 case 0x3cc:
2580 val = s->msr;
2581 break;
2582 case 0x3ce:
2583 val = s->gr_index;
2584 break;
2585 case 0x3cf:
2586 val = cirrus_vga_read_gr(c, s->gr_index);
2587 #ifdef DEBUG_VGA_REG
2588 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2589 #endif
2590 break;
2591 case 0x3b4:
2592 case 0x3d4:
2593 val = s->cr_index;
2594 break;
2595 case 0x3b5:
2596 case 0x3d5:
2597 val = cirrus_vga_read_cr(c, s->cr_index);
2598 #ifdef DEBUG_VGA_REG
2599 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2600 #endif
2601 break;
2602 case 0x3ba:
2603 case 0x3da:
2604 /* just toggle to fool polling */
2605 val = s->st01 = s->retrace(s);
2606 s->ar_flip_flop = 0;
2607 break;
2608 default:
2609 val = 0x00;
2610 break;
2611 }
2612 }
2613 trace_vga_cirrus_read_io(addr, val);
2614 return val;
2615 }
2616
2617 static void cirrus_vga_ioport_write(void *opaque, hwaddr addr, uint64_t val,
2618 unsigned size)
2619 {
2620 CirrusVGAState *c = opaque;
2621 VGACommonState *s = &c->vga;
2622 int index;
2623
2624 addr += 0x3b0;
2625
2626 /* check port range access depending on color/monochrome mode */
2627 if (vga_ioport_invalid(s, addr)) {
2628 return;
2629 }
2630 trace_vga_cirrus_write_io(addr, val);
2631
2632 switch (addr) {
2633 case 0x3c0:
2634 if (s->ar_flip_flop == 0) {
2635 val &= 0x3f;
2636 s->ar_index = val;
2637 } else {
2638 index = s->ar_index & 0x1f;
2639 switch (index) {
2640 case 0x00 ... 0x0f:
2641 s->ar[index] = val & 0x3f;
2642 break;
2643 case 0x10:
2644 s->ar[index] = val & ~0x10;
2645 break;
2646 case 0x11:
2647 s->ar[index] = val;
2648 break;
2649 case 0x12:
2650 s->ar[index] = val & ~0xc0;
2651 break;
2652 case 0x13:
2653 s->ar[index] = val & ~0xf0;
2654 break;
2655 case 0x14:
2656 s->ar[index] = val & ~0xf0;
2657 break;
2658 default:
2659 break;
2660 }
2661 }
2662 s->ar_flip_flop ^= 1;
2663 break;
2664 case 0x3c2:
2665 s->msr = val & ~0x10;
2666 s->update_retrace_info(s);
2667 break;
2668 case 0x3c4:
2669 s->sr_index = val;
2670 break;
2671 case 0x3c5:
2672 #ifdef DEBUG_VGA_REG
2673 printf("vga: write SR%x = 0x%02" PRIu64 "\n", s->sr_index, val);
2674 #endif
2675 cirrus_vga_write_sr(c, val);
2676 break;
2677 case 0x3c6:
2678 cirrus_write_hidden_dac(c, val);
2679 break;
2680 case 0x3c7:
2681 s->dac_read_index = val;
2682 s->dac_sub_index = 0;
2683 s->dac_state = 3;
2684 break;
2685 case 0x3c8:
2686 s->dac_write_index = val;
2687 s->dac_sub_index = 0;
2688 s->dac_state = 0;
2689 break;
2690 case 0x3c9:
2691 cirrus_vga_write_palette(c, val);
2692 break;
2693 case 0x3ce:
2694 s->gr_index = val;
2695 break;
2696 case 0x3cf:
2697 #ifdef DEBUG_VGA_REG
2698 printf("vga: write GR%x = 0x%02" PRIu64 "\n", s->gr_index, val);
2699 #endif
2700 cirrus_vga_write_gr(c, s->gr_index, val);
2701 break;
2702 case 0x3b4:
2703 case 0x3d4:
2704 s->cr_index = val;
2705 break;
2706 case 0x3b5:
2707 case 0x3d5:
2708 #ifdef DEBUG_VGA_REG
2709 printf("vga: write CR%x = 0x%02"PRIu64"\n", s->cr_index, val);
2710 #endif
2711 cirrus_vga_write_cr(c, val);
2712 break;
2713 case 0x3ba:
2714 case 0x3da:
2715 s->fcr = val & 0x10;
2716 break;
2717 }
2718 }
2719
2720 /***************************************
2721 *
2722 * memory-mapped I/O access
2723 *
2724 ***************************************/
2725
2726 static uint64_t cirrus_mmio_read(void *opaque, hwaddr addr,
2727 unsigned size)
2728 {
2729 CirrusVGAState *s = opaque;
2730
2731 if (addr >= 0x100) {
2732 return cirrus_mmio_blt_read(s, addr - 0x100);
2733 } else {
2734 return cirrus_vga_ioport_read(s, addr + 0x10, size);
2735 }
2736 }
2737
2738 static void cirrus_mmio_write(void *opaque, hwaddr addr,
2739 uint64_t val, unsigned size)
2740 {
2741 CirrusVGAState *s = opaque;
2742
2743 if (addr >= 0x100) {
2744 cirrus_mmio_blt_write(s, addr - 0x100, val);
2745 } else {
2746 cirrus_vga_ioport_write(s, addr + 0x10, val, size);
2747 }
2748 }
2749
2750 static const MemoryRegionOps cirrus_mmio_io_ops = {
2751 .read = cirrus_mmio_read,
2752 .write = cirrus_mmio_write,
2753 .endianness = DEVICE_LITTLE_ENDIAN,
2754 .impl = {
2755 .min_access_size = 1,
2756 .max_access_size = 1,
2757 },
2758 };
2759
2760 /* load/save state */
2761
2762 static int cirrus_post_load(void *opaque, int version_id)
2763 {
2764 CirrusVGAState *s = opaque;
2765
2766 s->vga.gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
2767 s->vga.gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
2768
2769 cirrus_update_memory_access(s);
2770 /* force refresh */
2771 s->vga.graphic_mode = -1;
2772 cirrus_update_bank_ptr(s, 0);
2773 cirrus_update_bank_ptr(s, 1);
2774 return 0;
2775 }
2776
2777 static const VMStateDescription vmstate_cirrus_vga = {
2778 .name = "cirrus_vga",
2779 .version_id = 2,
2780 .minimum_version_id = 1,
2781 .post_load = cirrus_post_load,
2782 .fields = (VMStateField[]) {
2783 VMSTATE_UINT32(vga.latch, CirrusVGAState),
2784 VMSTATE_UINT8(vga.sr_index, CirrusVGAState),
2785 VMSTATE_BUFFER(vga.sr, CirrusVGAState),
2786 VMSTATE_UINT8(vga.gr_index, CirrusVGAState),
2787 VMSTATE_UINT8(cirrus_shadow_gr0, CirrusVGAState),
2788 VMSTATE_UINT8(cirrus_shadow_gr1, CirrusVGAState),
2789 VMSTATE_BUFFER_START_MIDDLE(vga.gr, CirrusVGAState, 2),
2790 VMSTATE_UINT8(vga.ar_index, CirrusVGAState),
2791 VMSTATE_BUFFER(vga.ar, CirrusVGAState),
2792 VMSTATE_INT32(vga.ar_flip_flop, CirrusVGAState),
2793 VMSTATE_UINT8(vga.cr_index, CirrusVGAState),
2794 VMSTATE_BUFFER(vga.cr, CirrusVGAState),
2795 VMSTATE_UINT8(vga.msr, CirrusVGAState),
2796 VMSTATE_UINT8(vga.fcr, CirrusVGAState),
2797 VMSTATE_UINT8(vga.st00, CirrusVGAState),
2798 VMSTATE_UINT8(vga.st01, CirrusVGAState),
2799 VMSTATE_UINT8(vga.dac_state, CirrusVGAState),
2800 VMSTATE_UINT8(vga.dac_sub_index, CirrusVGAState),
2801 VMSTATE_UINT8(vga.dac_read_index, CirrusVGAState),
2802 VMSTATE_UINT8(vga.dac_write_index, CirrusVGAState),
2803 VMSTATE_BUFFER(vga.dac_cache, CirrusVGAState),
2804 VMSTATE_BUFFER(vga.palette, CirrusVGAState),
2805 VMSTATE_INT32(vga.bank_offset, CirrusVGAState),
2806 VMSTATE_UINT8(cirrus_hidden_dac_lockindex, CirrusVGAState),
2807 VMSTATE_UINT8(cirrus_hidden_dac_data, CirrusVGAState),
2808 VMSTATE_UINT32(vga.hw_cursor_x, CirrusVGAState),
2809 VMSTATE_UINT32(vga.hw_cursor_y, CirrusVGAState),
2810 /* XXX: we do not save the bitblt state - we assume we do not save
2811 the state when the blitter is active */
2812 VMSTATE_END_OF_LIST()
2813 }
2814 };
2815
2816 static const VMStateDescription vmstate_pci_cirrus_vga = {
2817 .name = "cirrus_vga",
2818 .version_id = 2,
2819 .minimum_version_id = 2,
2820 .fields = (VMStateField[]) {
2821 VMSTATE_PCI_DEVICE(dev, PCICirrusVGAState),
2822 VMSTATE_STRUCT(cirrus_vga, PCICirrusVGAState, 0,
2823 vmstate_cirrus_vga, CirrusVGAState),
2824 VMSTATE_END_OF_LIST()
2825 }
2826 };
2827
2828 /***************************************
2829 *
2830 * initialize
2831 *
2832 ***************************************/
2833
2834 static void cirrus_reset(void *opaque)
2835 {
2836 CirrusVGAState *s = opaque;
2837
2838 vga_common_reset(&s->vga);
2839 unmap_linear_vram(s);
2840 s->vga.sr[0x06] = 0x0f;
2841 if (s->device_id == CIRRUS_ID_CLGD5446) {
2842 /* 4MB 64 bit memory config, always PCI */
2843 s->vga.sr[0x1F] = 0x2d; // MemClock
2844 s->vga.gr[0x18] = 0x0f; // fastest memory configuration
2845 s->vga.sr[0x0f] = 0x98;
2846 s->vga.sr[0x17] = 0x20;
2847 s->vga.sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
2848 } else {
2849 s->vga.sr[0x1F] = 0x22; // MemClock
2850 s->vga.sr[0x0F] = CIRRUS_MEMSIZE_2M;
2851 s->vga.sr[0x17] = s->bustype;
2852 s->vga.sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
2853 }
2854 s->vga.cr[0x27] = s->device_id;
2855
2856 s->cirrus_hidden_dac_lockindex = 5;
2857 s->cirrus_hidden_dac_data = 0;
2858 }
2859
2860 static const MemoryRegionOps cirrus_linear_io_ops = {
2861 .read = cirrus_linear_read,
2862 .write = cirrus_linear_write,
2863 .endianness = DEVICE_LITTLE_ENDIAN,
2864 .impl = {
2865 .min_access_size = 1,
2866 .max_access_size = 1,
2867 },
2868 };
2869
2870 static const MemoryRegionOps cirrus_vga_io_ops = {
2871 .read = cirrus_vga_ioport_read,
2872 .write = cirrus_vga_ioport_write,
2873 .endianness = DEVICE_LITTLE_ENDIAN,
2874 .impl = {
2875 .min_access_size = 1,
2876 .max_access_size = 1,
2877 },
2878 };
2879
2880 static void cirrus_init_common(CirrusVGAState *s, Object *owner,
2881 int device_id, int is_pci,
2882 MemoryRegion *system_memory,
2883 MemoryRegion *system_io)
2884 {
2885 int i;
2886 static int inited;
2887
2888 if (!inited) {
2889 inited = 1;
2890 for(i = 0;i < 256; i++)
2891 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
2892 rop_to_index[CIRRUS_ROP_0] = 0;
2893 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
2894 rop_to_index[CIRRUS_ROP_NOP] = 2;
2895 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
2896 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
2897 rop_to_index[CIRRUS_ROP_SRC] = 5;
2898 rop_to_index[CIRRUS_ROP_1] = 6;
2899 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
2900 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
2901 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
2902 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
2903 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
2904 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
2905 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
2906 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
2907 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
2908 s->device_id = device_id;
2909 if (is_pci)
2910 s->bustype = CIRRUS_BUSTYPE_PCI;
2911 else
2912 s->bustype = CIRRUS_BUSTYPE_ISA;
2913 }
2914
2915 /* Register ioport 0x3b0 - 0x3df */
2916 memory_region_init_io(&s->cirrus_vga_io, owner, &cirrus_vga_io_ops, s,
2917 "cirrus-io", 0x30);
2918 memory_region_set_flush_coalesced(&s->cirrus_vga_io);
2919 memory_region_add_subregion(system_io, 0x3b0, &s->cirrus_vga_io);
2920
2921 memory_region_init(&s->low_mem_container, owner,
2922 "cirrus-lowmem-container",
2923 0x20000);
2924
2925 memory_region_init_io(&s->low_mem, owner, &cirrus_vga_mem_ops, s,
2926 "cirrus-low-memory", 0x20000);
2927 memory_region_add_subregion(&s->low_mem_container, 0, &s->low_mem);
2928 for (i = 0; i < 2; ++i) {
2929 static const char *names[] = { "vga.bank0", "vga.bank1" };
2930 MemoryRegion *bank = &s->cirrus_bank[i];
2931 memory_region_init_alias(bank, owner, names[i], &s->vga.vram,
2932 0, 0x8000);
2933 memory_region_set_enabled(bank, false);
2934 memory_region_add_subregion_overlap(&s->low_mem_container, i * 0x8000,
2935 bank, 1);
2936 }
2937 memory_region_add_subregion_overlap(system_memory,
2938 0x000a0000,
2939 &s->low_mem_container,
2940 1);
2941 memory_region_set_coalescing(&s->low_mem);
2942
2943 /* I/O handler for LFB */
2944 memory_region_init_io(&s->cirrus_linear_io, owner, &cirrus_linear_io_ops, s,
2945 "cirrus-linear-io", s->vga.vram_size_mb
2946 * 1024 * 1024);
2947 memory_region_set_flush_coalesced(&s->cirrus_linear_io);
2948
2949 /* I/O handler for LFB */
2950 memory_region_init_io(&s->cirrus_linear_bitblt_io, owner,
2951 &cirrus_linear_bitblt_io_ops,
2952 s,
2953 "cirrus-bitblt-mmio",
2954 0x400000);
2955 memory_region_set_flush_coalesced(&s->cirrus_linear_bitblt_io);
2956
2957 /* I/O handler for memory-mapped I/O */
2958 memory_region_init_io(&s->cirrus_mmio_io, owner, &cirrus_mmio_io_ops, s,
2959 "cirrus-mmio", CIRRUS_PNPMMIO_SIZE);
2960 memory_region_set_flush_coalesced(&s->cirrus_mmio_io);
2961
2962 s->real_vram_size =
2963 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
2964
2965 /* XXX: s->vga.vram_size must be a power of two */
2966 s->cirrus_addr_mask = s->real_vram_size - 1;
2967 s->linear_mmio_mask = s->real_vram_size - 256;
2968
2969 s->vga.get_bpp = cirrus_get_bpp;
2970 s->vga.get_offsets = cirrus_get_offsets;
2971 s->vga.get_resolution = cirrus_get_resolution;
2972 s->vga.cursor_invalidate = cirrus_cursor_invalidate;
2973 s->vga.cursor_draw_line = cirrus_cursor_draw_line;
2974
2975 qemu_register_reset(cirrus_reset, s);
2976 }
2977
2978 /***************************************
2979 *
2980 * ISA bus support
2981 *
2982 ***************************************/
2983
2984 static void isa_cirrus_vga_realizefn(DeviceState *dev, Error **errp)
2985 {
2986 ISADevice *isadev = ISA_DEVICE(dev);
2987 ISACirrusVGAState *d = ISA_CIRRUS_VGA(dev);
2988 VGACommonState *s = &d->cirrus_vga.vga;
2989
2990 /* follow real hardware, cirrus card emulated has 4 MB video memory.
2991 Also accept 8 MB/16 MB for backward compatibility. */
2992 if (s->vram_size_mb != 4 && s->vram_size_mb != 8 &&
2993 s->vram_size_mb != 16) {
2994 error_setg(errp, "Invalid cirrus_vga ram size '%u'",
2995 s->vram_size_mb);
2996 return;
2997 }
2998 vga_common_init(s, OBJECT(dev), true);
2999 cirrus_init_common(&d->cirrus_vga, OBJECT(dev), CIRRUS_ID_CLGD5430, 0,
3000 isa_address_space(isadev),
3001 isa_address_space_io(isadev));
3002 s->con = graphic_console_init(dev, 0, s->hw_ops, s);
3003 rom_add_vga(VGABIOS_CIRRUS_FILENAME);
3004 /* XXX ISA-LFB support */
3005 /* FIXME not qdev yet */
3006 }
3007
3008 static Property isa_cirrus_vga_properties[] = {
3009 DEFINE_PROP_UINT32("vgamem_mb", struct ISACirrusVGAState,
3010 cirrus_vga.vga.vram_size_mb, 8),
3011 DEFINE_PROP_END_OF_LIST(),
3012 };
3013
3014 static void isa_cirrus_vga_class_init(ObjectClass *klass, void *data)
3015 {
3016 DeviceClass *dc = DEVICE_CLASS(klass);
3017
3018 dc->vmsd = &vmstate_cirrus_vga;
3019 dc->realize = isa_cirrus_vga_realizefn;
3020 dc->props = isa_cirrus_vga_properties;
3021 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
3022 }
3023
3024 static const TypeInfo isa_cirrus_vga_info = {
3025 .name = TYPE_ISA_CIRRUS_VGA,
3026 .parent = TYPE_ISA_DEVICE,
3027 .instance_size = sizeof(ISACirrusVGAState),
3028 .class_init = isa_cirrus_vga_class_init,
3029 };
3030
3031 /***************************************
3032 *
3033 * PCI bus support
3034 *
3035 ***************************************/
3036
3037 static void pci_cirrus_vga_realize(PCIDevice *dev, Error **errp)
3038 {
3039 PCICirrusVGAState *d = PCI_CIRRUS_VGA(dev);
3040 CirrusVGAState *s = &d->cirrus_vga;
3041 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
3042 int16_t device_id = pc->device_id;
3043
3044 /* follow real hardware, cirrus card emulated has 4 MB video memory.
3045 Also accept 8 MB/16 MB for backward compatibility. */
3046 if (s->vga.vram_size_mb != 4 && s->vga.vram_size_mb != 8 &&
3047 s->vga.vram_size_mb != 16) {
3048 error_setg(errp, "Invalid cirrus_vga ram size '%u'",
3049 s->vga.vram_size_mb);
3050 return;
3051 }
3052 /* setup VGA */
3053 vga_common_init(&s->vga, OBJECT(dev), true);
3054 cirrus_init_common(s, OBJECT(dev), device_id, 1, pci_address_space(dev),
3055 pci_address_space_io(dev));
3056 s->vga.con = graphic_console_init(DEVICE(dev), 0, s->vga.hw_ops, &s->vga);
3057
3058 /* setup PCI */
3059
3060 memory_region_init(&s->pci_bar, OBJECT(dev), "cirrus-pci-bar0", 0x2000000);
3061
3062 /* XXX: add byte swapping apertures */
3063 memory_region_add_subregion(&s->pci_bar, 0, &s->cirrus_linear_io);
3064 memory_region_add_subregion(&s->pci_bar, 0x1000000,
3065 &s->cirrus_linear_bitblt_io);
3066
3067 /* setup memory space */
3068 /* memory #0 LFB */
3069 /* memory #1 memory-mapped I/O */
3070 /* XXX: s->vga.vram_size must be a power of two */
3071 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->pci_bar);
3072 if (device_id == CIRRUS_ID_CLGD5446) {
3073 pci_register_bar(&d->dev, 1, 0, &s->cirrus_mmio_io);
3074 }
3075 }
3076
3077 static Property pci_vga_cirrus_properties[] = {
3078 DEFINE_PROP_UINT32("vgamem_mb", struct PCICirrusVGAState,
3079 cirrus_vga.vga.vram_size_mb, 8),
3080 DEFINE_PROP_END_OF_LIST(),
3081 };
3082
3083 static void cirrus_vga_class_init(ObjectClass *klass, void *data)
3084 {
3085 DeviceClass *dc = DEVICE_CLASS(klass);
3086 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3087
3088 k->realize = pci_cirrus_vga_realize;
3089 k->romfile = VGABIOS_CIRRUS_FILENAME;
3090 k->vendor_id = PCI_VENDOR_ID_CIRRUS;
3091 k->device_id = CIRRUS_ID_CLGD5446;
3092 k->class_id = PCI_CLASS_DISPLAY_VGA;
3093 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
3094 dc->desc = "Cirrus CLGD 54xx VGA";
3095 dc->vmsd = &vmstate_pci_cirrus_vga;
3096 dc->props = pci_vga_cirrus_properties;
3097 dc->hotpluggable = false;
3098 }
3099
3100 static const TypeInfo cirrus_vga_info = {
3101 .name = TYPE_PCI_CIRRUS_VGA,
3102 .parent = TYPE_PCI_DEVICE,
3103 .instance_size = sizeof(PCICirrusVGAState),
3104 .class_init = cirrus_vga_class_init,
3105 };
3106
3107 static void cirrus_vga_register_types(void)
3108 {
3109 type_register_static(&isa_cirrus_vga_info);
3110 type_register_static(&cirrus_vga_info);
3111 }
3112
3113 type_init(cirrus_vga_register_types)
AR7 emulation for QEMU