1 /* Support for generating ACPI tables and passing them to Guests
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
7 * Author: Michael S. Tsirkin <mst@redhat.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qapi/qmp/qnum.h"
26 #include "acpi-build.h"
27 #include "acpi-common.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
31 #include "hw/core/cpu.h"
32 #include "target/i386/cpu.h"
33 #include "hw/misc/pvpanic.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/acpi/cpu.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/block/fdc.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "hw/acpi/vmgenid.h"
46 #include "sysemu/tpm_backend.h"
47 #include "hw/rtc/mc146818rtc_regs.h"
48 #include "migration/vmstate.h"
49 #include "hw/mem/memory-device.h"
50 #include "hw/mem/nvdimm.h"
51 #include "sysemu/numa.h"
52 #include "sysemu/reset.h"
53 #include "hw/hyperv/vmbus-bridge.h"
55 /* Supported chipsets: */
56 #include "hw/southbridge/piix.h"
57 #include "hw/acpi/pcihp.h"
58 #include "hw/i386/fw_cfg.h"
59 #include "hw/i386/ich9.h"
60 #include "hw/pci/pci_bus.h"
61 #include "hw/pci-host/q35.h"
62 #include "hw/i386/x86-iommu.h"
64 #include "hw/acpi/aml-build.h"
65 #include "hw/acpi/utils.h"
66 #include "hw/acpi/pci.h"
68 #include "qom/qom-qobject.h"
69 #include "hw/i386/amd_iommu.h"
70 #include "hw/i386/intel_iommu.h"
72 #include "hw/acpi/ipmi.h"
73 #include "hw/acpi/hmat.h"
75 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
76 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
77 * a little bit, there should be plenty of free space since the DSDT
78 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
80 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
81 #define ACPI_BUILD_ALIGN_SIZE 0x1000
83 #define ACPI_BUILD_TABLE_SIZE 0x20000
85 /* #define DEBUG_ACPI_BUILD */
86 #ifdef DEBUG_ACPI_BUILD
87 #define ACPI_BUILD_DPRINTF(fmt, ...) \
88 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
90 #define ACPI_BUILD_DPRINTF(fmt, ...)
93 typedef struct AcpiPmInfo
{
98 bool smi_on_cpu_unplug
;
102 uint16_t cpu_hp_io_base
;
103 uint16_t pcihp_io_base
;
104 uint16_t pcihp_io_len
;
107 typedef struct AcpiMiscInfo
{
110 TPMVersion tpm_version
;
111 const unsigned char *dsdt_code
;
113 uint16_t pvpanic_port
;
114 uint16_t applesmc_io_base
;
117 typedef struct AcpiBuildPciBusHotplugState
{
118 GArray
*device_table
;
119 GArray
*notify_table
;
120 struct AcpiBuildPciBusHotplugState
*parent
;
121 bool pcihp_bridge_en
;
122 } AcpiBuildPciBusHotplugState
;
124 typedef struct FwCfgTPMConfig
{
125 uint32_t tpmppi_address
;
127 uint8_t tpmppi_version
;
128 } QEMU_PACKED FwCfgTPMConfig
;
130 static bool acpi_get_mcfg(AcpiMcfgInfo
*mcfg
);
132 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio
= {
133 .space_id
= AML_AS_SYSTEM_IO
,
134 .address
= NVDIMM_ACPI_IO_BASE
,
135 .bit_width
= NVDIMM_ACPI_IO_LEN
<< 3
138 static void init_common_fadt_data(MachineState
*ms
, Object
*o
,
141 X86MachineState
*x86ms
= X86_MACHINE(ms
);
143 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old
144 * behavior for compatibility irrelevant to smm_enabled, which doesn't
145 * comforms to ACPI spec.
147 bool smm_enabled
= object_property_get_bool(o
, "smm-compat", NULL
) ?
148 true : x86_machine_is_smm_enabled(x86ms
);
149 uint32_t io
= object_property_get_uint(o
, ACPI_PM_PROP_PM_IO_BASE
, NULL
);
150 AmlAddressSpace as
= AML_AS_SYSTEM_IO
;
151 AcpiFadtData fadt
= {
154 (1 << ACPI_FADT_F_WBINVD
) |
155 (1 << ACPI_FADT_F_PROC_C1
) |
156 (1 << ACPI_FADT_F_SLP_BUTTON
) |
157 (1 << ACPI_FADT_F_RTC_S4
) |
158 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK
) |
159 /* APIC destination mode ("Flat Logical") has an upper limit of 8
160 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
163 ((ms
->smp
.max_cpus
> 8) ?
164 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL
) : 0),
165 .int_model
= 1 /* Multiple APIC */,
166 .rtc_century
= RTC_CENTURY
,
167 .plvl2_lat
= 0xfff /* C2 state not supported */,
168 .plvl3_lat
= 0xfff /* C3 state not supported */,
169 .smi_cmd
= smm_enabled
? ACPI_PORT_SMI_CMD
: 0,
170 .sci_int
= object_property_get_uint(o
, ACPI_PM_PROP_SCI_INT
, NULL
),
173 object_property_get_uint(o
, ACPI_PM_PROP_ACPI_ENABLE_CMD
, NULL
) :
177 object_property_get_uint(o
, ACPI_PM_PROP_ACPI_DISABLE_CMD
, NULL
) :
179 .pm1a_evt
= { .space_id
= as
, .bit_width
= 4 * 8, .address
= io
},
180 .pm1a_cnt
= { .space_id
= as
, .bit_width
= 2 * 8,
181 .address
= io
+ 0x04 },
182 .pm_tmr
= { .space_id
= as
, .bit_width
= 4 * 8, .address
= io
+ 0x08 },
183 .gpe0_blk
= { .space_id
= as
, .bit_width
=
184 object_property_get_uint(o
, ACPI_PM_PROP_GPE0_BLK_LEN
, NULL
) * 8,
185 .address
= object_property_get_uint(o
, ACPI_PM_PROP_GPE0_BLK
, NULL
)
191 static Object
*object_resolve_type_unambiguous(const char *typename
)
194 Object
*o
= object_resolve_path_type("", typename
, &ambig
);
202 static void acpi_get_pm_info(MachineState
*machine
, AcpiPmInfo
*pm
)
204 Object
*piix
= object_resolve_type_unambiguous(TYPE_PIIX4_PM
);
205 Object
*lpc
= object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE
);
206 Object
*obj
= piix
? piix
: lpc
;
208 pm
->cpu_hp_io_base
= 0;
209 pm
->pcihp_io_base
= 0;
210 pm
->pcihp_io_len
= 0;
211 pm
->smi_on_cpuhp
= false;
212 pm
->smi_on_cpu_unplug
= false;
215 init_common_fadt_data(machine
, obj
, &pm
->fadt
);
217 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
219 pm
->cpu_hp_io_base
= PIIX4_CPU_HOTPLUG_IO_BASE
;
221 object_property_get_uint(obj
, ACPI_PCIHP_IO_BASE_PROP
, NULL
);
223 object_property_get_uint(obj
, ACPI_PCIHP_IO_LEN_PROP
, NULL
);
226 uint64_t smi_features
= object_property_get_uint(lpc
,
227 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP
, NULL
);
228 struct AcpiGenericAddress r
= { .space_id
= AML_AS_SYSTEM_IO
,
229 .bit_width
= 8, .address
= ICH9_RST_CNT_IOPORT
};
230 pm
->fadt
.reset_reg
= r
;
231 pm
->fadt
.reset_val
= 0xf;
232 pm
->fadt
.flags
|= 1 << ACPI_FADT_F_RESET_REG_SUP
;
233 pm
->cpu_hp_io_base
= ICH9_CPU_HOTPLUG_IO_BASE
;
235 !!(smi_features
& BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT
));
236 pm
->smi_on_cpu_unplug
=
237 !!(smi_features
& BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT
));
240 /* The above need not be conditional on machine type because the reset port
241 * happens to be the same on PIIX (pc) and ICH9 (q35). */
242 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT
!= PIIX_RCR_IOPORT
);
244 /* Fill in optional s3/s4 related properties */
245 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S3_DISABLED
, NULL
);
247 pm
->s3_disabled
= qnum_get_uint(qobject_to(QNum
, o
));
249 pm
->s3_disabled
= false;
252 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_DISABLED
, NULL
);
254 pm
->s4_disabled
= qnum_get_uint(qobject_to(QNum
, o
));
256 pm
->s4_disabled
= false;
259 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_VAL
, NULL
);
261 pm
->s4_val
= qnum_get_uint(qobject_to(QNum
, o
));
267 pm
->pcihp_bridge_en
=
268 object_property_get_bool(obj
, "acpi-pci-hotplug-with-bridge-support",
271 object_property_get_bool(obj
, "acpi-root-pci-hotplug",
275 static void acpi_get_misc_info(AcpiMiscInfo
*info
)
277 Object
*piix
= object_resolve_type_unambiguous(TYPE_PIIX4_PM
);
278 Object
*lpc
= object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE
);
279 assert(!!piix
!= !!lpc
);
282 info
->is_piix4
= true;
285 info
->is_piix4
= false;
288 info
->has_hpet
= hpet_find();
289 info
->tpm_version
= tpm_get_version(tpm_find());
290 info
->pvpanic_port
= pvpanic_port();
291 info
->applesmc_io_base
= applesmc_port();
295 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
296 * On i386 arch we only have two pci hosts, so we can look only for them.
298 static Object
*acpi_get_i386_pci_host(void)
302 host
= OBJECT_CHECK(PCIHostState
,
303 object_resolve_path("/machine/i440fx", NULL
),
304 TYPE_PCI_HOST_BRIDGE
);
306 host
= OBJECT_CHECK(PCIHostState
,
307 object_resolve_path("/machine/q35", NULL
),
308 TYPE_PCI_HOST_BRIDGE
);
314 static void acpi_get_pci_holes(Range
*hole
, Range
*hole64
)
318 pci_host
= acpi_get_i386_pci_host();
321 range_set_bounds1(hole
,
322 object_property_get_uint(pci_host
,
323 PCI_HOST_PROP_PCI_HOLE_START
,
325 object_property_get_uint(pci_host
,
326 PCI_HOST_PROP_PCI_HOLE_END
,
328 range_set_bounds1(hole64
,
329 object_property_get_uint(pci_host
,
330 PCI_HOST_PROP_PCI_HOLE64_START
,
332 object_property_get_uint(pci_host
,
333 PCI_HOST_PROP_PCI_HOLE64_END
,
337 static void acpi_align_size(GArray
*blob
, unsigned align
)
339 /* Align size to multiple of given size. This reduces the chance
340 * we need to change size in the future (breaking cross version migration).
342 g_array_set_size(blob
, ROUND_UP(acpi_data_len(blob
), align
));
347 build_facs(GArray
*table_data
)
349 AcpiFacsDescriptorRev1
*facs
= acpi_data_push(table_data
, sizeof *facs
);
350 memcpy(&facs
->signature
, "FACS", 4);
351 facs
->length
= cpu_to_le32(sizeof(*facs
));
354 static void build_append_pcihp_notify_entry(Aml
*method
, int slot
)
357 int32_t devfn
= PCI_DEVFN(slot
, 0);
359 if_ctx
= aml_if(aml_and(aml_arg(0), aml_int(0x1U
<< slot
), NULL
));
360 aml_append(if_ctx
, aml_notify(aml_name("S%.02X", devfn
), aml_arg(1)));
361 aml_append(method
, if_ctx
);
364 static void build_append_pci_bus_devices(Aml
*parent_scope
, PCIBus
*bus
,
365 bool pcihp_bridge_en
)
367 Aml
*dev
, *notify_method
= NULL
, *method
;
372 bsel
= object_property_get_qobject(OBJECT(bus
), ACPI_PCIHP_PROP_BSEL
, NULL
);
374 uint64_t bsel_val
= qnum_get_uint(qobject_to(QNum
, bsel
));
376 aml_append(parent_scope
, aml_name_decl("BSEL", aml_int(bsel_val
)));
377 notify_method
= aml_method("DVNT", 2, AML_NOTSERIALIZED
);
380 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); i
+= PCI_FUNC_MAX
) {
383 PCIDevice
*pdev
= bus
->devices
[i
];
384 int slot
= PCI_SLOT(i
);
385 bool hotplug_enabled_dev
;
387 bool cold_plugged_bridge
;
390 if (bsel
) { /* add hotplug slots for non present devices */
391 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
392 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
393 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
394 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
396 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
398 aml_append(dev
, method
);
399 method
= aml_method("_DSM", 4, AML_SERIALIZED
);
401 aml_return(aml_call6("PDSM", aml_arg(0), aml_arg(1),
402 aml_arg(2), aml_arg(3),
403 aml_name("BSEL"), aml_name("_SUN")))
405 aml_append(dev
, method
);
406 aml_append(parent_scope
, dev
);
408 build_append_pcihp_notify_entry(notify_method
, slot
);
413 pc
= PCI_DEVICE_GET_CLASS(pdev
);
414 dc
= DEVICE_GET_CLASS(pdev
);
417 * Cold plugged bridges aren't themselves hot-pluggable.
418 * Hotplugged bridges *are* hot-pluggable.
420 cold_plugged_bridge
= pc
->is_bridge
&& !DEVICE(pdev
)->hotplugged
;
421 bridge_in_acpi
= cold_plugged_bridge
&& pcihp_bridge_en
;
423 hotplug_enabled_dev
= bsel
&& dc
->hotpluggable
&& !cold_plugged_bridge
;
425 if (pc
->class_id
== PCI_CLASS_BRIDGE_ISA
) {
429 /* start to compose PCI slot descriptor */
430 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
431 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
434 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
435 method
= aml_method("_DSM", 4, AML_SERIALIZED
);
436 aml_append(method
, aml_return(
437 aml_call6("PDSM", aml_arg(0), aml_arg(1), aml_arg(2),
438 aml_arg(3), aml_name("BSEL"), aml_name("_SUN"))
440 aml_append(dev
, method
);
443 if (pc
->class_id
== PCI_CLASS_DISPLAY_VGA
) {
444 /* add VGA specific AML methods */
447 if (object_dynamic_cast(OBJECT(pdev
), "qxl-vga")) {
453 method
= aml_method("_S1D", 0, AML_NOTSERIALIZED
);
454 aml_append(method
, aml_return(aml_int(0)));
455 aml_append(dev
, method
);
457 method
= aml_method("_S2D", 0, AML_NOTSERIALIZED
);
458 aml_append(method
, aml_return(aml_int(0)));
459 aml_append(dev
, method
);
461 method
= aml_method("_S3D", 0, AML_NOTSERIALIZED
);
462 aml_append(method
, aml_return(aml_int(s3d
)));
463 aml_append(dev
, method
);
464 } else if (hotplug_enabled_dev
) {
465 /* add _EJ0 to make slot hotpluggable */
466 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
468 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
470 aml_append(dev
, method
);
473 build_append_pcihp_notify_entry(notify_method
, slot
);
475 } else if (bridge_in_acpi
) {
477 * device is coldplugged bridge,
478 * add child device descriptions into its scope
480 PCIBus
*sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(pdev
));
482 build_append_pci_bus_devices(dev
, sec_bus
, pcihp_bridge_en
);
484 /* slot descriptor has been composed, add it into parent context */
485 aml_append(parent_scope
, dev
);
489 aml_append(parent_scope
, notify_method
);
492 /* Append PCNT method to notify about events on local and child buses.
493 * Add this method for root bus only when hotplug is enabled since DSDT
496 if (bsel
|| pcihp_bridge_en
) {
497 method
= aml_method("PCNT", 0, AML_NOTSERIALIZED
);
499 /* If bus supports hotplug select it and notify about local events */
501 uint64_t bsel_val
= qnum_get_uint(qobject_to(QNum
, bsel
));
503 aml_append(method
, aml_store(aml_int(bsel_val
), aml_name("BNUM")));
504 aml_append(method
, aml_call2("DVNT", aml_name("PCIU"),
505 aml_int(1))); /* Device Check */
506 aml_append(method
, aml_call2("DVNT", aml_name("PCID"),
507 aml_int(3))); /* Eject Request */
510 /* Notify about child bus events in any case */
511 if (pcihp_bridge_en
) {
512 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
513 int32_t devfn
= sec
->parent_dev
->devfn
;
515 if (pci_bus_is_root(sec
) || pci_bus_is_express(sec
)) {
519 aml_append(method
, aml_name("^S%.02X.PCNT", devfn
));
523 aml_append(parent_scope
, method
);
528 Aml
*aml_pci_device_dsm(void)
530 Aml
*method
, *UUID
, *ifctx
, *ifctx1
, *ifctx2
, *ifctx3
, *elsectx
;
531 Aml
*acpi_index
= aml_local(0);
532 Aml
*zero
= aml_int(0);
533 Aml
*bnum
= aml_arg(4);
534 Aml
*func
= aml_arg(2);
535 Aml
*rev
= aml_arg(1);
536 Aml
*sun
= aml_arg(5);
538 method
= aml_method("PDSM", 6, AML_SERIALIZED
);
541 * PCI Firmware Specification 3.1
542 * 4.6. _DSM Definitions for PCI
544 UUID
= aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
545 ifctx
= aml_if(aml_equal(aml_arg(0), UUID
));
547 aml_append(ifctx
, aml_store(aml_call2("AIDX", bnum
, sun
), acpi_index
));
548 ifctx1
= aml_if(aml_equal(func
, zero
));
550 uint8_t byte_list
[1];
552 ifctx2
= aml_if(aml_equal(rev
, aml_int(2)));
555 * advertise function 7 if device has acpi-index
557 * 0: not present (default value)
558 * FFFFFFFF: not supported (old QEMU without PIDX reg)
559 * other: device's acpi-index
561 ifctx3
= aml_if(aml_lnot(
562 aml_or(aml_equal(acpi_index
, zero
),
563 aml_equal(acpi_index
, aml_int(0xFFFFFFFF)), NULL
)
567 1 /* have supported functions */ |
568 1 << 7 /* support for function 7 */
570 aml_append(ifctx3
, aml_return(aml_buffer(1, byte_list
)));
572 aml_append(ifctx2
, ifctx3
);
574 aml_append(ifctx1
, ifctx2
);
576 byte_list
[0] = 0; /* nothing supported */
577 aml_append(ifctx1
, aml_return(aml_buffer(1, byte_list
)));
579 aml_append(ifctx
, ifctx1
);
580 elsectx
= aml_else();
582 * PCI Firmware Specification 3.1
583 * 4.6.7. _DSM for Naming a PCI or PCI Express Device Under
586 ifctx1
= aml_if(aml_equal(func
, aml_int(7)));
588 Aml
*pkg
= aml_package(2);
589 Aml
*ret
= aml_local(1);
591 aml_append(pkg
, zero
);
593 * optional, if not impl. should return null string
595 aml_append(pkg
, aml_string("%s", ""));
596 aml_append(ifctx1
, aml_store(pkg
, ret
));
598 * update acpi-index to actual value
600 aml_append(ifctx1
, aml_store(acpi_index
, aml_index(ret
, zero
)));
601 aml_append(ifctx1
, aml_return(ret
));
603 aml_append(elsectx
, ifctx1
);
604 aml_append(ifctx
, elsectx
);
606 aml_append(method
, ifctx
);
612 * @link_name: link name for PCI route entry
614 * build AML package containing a PCI route entry for @link_name
616 static Aml
*build_prt_entry(const char *link_name
)
618 Aml
*a_zero
= aml_int(0);
619 Aml
*pkg
= aml_package(4);
620 aml_append(pkg
, a_zero
);
621 aml_append(pkg
, a_zero
);
622 aml_append(pkg
, aml_name("%s", link_name
));
623 aml_append(pkg
, a_zero
);
628 * initialize_route - Initialize the interrupt routing rule
629 * through a specific LINK:
630 * if (lnk_idx == idx)
631 * route using link 'link_name'
633 static Aml
*initialize_route(Aml
*route
, const char *link_name
,
634 Aml
*lnk_idx
, int idx
)
636 Aml
*if_ctx
= aml_if(aml_equal(lnk_idx
, aml_int(idx
)));
637 Aml
*pkg
= build_prt_entry(link_name
);
639 aml_append(if_ctx
, aml_store(pkg
, route
));
645 * build_prt - Define interrupt rounting rules
647 * Returns an array of 128 routes, one for each device,
648 * based on device location.
649 * The main goal is to equaly distribute the interrupts
650 * over the 4 existing ACPI links (works only for i440fx).
651 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
654 static Aml
*build_prt(bool is_pci0_prt
)
656 Aml
*method
, *while_ctx
, *pin
, *res
;
658 method
= aml_method("_PRT", 0, AML_NOTSERIALIZED
);
661 aml_append(method
, aml_store(aml_package(128), res
));
662 aml_append(method
, aml_store(aml_int(0), pin
));
664 /* while (pin < 128) */
665 while_ctx
= aml_while(aml_lless(pin
, aml_int(128)));
667 Aml
*slot
= aml_local(2);
668 Aml
*lnk_idx
= aml_local(3);
669 Aml
*route
= aml_local(4);
671 /* slot = pin >> 2 */
672 aml_append(while_ctx
,
673 aml_store(aml_shiftright(pin
, aml_int(2), NULL
), slot
));
674 /* lnk_idx = (slot + pin) & 3 */
675 aml_append(while_ctx
,
676 aml_store(aml_and(aml_add(pin
, slot
, NULL
), aml_int(3), NULL
),
679 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
680 aml_append(while_ctx
, initialize_route(route
, "LNKD", lnk_idx
, 0));
682 Aml
*if_device_1
, *if_pin_4
, *else_pin_4
;
684 /* device 1 is the power-management device, needs SCI */
685 if_device_1
= aml_if(aml_equal(lnk_idx
, aml_int(1)));
687 if_pin_4
= aml_if(aml_equal(pin
, aml_int(4)));
690 aml_store(build_prt_entry("LNKS"), route
));
692 aml_append(if_device_1
, if_pin_4
);
693 else_pin_4
= aml_else();
695 aml_append(else_pin_4
,
696 aml_store(build_prt_entry("LNKA"), route
));
698 aml_append(if_device_1
, else_pin_4
);
700 aml_append(while_ctx
, if_device_1
);
702 aml_append(while_ctx
, initialize_route(route
, "LNKA", lnk_idx
, 1));
704 aml_append(while_ctx
, initialize_route(route
, "LNKB", lnk_idx
, 2));
705 aml_append(while_ctx
, initialize_route(route
, "LNKC", lnk_idx
, 3));
707 /* route[0] = 0x[slot]FFFF */
708 aml_append(while_ctx
,
709 aml_store(aml_or(aml_shiftleft(slot
, aml_int(16)), aml_int(0xFFFF),
711 aml_index(route
, aml_int(0))));
712 /* route[1] = pin & 3 */
713 aml_append(while_ctx
,
714 aml_store(aml_and(pin
, aml_int(3), NULL
),
715 aml_index(route
, aml_int(1))));
716 /* res[pin] = route */
717 aml_append(while_ctx
, aml_store(route
, aml_index(res
, pin
)));
719 aml_append(while_ctx
, aml_increment(pin
));
721 aml_append(method
, while_ctx
);
723 aml_append(method
, aml_return(res
));
728 static void build_hpet_aml(Aml
*table
)
734 Aml
*scope
= aml_scope("_SB");
735 Aml
*dev
= aml_device("HPET");
736 Aml
*zero
= aml_int(0);
737 Aml
*id
= aml_local(0);
738 Aml
*period
= aml_local(1);
740 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0103")));
741 aml_append(dev
, aml_name_decl("_UID", zero
));
744 aml_operation_region("HPTM", AML_SYSTEM_MEMORY
, aml_int(HPET_BASE
),
746 field
= aml_field("HPTM", AML_DWORD_ACC
, AML_LOCK
, AML_PRESERVE
);
747 aml_append(field
, aml_named_field("VEND", 32));
748 aml_append(field
, aml_named_field("PRD", 32));
749 aml_append(dev
, field
);
751 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
752 aml_append(method
, aml_store(aml_name("VEND"), id
));
753 aml_append(method
, aml_store(aml_name("PRD"), period
));
754 aml_append(method
, aml_shiftright(id
, aml_int(16), id
));
755 if_ctx
= aml_if(aml_lor(aml_equal(id
, zero
),
756 aml_equal(id
, aml_int(0xffff))));
758 aml_append(if_ctx
, aml_return(zero
));
760 aml_append(method
, if_ctx
);
762 if_ctx
= aml_if(aml_lor(aml_equal(period
, zero
),
763 aml_lgreater(period
, aml_int(100000000))));
765 aml_append(if_ctx
, aml_return(zero
));
767 aml_append(method
, if_ctx
);
769 aml_append(method
, aml_return(aml_int(0x0F)));
770 aml_append(dev
, method
);
772 crs
= aml_resource_template();
773 aml_append(crs
, aml_memory32_fixed(HPET_BASE
, HPET_LEN
, AML_READ_ONLY
));
774 aml_append(dev
, aml_name_decl("_CRS", crs
));
776 aml_append(scope
, dev
);
777 aml_append(table
, scope
);
780 static Aml
*build_vmbus_device_aml(VMBusBridge
*vmbus_bridge
)
786 dev
= aml_device("VMBS");
787 aml_append(dev
, aml_name_decl("STA", aml_int(0xF)));
788 aml_append(dev
, aml_name_decl("_HID", aml_string("VMBus")));
789 aml_append(dev
, aml_name_decl("_UID", aml_int(0x0)));
790 aml_append(dev
, aml_name_decl("_DDN", aml_string("VMBUS")));
792 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
793 aml_append(method
, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL
),
795 aml_append(dev
, method
);
797 method
= aml_method("_PS0", 0, AML_NOTSERIALIZED
);
798 aml_append(method
, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL
),
800 aml_append(dev
, method
);
802 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
803 aml_append(method
, aml_return(aml_name("STA")));
804 aml_append(dev
, method
);
806 aml_append(dev
, aml_name_decl("_PS3", aml_int(0x0)));
808 crs
= aml_resource_template();
809 aml_append(crs
, aml_irq_no_flags(vmbus_bridge
->irq
));
810 aml_append(dev
, aml_name_decl("_CRS", crs
));
815 static void build_isa_devices_aml(Aml
*table
)
818 Object
*obj
= object_resolve_path_type("", TYPE_ISA_BUS
, &ambiguous
);
821 assert(obj
&& !ambiguous
);
823 scope
= aml_scope("_SB.PCI0.ISA");
824 build_acpi_ipmi_devices(scope
, BUS(obj
), "\\_SB.PCI0.ISA");
825 isa_build_aml(ISA_BUS(obj
), scope
);
827 aml_append(table
, scope
);
830 static void build_dbg_aml(Aml
*table
)
835 Aml
*scope
= aml_scope("\\");
836 Aml
*buf
= aml_local(0);
837 Aml
*len
= aml_local(1);
838 Aml
*idx
= aml_local(2);
841 aml_operation_region("DBG", AML_SYSTEM_IO
, aml_int(0x0402), 0x01));
842 field
= aml_field("DBG", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
843 aml_append(field
, aml_named_field("DBGB", 8));
844 aml_append(scope
, field
);
846 method
= aml_method("DBUG", 1, AML_NOTSERIALIZED
);
848 aml_append(method
, aml_to_hexstring(aml_arg(0), buf
));
849 aml_append(method
, aml_to_buffer(buf
, buf
));
850 aml_append(method
, aml_subtract(aml_sizeof(buf
), aml_int(1), len
));
851 aml_append(method
, aml_store(aml_int(0), idx
));
853 while_ctx
= aml_while(aml_lless(idx
, len
));
854 aml_append(while_ctx
,
855 aml_store(aml_derefof(aml_index(buf
, idx
)), aml_name("DBGB")));
856 aml_append(while_ctx
, aml_increment(idx
));
857 aml_append(method
, while_ctx
);
859 aml_append(method
, aml_store(aml_int(0x0A), aml_name("DBGB")));
860 aml_append(scope
, method
);
862 aml_append(table
, scope
);
865 static Aml
*build_link_dev(const char *name
, uint8_t uid
, Aml
*reg
)
870 uint32_t irqs
[] = {5, 10, 11};
872 dev
= aml_device("%s", name
);
873 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
874 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
876 crs
= aml_resource_template();
877 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
878 AML_SHARED
, irqs
, ARRAY_SIZE(irqs
)));
879 aml_append(dev
, aml_name_decl("_PRS", crs
));
881 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
882 aml_append(method
, aml_return(aml_call1("IQST", reg
)));
883 aml_append(dev
, method
);
885 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
886 aml_append(method
, aml_or(reg
, aml_int(0x80), reg
));
887 aml_append(dev
, method
);
889 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
890 aml_append(method
, aml_return(aml_call1("IQCR", reg
)));
891 aml_append(dev
, method
);
893 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
894 aml_append(method
, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
895 aml_append(method
, aml_store(aml_name("PRRI"), reg
));
896 aml_append(dev
, method
);
901 static Aml
*build_gsi_link_dev(const char *name
, uint8_t uid
, uint8_t gsi
)
908 dev
= aml_device("%s", name
);
909 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
910 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
912 crs
= aml_resource_template();
914 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
915 AML_SHARED
, &irqs
, 1));
916 aml_append(dev
, aml_name_decl("_PRS", crs
));
918 aml_append(dev
, aml_name_decl("_CRS", crs
));
921 * _DIS can be no-op because the interrupt cannot be disabled.
923 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
924 aml_append(dev
, method
);
926 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
927 aml_append(dev
, method
);
932 /* _CRS method - get current settings */
933 static Aml
*build_iqcr_method(bool is_piix4
)
937 Aml
*method
= aml_method("IQCR", 1, AML_SERIALIZED
);
938 Aml
*crs
= aml_resource_template();
941 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
,
942 AML_ACTIVE_HIGH
, AML_SHARED
, &irqs
, 1));
943 aml_append(method
, aml_name_decl("PRR0", crs
));
946 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
949 if_ctx
= aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
950 aml_append(if_ctx
, aml_store(aml_arg(0), aml_name("PRRI")));
951 aml_append(method
, if_ctx
);
954 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL
),
958 aml_append(method
, aml_return(aml_name("PRR0")));
962 /* _STA method - get status */
963 static Aml
*build_irq_status_method(void)
966 Aml
*method
= aml_method("IQST", 1, AML_NOTSERIALIZED
);
968 if_ctx
= aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL
));
969 aml_append(if_ctx
, aml_return(aml_int(0x09)));
970 aml_append(method
, if_ctx
);
971 aml_append(method
, aml_return(aml_int(0x0B)));
975 static void build_piix4_pci0_int(Aml
*table
)
982 Aml
*sb_scope
= aml_scope("_SB");
983 Aml
*pci0_scope
= aml_scope("PCI0");
985 aml_append(pci0_scope
, build_prt(true));
986 aml_append(sb_scope
, pci0_scope
);
988 field
= aml_field("PCI0.ISA.P40C", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
989 aml_append(field
, aml_named_field("PRQ0", 8));
990 aml_append(field
, aml_named_field("PRQ1", 8));
991 aml_append(field
, aml_named_field("PRQ2", 8));
992 aml_append(field
, aml_named_field("PRQ3", 8));
993 aml_append(sb_scope
, field
);
995 aml_append(sb_scope
, build_irq_status_method());
996 aml_append(sb_scope
, build_iqcr_method(true));
998 aml_append(sb_scope
, build_link_dev("LNKA", 0, aml_name("PRQ0")));
999 aml_append(sb_scope
, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1000 aml_append(sb_scope
, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1001 aml_append(sb_scope
, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1003 dev
= aml_device("LNKS");
1005 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1006 aml_append(dev
, aml_name_decl("_UID", aml_int(4)));
1008 crs
= aml_resource_template();
1010 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
,
1011 AML_ACTIVE_HIGH
, AML_SHARED
,
1013 aml_append(dev
, aml_name_decl("_PRS", crs
));
1015 /* The SCI cannot be disabled and is always attached to GSI 9,
1016 * so these are no-ops. We only need this link to override the
1017 * polarity to active high and match the content of the MADT.
1019 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1020 aml_append(method
, aml_return(aml_int(0x0b)));
1021 aml_append(dev
, method
);
1023 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1024 aml_append(dev
, method
);
1026 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1027 aml_append(method
, aml_return(aml_name("_PRS")));
1028 aml_append(dev
, method
);
1030 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1031 aml_append(dev
, method
);
1033 aml_append(sb_scope
, dev
);
1035 aml_append(table
, sb_scope
);
1038 static void append_q35_prt_entry(Aml
*ctx
, uint32_t nr
, const char *name
)
1043 char base
= name
[3] < 'E' ? 'A' : 'E';
1044 char *s
= g_strdup(name
);
1045 Aml
*a_nr
= aml_int((nr
<< 16) | 0xffff);
1047 assert(strlen(s
) == 4);
1049 head
= name
[3] - base
;
1050 for (i
= 0; i
< 4; i
++) {
1054 s
[3] = base
+ head
+ i
;
1055 pkg
= aml_package(4);
1056 aml_append(pkg
, a_nr
);
1057 aml_append(pkg
, aml_int(i
));
1058 aml_append(pkg
, aml_name("%s", s
));
1059 aml_append(pkg
, aml_int(0));
1060 aml_append(ctx
, pkg
);
1065 static Aml
*build_q35_routing_table(const char *str
)
1069 char *name
= g_strdup_printf("%s ", str
);
1071 pkg
= aml_package(128);
1072 for (i
= 0; i
< 0x18; i
++) {
1073 name
[3] = 'E' + (i
& 0x3);
1074 append_q35_prt_entry(pkg
, i
, name
);
1078 append_q35_prt_entry(pkg
, 0x18, name
);
1080 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1081 for (i
= 0x0019; i
< 0x1e; i
++) {
1083 append_q35_prt_entry(pkg
, i
, name
);
1086 /* PCIe->PCI bridge. use PIRQ[E-H] */
1088 append_q35_prt_entry(pkg
, 0x1e, name
);
1090 append_q35_prt_entry(pkg
, 0x1f, name
);
1096 static void build_q35_pci0_int(Aml
*table
)
1100 Aml
*sb_scope
= aml_scope("_SB");
1101 Aml
*pci0_scope
= aml_scope("PCI0");
1103 /* Zero => PIC mode, One => APIC Mode */
1104 aml_append(table
, aml_name_decl("PICF", aml_int(0)));
1105 method
= aml_method("_PIC", 1, AML_NOTSERIALIZED
);
1107 aml_append(method
, aml_store(aml_arg(0), aml_name("PICF")));
1109 aml_append(table
, method
);
1111 aml_append(pci0_scope
,
1112 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1113 aml_append(pci0_scope
,
1114 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1116 method
= aml_method("_PRT", 0, AML_NOTSERIALIZED
);
1121 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1123 /* Note: we provide the same info as the PCI routing
1124 table of the Bochs BIOS */
1125 if_ctx
= aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1126 aml_append(if_ctx
, aml_return(aml_name("PRTP")));
1127 aml_append(method
, if_ctx
);
1128 else_ctx
= aml_else();
1129 aml_append(else_ctx
, aml_return(aml_name("PRTA")));
1130 aml_append(method
, else_ctx
);
1132 aml_append(pci0_scope
, method
);
1133 aml_append(sb_scope
, pci0_scope
);
1135 field
= aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1136 aml_append(field
, aml_named_field("PRQA", 8));
1137 aml_append(field
, aml_named_field("PRQB", 8));
1138 aml_append(field
, aml_named_field("PRQC", 8));
1139 aml_append(field
, aml_named_field("PRQD", 8));
1140 aml_append(field
, aml_reserved_field(0x20));
1141 aml_append(field
, aml_named_field("PRQE", 8));
1142 aml_append(field
, aml_named_field("PRQF", 8));
1143 aml_append(field
, aml_named_field("PRQG", 8));
1144 aml_append(field
, aml_named_field("PRQH", 8));
1145 aml_append(sb_scope
, field
);
1147 aml_append(sb_scope
, build_irq_status_method());
1148 aml_append(sb_scope
, build_iqcr_method(false));
1150 aml_append(sb_scope
, build_link_dev("LNKA", 0, aml_name("PRQA")));
1151 aml_append(sb_scope
, build_link_dev("LNKB", 1, aml_name("PRQB")));
1152 aml_append(sb_scope
, build_link_dev("LNKC", 2, aml_name("PRQC")));
1153 aml_append(sb_scope
, build_link_dev("LNKD", 3, aml_name("PRQD")));
1154 aml_append(sb_scope
, build_link_dev("LNKE", 4, aml_name("PRQE")));
1155 aml_append(sb_scope
, build_link_dev("LNKF", 5, aml_name("PRQF")));
1156 aml_append(sb_scope
, build_link_dev("LNKG", 6, aml_name("PRQG")));
1157 aml_append(sb_scope
, build_link_dev("LNKH", 7, aml_name("PRQH")));
1159 aml_append(sb_scope
, build_gsi_link_dev("GSIA", 0x10, 0x10));
1160 aml_append(sb_scope
, build_gsi_link_dev("GSIB", 0x11, 0x11));
1161 aml_append(sb_scope
, build_gsi_link_dev("GSIC", 0x12, 0x12));
1162 aml_append(sb_scope
, build_gsi_link_dev("GSID", 0x13, 0x13));
1163 aml_append(sb_scope
, build_gsi_link_dev("GSIE", 0x14, 0x14));
1164 aml_append(sb_scope
, build_gsi_link_dev("GSIF", 0x15, 0x15));
1165 aml_append(sb_scope
, build_gsi_link_dev("GSIG", 0x16, 0x16));
1166 aml_append(sb_scope
, build_gsi_link_dev("GSIH", 0x17, 0x17));
1168 aml_append(table
, sb_scope
);
1171 static Aml
*build_q35_dram_controller(const AcpiMcfgInfo
*mcfg
)
1174 Aml
*resource_template
;
1176 /* DRAM controller */
1177 dev
= aml_device("DRAC");
1178 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0C01")));
1180 resource_template
= aml_resource_template();
1181 if (mcfg
->base
+ mcfg
->size
- 1 >= (1ULL << 32)) {
1182 aml_append(resource_template
,
1183 aml_qword_memory(AML_POS_DECODE
,
1190 mcfg
->base
+ mcfg
->size
- 1,
1194 aml_append(resource_template
,
1195 aml_dword_memory(AML_POS_DECODE
,
1202 mcfg
->base
+ mcfg
->size
- 1,
1206 aml_append(dev
, aml_name_decl("_CRS", resource_template
));
1211 static void build_q35_isa_bridge(Aml
*table
)
1216 scope
= aml_scope("_SB.PCI0");
1217 dev
= aml_device("ISA");
1218 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x001F0000)));
1220 /* ICH9 PCI to ISA irq remapping */
1221 aml_append(dev
, aml_operation_region("PIRQ", AML_PCI_CONFIG
,
1222 aml_int(0x60), 0x0C));
1224 aml_append(scope
, dev
);
1225 aml_append(table
, scope
);
1228 static void build_piix4_isa_bridge(Aml
*table
)
1233 scope
= aml_scope("_SB.PCI0");
1234 dev
= aml_device("ISA");
1235 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x00010000)));
1237 /* PIIX PCI to ISA irq remapping */
1238 aml_append(dev
, aml_operation_region("P40C", AML_PCI_CONFIG
,
1239 aml_int(0x60), 0x04));
1241 aml_append(scope
, dev
);
1242 aml_append(table
, scope
);
1245 static void build_piix4_pci_hotplug(Aml
*table
)
1251 scope
= aml_scope("_SB.PCI0");
1254 aml_operation_region("PCST", AML_SYSTEM_IO
, aml_int(0xae00), 0x08));
1255 field
= aml_field("PCST", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1256 aml_append(field
, aml_named_field("PCIU", 32));
1257 aml_append(field
, aml_named_field("PCID", 32));
1258 aml_append(scope
, field
);
1261 aml_operation_region("SEJ", AML_SYSTEM_IO
, aml_int(0xae08), 0x04));
1262 field
= aml_field("SEJ", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1263 aml_append(field
, aml_named_field("B0EJ", 32));
1264 aml_append(scope
, field
);
1267 aml_operation_region("BNMR", AML_SYSTEM_IO
, aml_int(0xae10), 0x08));
1268 field
= aml_field("BNMR", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1269 aml_append(field
, aml_named_field("BNUM", 32));
1270 aml_append(field
, aml_named_field("PIDX", 32));
1271 aml_append(scope
, field
);
1273 aml_append(scope
, aml_mutex("BLCK", 0));
1275 method
= aml_method("PCEJ", 2, AML_NOTSERIALIZED
);
1276 aml_append(method
, aml_acquire(aml_name("BLCK"), 0xFFFF));
1277 aml_append(method
, aml_store(aml_arg(0), aml_name("BNUM")));
1279 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1280 aml_append(method
, aml_release(aml_name("BLCK")));
1281 aml_append(method
, aml_return(aml_int(0)));
1282 aml_append(scope
, method
);
1284 method
= aml_method("AIDX", 2, AML_NOTSERIALIZED
);
1285 aml_append(method
, aml_acquire(aml_name("BLCK"), 0xFFFF));
1286 aml_append(method
, aml_store(aml_arg(0), aml_name("BNUM")));
1288 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("PIDX")));
1289 aml_append(method
, aml_store(aml_name("PIDX"), aml_local(0)));
1290 aml_append(method
, aml_release(aml_name("BLCK")));
1291 aml_append(method
, aml_return(aml_local(0)));
1292 aml_append(scope
, method
);
1294 aml_append(scope
, aml_pci_device_dsm());
1296 aml_append(table
, scope
);
1299 static Aml
*build_q35_osc_method(void)
1305 Aml
*a_cwd1
= aml_name("CDW1");
1306 Aml
*a_ctrl
= aml_local(0);
1308 method
= aml_method("_OSC", 4, AML_NOTSERIALIZED
);
1309 aml_append(method
, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1311 if_ctx
= aml_if(aml_equal(
1312 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1313 aml_append(if_ctx
, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1314 aml_append(if_ctx
, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1316 aml_append(if_ctx
, aml_store(aml_name("CDW3"), a_ctrl
));
1319 * Always allow native PME, AER (no dependencies)
1320 * Allow SHPC (PCI bridges can have SHPC controller)
1322 aml_append(if_ctx
, aml_and(a_ctrl
, aml_int(0x1F), a_ctrl
));
1324 if_ctx2
= aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1325 /* Unknown revision */
1326 aml_append(if_ctx2
, aml_or(a_cwd1
, aml_int(0x08), a_cwd1
));
1327 aml_append(if_ctx
, if_ctx2
);
1329 if_ctx2
= aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl
)));
1330 /* Capabilities bits were masked */
1331 aml_append(if_ctx2
, aml_or(a_cwd1
, aml_int(0x10), a_cwd1
));
1332 aml_append(if_ctx
, if_ctx2
);
1334 /* Update DWORD3 in the buffer */
1335 aml_append(if_ctx
, aml_store(a_ctrl
, aml_name("CDW3")));
1336 aml_append(method
, if_ctx
);
1338 else_ctx
= aml_else();
1339 /* Unrecognized UUID */
1340 aml_append(else_ctx
, aml_or(a_cwd1
, aml_int(4), a_cwd1
));
1341 aml_append(method
, else_ctx
);
1343 aml_append(method
, aml_return(aml_arg(3)));
1347 static void build_smb0(Aml
*table
, I2CBus
*smbus
, int devnr
, int func
)
1349 Aml
*scope
= aml_scope("_SB.PCI0");
1350 Aml
*dev
= aml_device("SMB0");
1352 aml_append(dev
, aml_name_decl("_ADR", aml_int(devnr
<< 16 | func
)));
1353 build_acpi_ipmi_devices(dev
, BUS(smbus
), "\\_SB.PCI0.SMB0");
1354 aml_append(scope
, dev
);
1355 aml_append(table
, scope
);
1359 build_dsdt(GArray
*table_data
, BIOSLinker
*linker
,
1360 AcpiPmInfo
*pm
, AcpiMiscInfo
*misc
,
1361 Range
*pci_hole
, Range
*pci_hole64
, MachineState
*machine
)
1363 CrsRangeEntry
*entry
;
1364 Aml
*dsdt
, *sb_scope
, *scope
, *dev
, *method
, *field
, *pkg
, *crs
;
1365 CrsRangeSet crs_range_set
;
1366 PCMachineState
*pcms
= PC_MACHINE(machine
);
1367 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(machine
);
1368 X86MachineState
*x86ms
= X86_MACHINE(machine
);
1370 bool mcfg_valid
= !!acpi_get_mcfg(&mcfg
);
1371 uint32_t nr_mem
= machine
->ram_slots
;
1372 int root_bus_limit
= 0xFF;
1374 TPMIf
*tpm
= tpm_find();
1376 VMBusBridge
*vmbus_bridge
= vmbus_bridge_find();
1378 dsdt
= init_aml_allocator();
1380 /* Reserve space for header */
1381 acpi_data_push(dsdt
->buf
, sizeof(AcpiTableHeader
));
1383 build_dbg_aml(dsdt
);
1384 if (misc
->is_piix4
) {
1385 sb_scope
= aml_scope("_SB");
1386 dev
= aml_device("PCI0");
1387 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1388 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
1389 aml_append(dev
, aml_name_decl("_UID", aml_int(pcmc
->pci_root_uid
)));
1390 aml_append(sb_scope
, dev
);
1391 aml_append(dsdt
, sb_scope
);
1393 if (misc
->has_hpet
) {
1394 build_hpet_aml(dsdt
);
1396 build_piix4_isa_bridge(dsdt
);
1397 build_isa_devices_aml(dsdt
);
1398 if (pm
->pcihp_bridge_en
|| pm
->pcihp_root_en
) {
1399 build_piix4_pci_hotplug(dsdt
);
1401 build_piix4_pci0_int(dsdt
);
1403 sb_scope
= aml_scope("_SB");
1404 dev
= aml_device("PCI0");
1405 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1406 aml_append(dev
, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1407 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
1408 aml_append(dev
, aml_name_decl("_UID", aml_int(pcmc
->pci_root_uid
)));
1409 aml_append(dev
, build_q35_osc_method());
1410 aml_append(sb_scope
, dev
);
1412 aml_append(sb_scope
, build_q35_dram_controller(&mcfg
));
1415 if (pm
->smi_on_cpuhp
) {
1416 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */
1417 dev
= aml_device("PCI0.SMI0");
1418 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
1419 aml_append(dev
, aml_name_decl("_UID", aml_string("SMI resources")));
1420 crs
= aml_resource_template();
1429 aml_append(dev
, aml_name_decl("_CRS", crs
));
1430 aml_append(dev
, aml_operation_region("SMIR", AML_SYSTEM_IO
,
1431 aml_int(ACPI_PORT_SMI_CMD
), 2));
1432 field
= aml_field("SMIR", AML_BYTE_ACC
, AML_NOLOCK
,
1433 AML_WRITE_AS_ZEROS
);
1434 aml_append(field
, aml_named_field("SMIC", 8));
1435 aml_append(field
, aml_reserved_field(8));
1436 aml_append(dev
, field
);
1437 aml_append(sb_scope
, dev
);
1440 aml_append(dsdt
, sb_scope
);
1442 if (misc
->has_hpet
) {
1443 build_hpet_aml(dsdt
);
1445 build_q35_isa_bridge(dsdt
);
1446 build_isa_devices_aml(dsdt
);
1447 build_q35_pci0_int(dsdt
);
1448 if (pcms
->smbus
&& !pcmc
->do_not_add_smb_acpi
) {
1449 build_smb0(dsdt
, pcms
->smbus
, ICH9_SMB_DEV
, ICH9_SMB_FUNC
);
1454 sb_scope
= aml_scope("_SB");
1455 aml_append(sb_scope
, build_vmbus_device_aml(vmbus_bridge
));
1456 aml_append(dsdt
, sb_scope
);
1459 if (pcmc
->legacy_cpu_hotplug
) {
1460 build_legacy_cpu_hotplug_aml(dsdt
, machine
, pm
->cpu_hp_io_base
);
1462 CPUHotplugFeatures opts
= {
1463 .acpi_1_compatible
= true, .has_legacy_cphp
= true,
1464 .smi_path
= pm
->smi_on_cpuhp
? "\\_SB.PCI0.SMI0.SMIC" : NULL
,
1465 .fw_unplugs_cpu
= pm
->smi_on_cpu_unplug
,
1467 build_cpus_aml(dsdt
, machine
, opts
, pm
->cpu_hp_io_base
,
1468 "\\_SB.PCI0", "\\_GPE._E02");
1471 if (pcms
->memhp_io_base
&& nr_mem
) {
1472 build_memory_hotplug_aml(dsdt
, nr_mem
, "\\_SB.PCI0",
1473 "\\_GPE._E03", AML_SYSTEM_IO
,
1474 pcms
->memhp_io_base
);
1477 scope
= aml_scope("_GPE");
1479 aml_append(scope
, aml_name_decl("_HID", aml_string("ACPI0006")));
1481 if (misc
->is_piix4
&& (pm
->pcihp_bridge_en
|| pm
->pcihp_root_en
)) {
1482 method
= aml_method("_E01", 0, AML_NOTSERIALIZED
);
1484 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1485 aml_append(method
, aml_call0("\\_SB.PCI0.PCNT"));
1486 aml_append(method
, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1487 aml_append(scope
, method
);
1490 if (machine
->nvdimms_state
->is_enabled
) {
1491 method
= aml_method("_E04", 0, AML_NOTSERIALIZED
);
1492 aml_append(method
, aml_notify(aml_name("\\_SB.NVDR"),
1494 aml_append(scope
, method
);
1497 aml_append(dsdt
, scope
);
1499 crs_range_set_init(&crs_range_set
);
1500 bus
= PC_MACHINE(machine
)->bus
;
1502 QLIST_FOREACH(bus
, &bus
->child
, sibling
) {
1503 uint8_t bus_num
= pci_bus_num(bus
);
1504 uint8_t numa_node
= pci_bus_numa_node(bus
);
1506 /* look only for expander root buses */
1507 if (!pci_bus_is_root(bus
)) {
1511 if (bus_num
< root_bus_limit
) {
1512 root_bus_limit
= bus_num
- 1;
1515 scope
= aml_scope("\\_SB");
1516 dev
= aml_device("PC%.02X", bus_num
);
1517 aml_append(dev
, aml_name_decl("_UID", aml_int(bus_num
)));
1518 aml_append(dev
, aml_name_decl("_BBN", aml_int(bus_num
)));
1519 if (pci_bus_is_express(bus
)) {
1520 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1521 aml_append(dev
, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1522 aml_append(dev
, build_q35_osc_method());
1524 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1527 if (numa_node
!= NUMA_NODE_UNASSIGNED
) {
1528 aml_append(dev
, aml_name_decl("_PXM", aml_int(numa_node
)));
1531 aml_append(dev
, build_prt(false));
1532 crs
= build_crs(PCI_HOST_BRIDGE(BUS(bus
)->parent
), &crs_range_set
,
1534 aml_append(dev
, aml_name_decl("_CRS", crs
));
1535 aml_append(scope
, dev
);
1536 aml_append(dsdt
, scope
);
1541 * At this point crs_range_set has all the ranges used by pci
1542 * busses *other* than PCI0. These ranges will be excluded from
1543 * the PCI0._CRS. Add mmconfig to the set so it will be excluded
1547 crs_range_insert(crs_range_set
.mem_ranges
,
1548 mcfg
.base
, mcfg
.base
+ mcfg
.size
- 1);
1551 scope
= aml_scope("\\_SB.PCI0");
1552 /* build PCI0._CRS */
1553 crs
= aml_resource_template();
1555 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
1556 0x0000, 0x0, root_bus_limit
,
1557 0x0000, root_bus_limit
+ 1));
1558 aml_append(crs
, aml_io(AML_DECODE16
, 0x0CF8, 0x0CF8, 0x01, 0x08));
1561 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
1562 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
1563 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1565 crs_replace_with_free_ranges(crs_range_set
.io_ranges
, 0x0D00, 0xFFFF);
1566 for (i
= 0; i
< crs_range_set
.io_ranges
->len
; i
++) {
1567 entry
= g_ptr_array_index(crs_range_set
.io_ranges
, i
);
1569 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
1570 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
1571 0x0000, entry
->base
, entry
->limit
,
1572 0x0000, entry
->limit
- entry
->base
+ 1));
1576 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
1577 AML_CACHEABLE
, AML_READ_WRITE
,
1578 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1580 crs_replace_with_free_ranges(crs_range_set
.mem_ranges
,
1581 range_lob(pci_hole
),
1582 range_upb(pci_hole
));
1583 for (i
= 0; i
< crs_range_set
.mem_ranges
->len
; i
++) {
1584 entry
= g_ptr_array_index(crs_range_set
.mem_ranges
, i
);
1586 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
1587 AML_NON_CACHEABLE
, AML_READ_WRITE
,
1588 0, entry
->base
, entry
->limit
,
1589 0, entry
->limit
- entry
->base
+ 1));
1592 if (!range_is_empty(pci_hole64
)) {
1593 crs_replace_with_free_ranges(crs_range_set
.mem_64bit_ranges
,
1594 range_lob(pci_hole64
),
1595 range_upb(pci_hole64
));
1596 for (i
= 0; i
< crs_range_set
.mem_64bit_ranges
->len
; i
++) {
1597 entry
= g_ptr_array_index(crs_range_set
.mem_64bit_ranges
, i
);
1599 aml_qword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
1601 AML_CACHEABLE
, AML_READ_WRITE
,
1602 0, entry
->base
, entry
->limit
,
1603 0, entry
->limit
- entry
->base
+ 1));
1607 if (TPM_IS_TIS_ISA(tpm_find())) {
1608 aml_append(crs
, aml_memory32_fixed(TPM_TIS_ADDR_BASE
,
1609 TPM_TIS_ADDR_SIZE
, AML_READ_WRITE
));
1611 aml_append(scope
, aml_name_decl("_CRS", crs
));
1613 /* reserve GPE0 block resources */
1614 dev
= aml_device("GPE0");
1615 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
1616 aml_append(dev
, aml_name_decl("_UID", aml_string("GPE0 resources")));
1617 /* device present, functioning, decoding, not shown in UI */
1618 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
1619 crs
= aml_resource_template();
1623 pm
->fadt
.gpe0_blk
.address
,
1624 pm
->fadt
.gpe0_blk
.address
,
1626 pm
->fadt
.gpe0_blk
.bit_width
/ 8)
1628 aml_append(dev
, aml_name_decl("_CRS", crs
));
1629 aml_append(scope
, dev
);
1631 crs_range_set_free(&crs_range_set
);
1633 /* reserve PCIHP resources */
1634 if (pm
->pcihp_io_len
&& (pm
->pcihp_bridge_en
|| pm
->pcihp_root_en
)) {
1635 dev
= aml_device("PHPR");
1636 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
1638 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1639 /* device present, functioning, decoding, not shown in UI */
1640 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
1641 crs
= aml_resource_template();
1643 aml_io(AML_DECODE16
, pm
->pcihp_io_base
, pm
->pcihp_io_base
, 1,
1646 aml_append(dev
, aml_name_decl("_CRS", crs
));
1647 aml_append(scope
, dev
);
1649 aml_append(dsdt
, scope
);
1651 /* create S3_ / S4_ / S5_ packages if necessary */
1652 scope
= aml_scope("\\");
1653 if (!pm
->s3_disabled
) {
1654 pkg
= aml_package(4);
1655 aml_append(pkg
, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1656 aml_append(pkg
, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1657 aml_append(pkg
, aml_int(0)); /* reserved */
1658 aml_append(pkg
, aml_int(0)); /* reserved */
1659 aml_append(scope
, aml_name_decl("_S3", pkg
));
1662 if (!pm
->s4_disabled
) {
1663 pkg
= aml_package(4);
1664 aml_append(pkg
, aml_int(pm
->s4_val
)); /* PM1a_CNT.SLP_TYP */
1665 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1666 aml_append(pkg
, aml_int(pm
->s4_val
));
1667 aml_append(pkg
, aml_int(0)); /* reserved */
1668 aml_append(pkg
, aml_int(0)); /* reserved */
1669 aml_append(scope
, aml_name_decl("_S4", pkg
));
1672 pkg
= aml_package(4);
1673 aml_append(pkg
, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1674 aml_append(pkg
, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1675 aml_append(pkg
, aml_int(0)); /* reserved */
1676 aml_append(pkg
, aml_int(0)); /* reserved */
1677 aml_append(scope
, aml_name_decl("_S5", pkg
));
1678 aml_append(dsdt
, scope
);
1680 /* create fw_cfg node, unconditionally */
1682 scope
= aml_scope("\\_SB.PCI0");
1683 fw_cfg_add_acpi_dsdt(scope
, x86ms
->fw_cfg
);
1684 aml_append(dsdt
, scope
);
1687 if (misc
->applesmc_io_base
) {
1688 scope
= aml_scope("\\_SB.PCI0.ISA");
1689 dev
= aml_device("SMC");
1691 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("APP0001")));
1692 /* device present, functioning, decoding, not shown in UI */
1693 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
1695 crs
= aml_resource_template();
1697 aml_io(AML_DECODE16
, misc
->applesmc_io_base
, misc
->applesmc_io_base
,
1698 0x01, APPLESMC_MAX_DATA_LENGTH
)
1700 aml_append(crs
, aml_irq_no_flags(6));
1701 aml_append(dev
, aml_name_decl("_CRS", crs
));
1703 aml_append(scope
, dev
);
1704 aml_append(dsdt
, scope
);
1707 if (misc
->pvpanic_port
) {
1708 scope
= aml_scope("\\_SB.PCI0.ISA");
1710 dev
= aml_device("PEVT");
1711 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0001")));
1713 crs
= aml_resource_template();
1715 aml_io(AML_DECODE16
, misc
->pvpanic_port
, misc
->pvpanic_port
, 1, 1)
1717 aml_append(dev
, aml_name_decl("_CRS", crs
));
1719 aml_append(dev
, aml_operation_region("PEOR", AML_SYSTEM_IO
,
1720 aml_int(misc
->pvpanic_port
), 1));
1721 field
= aml_field("PEOR", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1722 aml_append(field
, aml_named_field("PEPT", 8));
1723 aml_append(dev
, field
);
1725 /* device present, functioning, decoding, shown in UI */
1726 aml_append(dev
, aml_name_decl("_STA", aml_int(0xF)));
1728 method
= aml_method("RDPT", 0, AML_NOTSERIALIZED
);
1729 aml_append(method
, aml_store(aml_name("PEPT"), aml_local(0)));
1730 aml_append(method
, aml_return(aml_local(0)));
1731 aml_append(dev
, method
);
1733 method
= aml_method("WRPT", 1, AML_NOTSERIALIZED
);
1734 aml_append(method
, aml_store(aml_arg(0), aml_name("PEPT")));
1735 aml_append(dev
, method
);
1737 aml_append(scope
, dev
);
1738 aml_append(dsdt
, scope
);
1741 sb_scope
= aml_scope("\\_SB");
1746 pci_host
= acpi_get_i386_pci_host();
1748 bus
= PCI_HOST_BRIDGE(pci_host
)->bus
;
1752 Aml
*scope
= aml_scope("PCI0");
1753 /* Scan all PCI buses. Generate tables to support hotplug. */
1754 build_append_pci_bus_devices(scope
, bus
, pm
->pcihp_bridge_en
);
1756 if (TPM_IS_TIS_ISA(tpm
)) {
1757 if (misc
->tpm_version
== TPM_VERSION_2_0
) {
1758 dev
= aml_device("TPM");
1759 aml_append(dev
, aml_name_decl("_HID",
1760 aml_string("MSFT0101")));
1762 dev
= aml_device("ISA.TPM");
1763 aml_append(dev
, aml_name_decl("_HID",
1764 aml_eisaid("PNP0C31")));
1767 aml_append(dev
, aml_name_decl("_STA", aml_int(0xF)));
1768 crs
= aml_resource_template();
1769 aml_append(crs
, aml_memory32_fixed(TPM_TIS_ADDR_BASE
,
1770 TPM_TIS_ADDR_SIZE
, AML_READ_WRITE
));
1772 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
1773 Rewrite to take IRQ from TPM device model and
1774 fix default IRQ value there to use some unused IRQ
1776 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
1777 aml_append(dev
, aml_name_decl("_CRS", crs
));
1779 tpm_build_ppi_acpi(tpm
, dev
);
1781 aml_append(scope
, dev
);
1784 aml_append(sb_scope
, scope
);
1788 if (TPM_IS_CRB(tpm
)) {
1789 dev
= aml_device("TPM");
1790 aml_append(dev
, aml_name_decl("_HID", aml_string("MSFT0101")));
1791 crs
= aml_resource_template();
1792 aml_append(crs
, aml_memory32_fixed(TPM_CRB_ADDR_BASE
,
1793 TPM_CRB_ADDR_SIZE
, AML_READ_WRITE
));
1794 aml_append(dev
, aml_name_decl("_CRS", crs
));
1796 aml_append(dev
, aml_name_decl("_STA", aml_int(0xf)));
1798 tpm_build_ppi_acpi(tpm
, dev
);
1800 aml_append(sb_scope
, dev
);
1803 aml_append(dsdt
, sb_scope
);
1805 /* copy AML table into ACPI tables blob and patch header there */
1806 g_array_append_vals(table_data
, dsdt
->buf
->data
, dsdt
->buf
->len
);
1807 build_header(linker
, table_data
,
1808 (void *)(table_data
->data
+ table_data
->len
- dsdt
->buf
->len
),
1809 "DSDT", dsdt
->buf
->len
, 1, x86ms
->oem_id
, x86ms
->oem_table_id
);
1810 free_aml_allocator();
1814 build_hpet(GArray
*table_data
, BIOSLinker
*linker
, const char *oem_id
,
1815 const char *oem_table_id
)
1819 hpet
= acpi_data_push(table_data
, sizeof(*hpet
));
1820 /* Note timer_block_id value must be kept in sync with value advertised by
1823 hpet
->timer_block_id
= cpu_to_le32(0x8086a201);
1824 hpet
->addr
.address
= cpu_to_le64(HPET_BASE
);
1825 build_header(linker
, table_data
,
1826 (void *)hpet
, "HPET", sizeof(*hpet
), 1, oem_id
, oem_table_id
);
1830 build_tpm_tcpa(GArray
*table_data
, BIOSLinker
*linker
, GArray
*tcpalog
,
1831 const char *oem_id
, const char *oem_table_id
)
1833 Acpi20Tcpa
*tcpa
= acpi_data_push(table_data
, sizeof *tcpa
);
1834 unsigned log_addr_size
= sizeof(tcpa
->log_area_start_address
);
1835 unsigned log_addr_offset
=
1836 (char *)&tcpa
->log_area_start_address
- table_data
->data
;
1838 tcpa
->platform_class
= cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT
);
1839 tcpa
->log_area_minimum_length
= cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE
);
1840 acpi_data_push(tcpalog
, le32_to_cpu(tcpa
->log_area_minimum_length
));
1842 bios_linker_loader_alloc(linker
, ACPI_BUILD_TPMLOG_FILE
, tcpalog
, 1,
1843 false /* high memory */);
1845 /* log area start address to be filled by Guest linker */
1846 bios_linker_loader_add_pointer(linker
,
1847 ACPI_BUILD_TABLE_FILE
, log_addr_offset
, log_addr_size
,
1848 ACPI_BUILD_TPMLOG_FILE
, 0);
1850 build_header(linker
, table_data
,
1851 (void *)tcpa
, "TCPA", sizeof(*tcpa
), 2, oem_id
, oem_table_id
);
1854 #define HOLE_640K_START (640 * KiB)
1855 #define HOLE_640K_END (1 * MiB)
1858 build_srat(GArray
*table_data
, BIOSLinker
*linker
, MachineState
*machine
)
1860 AcpiSystemResourceAffinityTable
*srat
;
1861 AcpiSratMemoryAffinity
*numamem
;
1864 int srat_start
, numa_start
, slots
;
1865 uint64_t mem_len
, mem_base
, next_base
;
1866 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1867 X86MachineState
*x86ms
= X86_MACHINE(machine
);
1868 const CPUArchIdList
*apic_ids
= mc
->possible_cpu_arch_ids(machine
);
1869 PCMachineState
*pcms
= PC_MACHINE(machine
);
1870 ram_addr_t hotplugabble_address_space_size
=
1871 object_property_get_int(OBJECT(pcms
), PC_MACHINE_DEVMEM_REGION_SIZE
,
1874 srat_start
= table_data
->len
;
1876 srat
= acpi_data_push(table_data
, sizeof *srat
);
1877 srat
->reserved1
= cpu_to_le32(1);
1879 for (i
= 0; i
< apic_ids
->len
; i
++) {
1880 int node_id
= apic_ids
->cpus
[i
].props
.node_id
;
1881 uint32_t apic_id
= apic_ids
->cpus
[i
].arch_id
;
1883 if (apic_id
< 255) {
1884 AcpiSratProcessorAffinity
*core
;
1886 core
= acpi_data_push(table_data
, sizeof *core
);
1887 core
->type
= ACPI_SRAT_PROCESSOR_APIC
;
1888 core
->length
= sizeof(*core
);
1889 core
->local_apic_id
= apic_id
;
1890 core
->proximity_lo
= node_id
;
1891 memset(core
->proximity_hi
, 0, 3);
1892 core
->local_sapic_eid
= 0;
1893 core
->flags
= cpu_to_le32(1);
1895 AcpiSratProcessorX2ApicAffinity
*core
;
1897 core
= acpi_data_push(table_data
, sizeof *core
);
1898 core
->type
= ACPI_SRAT_PROCESSOR_x2APIC
;
1899 core
->length
= sizeof(*core
);
1900 core
->x2apic_id
= cpu_to_le32(apic_id
);
1901 core
->proximity_domain
= cpu_to_le32(node_id
);
1902 core
->flags
= cpu_to_le32(1);
1907 /* the memory map is a bit tricky, it contains at least one hole
1908 * from 640k-1M and possibly another one from 3.5G-4G.
1911 numa_start
= table_data
->len
;
1913 for (i
= 1; i
< pcms
->numa_nodes
+ 1; ++i
) {
1914 mem_base
= next_base
;
1915 mem_len
= pcms
->node_mem
[i
- 1];
1916 next_base
= mem_base
+ mem_len
;
1918 /* Cut out the 640K hole */
1919 if (mem_base
<= HOLE_640K_START
&&
1920 next_base
> HOLE_640K_START
) {
1921 mem_len
-= next_base
- HOLE_640K_START
;
1923 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
1924 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
1925 MEM_AFFINITY_ENABLED
);
1928 /* Check for the rare case: 640K < RAM < 1M */
1929 if (next_base
<= HOLE_640K_END
) {
1930 next_base
= HOLE_640K_END
;
1933 mem_base
= HOLE_640K_END
;
1934 mem_len
= next_base
- HOLE_640K_END
;
1937 /* Cut out the ACPI_PCI hole */
1938 if (mem_base
<= x86ms
->below_4g_mem_size
&&
1939 next_base
> x86ms
->below_4g_mem_size
) {
1940 mem_len
-= next_base
- x86ms
->below_4g_mem_size
;
1942 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
1943 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
1944 MEM_AFFINITY_ENABLED
);
1946 mem_base
= 1ULL << 32;
1947 mem_len
= next_base
- x86ms
->below_4g_mem_size
;
1948 next_base
= mem_base
+ mem_len
;
1952 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
1953 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
1954 MEM_AFFINITY_ENABLED
);
1958 if (machine
->nvdimms_state
->is_enabled
) {
1959 nvdimm_build_srat(table_data
);
1962 slots
= (table_data
->len
- numa_start
) / sizeof *numamem
;
1963 for (; slots
< pcms
->numa_nodes
+ 2; slots
++) {
1964 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
1965 build_srat_memory(numamem
, 0, 0, 0, MEM_AFFINITY_NOFLAGS
);
1969 * Entry is required for Windows to enable memory hotplug in OS
1970 * and for Linux to enable SWIOTLB when booted with less than
1971 * 4G of RAM. Windows works better if the entry sets proximity
1972 * to the highest NUMA node in the machine.
1973 * Memory devices may override proximity set by this entry,
1974 * providing _PXM method if necessary.
1976 if (hotplugabble_address_space_size
) {
1977 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
1978 build_srat_memory(numamem
, machine
->device_memory
->base
,
1979 hotplugabble_address_space_size
, pcms
->numa_nodes
- 1,
1980 MEM_AFFINITY_HOTPLUGGABLE
| MEM_AFFINITY_ENABLED
);
1983 build_header(linker
, table_data
,
1984 (void *)(table_data
->data
+ srat_start
),
1986 table_data
->len
- srat_start
, 1, x86ms
->oem_id
,
1987 x86ms
->oem_table_id
);
1991 * VT-d spec 8.1 DMA Remapping Reporting Structure
1992 * (version Oct. 2014 or later)
1995 build_dmar_q35(GArray
*table_data
, BIOSLinker
*linker
, const char *oem_id
,
1996 const char *oem_table_id
)
1998 int dmar_start
= table_data
->len
;
2000 AcpiTableDmar
*dmar
;
2001 AcpiDmarHardwareUnit
*drhd
;
2002 AcpiDmarRootPortATS
*atsr
;
2003 uint8_t dmar_flags
= 0;
2004 X86IOMMUState
*iommu
= x86_iommu_get_default();
2005 AcpiDmarDeviceScope
*scope
= NULL
;
2006 /* Root complex IOAPIC use one path[0] only */
2007 size_t ioapic_scope_size
= sizeof(*scope
) + sizeof(scope
->path
[0]);
2008 IntelIOMMUState
*intel_iommu
= INTEL_IOMMU_DEVICE(iommu
);
2011 if (x86_iommu_ir_supported(iommu
)) {
2012 dmar_flags
|= 0x1; /* Flags: 0x1: INT_REMAP */
2015 dmar
= acpi_data_push(table_data
, sizeof(*dmar
));
2016 dmar
->host_address_width
= intel_iommu
->aw_bits
- 1;
2017 dmar
->flags
= dmar_flags
;
2019 /* DMAR Remapping Hardware Unit Definition structure */
2020 drhd
= acpi_data_push(table_data
, sizeof(*drhd
) + ioapic_scope_size
);
2021 drhd
->type
= cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT
);
2022 drhd
->length
= cpu_to_le16(sizeof(*drhd
) + ioapic_scope_size
);
2023 drhd
->flags
= ACPI_DMAR_INCLUDE_PCI_ALL
;
2024 drhd
->pci_segment
= cpu_to_le16(0);
2025 drhd
->address
= cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR
);
2027 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2028 * 8.3.1 (version Oct. 2014 or later). */
2029 scope
= &drhd
->scope
[0];
2030 scope
->entry_type
= 0x03; /* Type: 0x03 for IOAPIC */
2031 scope
->length
= ioapic_scope_size
;
2032 scope
->enumeration_id
= ACPI_BUILD_IOAPIC_ID
;
2033 scope
->bus
= Q35_PSEUDO_BUS_PLATFORM
;
2034 scope
->path
[0].device
= PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC
);
2035 scope
->path
[0].function
= PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC
);
2037 if (iommu
->dt_supported
) {
2038 atsr
= acpi_data_push(table_data
, sizeof(*atsr
));
2039 atsr
->type
= cpu_to_le16(ACPI_DMAR_TYPE_ATSR
);
2040 atsr
->length
= cpu_to_le16(sizeof(*atsr
));
2041 atsr
->flags
= ACPI_DMAR_ATSR_ALL_PORTS
;
2042 atsr
->pci_segment
= cpu_to_le16(0);
2045 build_header(linker
, table_data
, (void *)(table_data
->data
+ dmar_start
),
2046 "DMAR", table_data
->len
- dmar_start
, 1, oem_id
, oem_table_id
);
2050 * Windows ACPI Emulated Devices Table
2051 * (Version 1.0 - April 6, 2009)
2052 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx
2054 * Helpful to speedup Windows guests and ignored by others.
2057 build_waet(GArray
*table_data
, BIOSLinker
*linker
, const char *oem_id
,
2058 const char *oem_table_id
)
2060 int waet_start
= table_data
->len
;
2063 acpi_data_push(table_data
, sizeof(AcpiTableHeader
));
2065 * Set "ACPI PM timer good" flag.
2067 * Tells Windows guests that our ACPI PM timer is reliable in the
2068 * sense that guest can read it only once to obtain a reliable value.
2069 * Which avoids costly VMExits caused by guest re-reading it unnecessarily.
2071 build_append_int_noprefix(table_data
, 1 << 1 /* ACPI PM timer good */, 4);
2073 build_header(linker
, table_data
, (void *)(table_data
->data
+ waet_start
),
2074 "WAET", table_data
->len
- waet_start
, 1, oem_id
, oem_table_id
);
2078 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2079 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2081 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
2084 * Insert IVHD entry for device and recurse, insert alias, or insert range as
2085 * necessary for the PCI topology.
2088 insert_ivhd(PCIBus
*bus
, PCIDevice
*dev
, void *opaque
)
2090 GArray
*table_data
= opaque
;
2093 /* "Select" IVHD entry, type 0x2 */
2094 entry
= PCI_BUILD_BDF(pci_bus_num(bus
), dev
->devfn
) << 8 | 0x2;
2095 build_append_int_noprefix(table_data
, entry
, 4);
2097 if (object_dynamic_cast(OBJECT(dev
), TYPE_PCI_BRIDGE
)) {
2098 PCIBus
*sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(dev
));
2099 uint8_t sec
= pci_bus_num(sec_bus
);
2100 uint8_t sub
= dev
->config
[PCI_SUBORDINATE_BUS
];
2102 if (pci_bus_is_express(sec_bus
)) {
2104 * Walk the bus if there are subordinates, otherwise use a range
2105 * to cover an entire leaf bus. We could potentially also use a
2106 * range for traversed buses, but we'd need to take care not to
2107 * create both Select and Range entries covering the same device.
2108 * This is easier and potentially more compact.
2110 * An example bare metal system seems to use Select entries for
2111 * root ports without a slot (ie. built-ins) and Range entries
2112 * when there is a slot. The same system also only hard-codes
2113 * the alias range for an onboard PCIe-to-PCI bridge, apparently
2114 * making no effort to support nested bridges. We attempt to
2115 * be more thorough here.
2117 if (sec
== sub
) { /* leaf bus */
2118 /* "Start of Range" IVHD entry, type 0x3 */
2119 entry
= PCI_BUILD_BDF(sec
, PCI_DEVFN(0, 0)) << 8 | 0x3;
2120 build_append_int_noprefix(table_data
, entry
, 4);
2121 /* "End of Range" IVHD entry, type 0x4 */
2122 entry
= PCI_BUILD_BDF(sub
, PCI_DEVFN(31, 7)) << 8 | 0x4;
2123 build_append_int_noprefix(table_data
, entry
, 4);
2125 pci_for_each_device(sec_bus
, sec
, insert_ivhd
, table_data
);
2129 * If the secondary bus is conventional, then we need to create an
2130 * Alias range for everything downstream. The range covers the
2131 * first devfn on the secondary bus to the last devfn on the
2132 * subordinate bus. The alias target depends on legacy versus
2133 * express bridges, just as in pci_device_iommu_address_space().
2134 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec.
2136 uint16_t dev_id_a
, dev_id_b
;
2138 dev_id_a
= PCI_BUILD_BDF(sec
, PCI_DEVFN(0, 0));
2140 if (pci_is_express(dev
) &&
2141 pcie_cap_get_type(dev
) == PCI_EXP_TYPE_PCI_BRIDGE
) {
2142 dev_id_b
= dev_id_a
;
2144 dev_id_b
= PCI_BUILD_BDF(pci_bus_num(bus
), dev
->devfn
);
2147 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */
2148 build_append_int_noprefix(table_data
, dev_id_a
<< 8 | 0x43, 4);
2149 build_append_int_noprefix(table_data
, dev_id_b
<< 8 | 0x0, 4);
2151 /* "End of Range" IVHD entry, type 0x4 */
2152 entry
= PCI_BUILD_BDF(sub
, PCI_DEVFN(31, 7)) << 8 | 0x4;
2153 build_append_int_noprefix(table_data
, entry
, 4);
2158 /* For all PCI host bridges, walk and insert IVHD entries */
2160 ivrs_host_bridges(Object
*obj
, void *opaque
)
2162 GArray
*ivhd_blob
= opaque
;
2164 if (object_dynamic_cast(obj
, TYPE_PCI_HOST_BRIDGE
)) {
2165 PCIBus
*bus
= PCI_HOST_BRIDGE(obj
)->bus
;
2168 pci_for_each_device(bus
, pci_bus_num(bus
), insert_ivhd
, ivhd_blob
);
2176 build_amd_iommu(GArray
*table_data
, BIOSLinker
*linker
, const char *oem_id
,
2177 const char *oem_table_id
)
2179 int ivhd_table_len
= 24;
2180 int iommu_start
= table_data
->len
;
2181 AMDVIState
*s
= AMD_IOMMU_DEVICE(x86_iommu_get_default());
2182 GArray
*ivhd_blob
= g_array_new(false, true, 1);
2185 acpi_data_push(table_data
, sizeof(AcpiTableHeader
));
2186 /* IVinfo - IO virtualization information common to all
2187 * IOMMU units in a system
2189 build_append_int_noprefix(table_data
, 40UL << 8/* PASize */, 4);
2191 build_append_int_noprefix(table_data
, 0, 8);
2193 /* IVHD definition - type 10h */
2194 build_append_int_noprefix(table_data
, 0x10, 1);
2195 /* virtualization flags */
2196 build_append_int_noprefix(table_data
,
2197 (1UL << 0) | /* HtTunEn */
2198 (1UL << 4) | /* iotblSup */
2199 (1UL << 6) | /* PrefSup */
2200 (1UL << 7), /* PPRSup */
2204 * A PCI bus walk, for each PCI host bridge, is necessary to create a
2205 * complete set of IVHD entries. Do this into a separate blob so that we
2206 * can calculate the total IVRS table length here and then append the new
2207 * blob further below. Fall back to an entry covering all devices, which
2208 * is sufficient when no aliases are present.
2210 object_child_foreach_recursive(object_get_root(),
2211 ivrs_host_bridges
, ivhd_blob
);
2213 if (!ivhd_blob
->len
) {
2215 * Type 1 device entry reporting all devices
2216 * These are 4-byte device entries currently reporting the range of
2217 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2219 build_append_int_noprefix(ivhd_blob
, 0x0000001, 4);
2222 ivhd_table_len
+= ivhd_blob
->len
;
2225 * When interrupt remapping is supported, we add a special IVHD device
2228 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2229 ivhd_table_len
+= 8;
2233 build_append_int_noprefix(table_data
, ivhd_table_len
, 2);
2235 build_append_int_noprefix(table_data
, s
->devid
, 2);
2236 /* Capability offset */
2237 build_append_int_noprefix(table_data
, s
->capab_offset
, 2);
2238 /* IOMMU base address */
2239 build_append_int_noprefix(table_data
, s
->mmio
.addr
, 8);
2240 /* PCI Segment Group */
2241 build_append_int_noprefix(table_data
, 0, 2);
2243 build_append_int_noprefix(table_data
, 0, 2);
2244 /* IOMMU Feature Reporting */
2245 build_append_int_noprefix(table_data
,
2246 (48UL << 30) | /* HATS */
2247 (48UL << 28) | /* GATS */
2248 (1UL << 2) | /* GTSup */
2249 (1UL << 6), /* GASup */
2252 /* IVHD entries as found above */
2253 g_array_append_vals(table_data
, ivhd_blob
->data
, ivhd_blob
->len
);
2254 g_array_free(ivhd_blob
, TRUE
);
2257 * Add a special IVHD device type.
2258 * Refer to spec - Table 95: IVHD device entry type codes
2260 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
2261 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
2263 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2264 build_append_int_noprefix(table_data
,
2265 (0x1ull
<< 56) | /* type IOAPIC */
2266 (IOAPIC_SB_DEVID
<< 40) | /* IOAPIC devid */
2267 0x48, /* special device */
2271 build_header(linker
, table_data
, (void *)(table_data
->data
+ iommu_start
),
2272 "IVRS", table_data
->len
- iommu_start
, 1, oem_id
,
2277 struct AcpiBuildState
{
2278 /* Copy of table in RAM (for patching). */
2279 MemoryRegion
*table_mr
;
2280 /* Is table patched? */
2283 MemoryRegion
*rsdp_mr
;
2284 MemoryRegion
*linker_mr
;
2287 static bool acpi_get_mcfg(AcpiMcfgInfo
*mcfg
)
2292 pci_host
= acpi_get_i386_pci_host();
2295 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_BASE
, NULL
);
2299 mcfg
->base
= qnum_get_uint(qobject_to(QNum
, o
));
2301 if (mcfg
->base
== PCIE_BASE_ADDR_UNMAPPED
) {
2305 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_SIZE
, NULL
);
2307 mcfg
->size
= qnum_get_uint(qobject_to(QNum
, o
));
2313 void acpi_build(AcpiBuildTables
*tables
, MachineState
*machine
)
2315 PCMachineState
*pcms
= PC_MACHINE(machine
);
2316 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2317 X86MachineState
*x86ms
= X86_MACHINE(machine
);
2318 GArray
*table_offsets
;
2319 unsigned facs
, dsdt
, rsdt
, fadt
;
2323 Range pci_hole
, pci_hole64
;
2326 GArray
*tables_blob
= tables
->table_data
;
2327 AcpiSlicOem slic_oem
= { .id
= NULL
, .table_id
= NULL
};
2328 Object
*vmgenid_dev
;
2332 acpi_get_pm_info(machine
, &pm
);
2333 acpi_get_misc_info(&misc
);
2334 acpi_get_pci_holes(&pci_hole
, &pci_hole64
);
2335 acpi_get_slic_oem(&slic_oem
);
2338 oem_id
= slic_oem
.id
;
2340 oem_id
= x86ms
->oem_id
;
2343 if (slic_oem
.table_id
) {
2344 oem_table_id
= slic_oem
.table_id
;
2346 oem_table_id
= x86ms
->oem_table_id
;
2349 table_offsets
= g_array_new(false, true /* clear */,
2351 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2353 bios_linker_loader_alloc(tables
->linker
,
2354 ACPI_BUILD_TABLE_FILE
, tables_blob
,
2355 64 /* Ensure FACS is aligned */,
2356 false /* high memory */);
2359 * FACS is pointed to by FADT.
2360 * We place it first since it's the only table that has alignment
2363 facs
= tables_blob
->len
;
2364 build_facs(tables_blob
);
2366 /* DSDT is pointed to by FADT */
2367 dsdt
= tables_blob
->len
;
2368 build_dsdt(tables_blob
, tables
->linker
, &pm
, &misc
,
2369 &pci_hole
, &pci_hole64
, machine
);
2371 /* Count the size of the DSDT and SSDT, we will need it for legacy
2372 * sizing of ACPI tables.
2374 aml_len
+= tables_blob
->len
- dsdt
;
2376 /* ACPI tables pointed to by RSDT */
2377 fadt
= tables_blob
->len
;
2378 acpi_add_table(table_offsets
, tables_blob
);
2379 pm
.fadt
.facs_tbl_offset
= &facs
;
2380 pm
.fadt
.dsdt_tbl_offset
= &dsdt
;
2381 pm
.fadt
.xdsdt_tbl_offset
= &dsdt
;
2382 build_fadt(tables_blob
, tables
->linker
, &pm
.fadt
, oem_id
, oem_table_id
);
2383 aml_len
+= tables_blob
->len
- fadt
;
2385 acpi_add_table(table_offsets
, tables_blob
);
2386 acpi_build_madt(tables_blob
, tables
->linker
, x86ms
,
2387 ACPI_DEVICE_IF(x86ms
->acpi_dev
), x86ms
->oem_id
,
2388 x86ms
->oem_table_id
);
2390 vmgenid_dev
= find_vmgenid_dev();
2392 acpi_add_table(table_offsets
, tables_blob
);
2393 vmgenid_build_acpi(VMGENID(vmgenid_dev
), tables_blob
,
2394 tables
->vmgenid
, tables
->linker
, x86ms
->oem_id
);
2397 if (misc
.has_hpet
) {
2398 acpi_add_table(table_offsets
, tables_blob
);
2399 build_hpet(tables_blob
, tables
->linker
, x86ms
->oem_id
,
2400 x86ms
->oem_table_id
);
2402 if (misc
.tpm_version
!= TPM_VERSION_UNSPEC
) {
2403 if (misc
.tpm_version
== TPM_VERSION_1_2
) {
2404 acpi_add_table(table_offsets
, tables_blob
);
2405 build_tpm_tcpa(tables_blob
, tables
->linker
, tables
->tcpalog
,
2406 x86ms
->oem_id
, x86ms
->oem_table_id
);
2407 } else { /* TPM_VERSION_2_0 */
2408 acpi_add_table(table_offsets
, tables_blob
);
2409 build_tpm2(tables_blob
, tables
->linker
, tables
->tcpalog
,
2410 x86ms
->oem_id
, x86ms
->oem_table_id
);
2413 if (pcms
->numa_nodes
) {
2414 acpi_add_table(table_offsets
, tables_blob
);
2415 build_srat(tables_blob
, tables
->linker
, machine
);
2416 if (machine
->numa_state
->have_numa_distance
) {
2417 acpi_add_table(table_offsets
, tables_blob
);
2418 build_slit(tables_blob
, tables
->linker
, machine
, x86ms
->oem_id
,
2419 x86ms
->oem_table_id
);
2421 if (machine
->numa_state
->hmat_enabled
) {
2422 acpi_add_table(table_offsets
, tables_blob
);
2423 build_hmat(tables_blob
, tables
->linker
, machine
->numa_state
,
2424 x86ms
->oem_id
, x86ms
->oem_table_id
);
2427 if (acpi_get_mcfg(&mcfg
)) {
2428 acpi_add_table(table_offsets
, tables_blob
);
2429 build_mcfg(tables_blob
, tables
->linker
, &mcfg
, x86ms
->oem_id
,
2430 x86ms
->oem_table_id
);
2432 if (x86_iommu_get_default()) {
2433 IommuType IOMMUType
= x86_iommu_get_type();
2434 if (IOMMUType
== TYPE_AMD
) {
2435 acpi_add_table(table_offsets
, tables_blob
);
2436 build_amd_iommu(tables_blob
, tables
->linker
, x86ms
->oem_id
,
2437 x86ms
->oem_table_id
);
2438 } else if (IOMMUType
== TYPE_INTEL
) {
2439 acpi_add_table(table_offsets
, tables_blob
);
2440 build_dmar_q35(tables_blob
, tables
->linker
, x86ms
->oem_id
,
2441 x86ms
->oem_table_id
);
2444 if (machine
->nvdimms_state
->is_enabled
) {
2445 nvdimm_build_acpi(table_offsets
, tables_blob
, tables
->linker
,
2446 machine
->nvdimms_state
, machine
->ram_slots
,
2447 x86ms
->oem_id
, x86ms
->oem_table_id
);
2450 acpi_add_table(table_offsets
, tables_blob
);
2451 build_waet(tables_blob
, tables
->linker
, x86ms
->oem_id
, x86ms
->oem_table_id
);
2453 /* Add tables supplied by user (if any) */
2454 for (u
= acpi_table_first(); u
; u
= acpi_table_next(u
)) {
2455 unsigned len
= acpi_table_len(u
);
2457 acpi_add_table(table_offsets
, tables_blob
);
2458 g_array_append_vals(tables_blob
, u
, len
);
2461 /* RSDT is pointed to by RSDP */
2462 rsdt
= tables_blob
->len
;
2463 build_rsdt(tables_blob
, tables
->linker
, table_offsets
,
2464 oem_id
, oem_table_id
);
2466 /* RSDP is in FSEG memory, so allocate it separately */
2468 AcpiRsdpData rsdp_data
= {
2470 .oem_id
= x86ms
->oem_id
,
2471 .xsdt_tbl_offset
= NULL
,
2472 .rsdt_tbl_offset
= &rsdt
,
2474 build_rsdp(tables
->rsdp
, tables
->linker
, &rsdp_data
);
2475 if (!pcmc
->rsdp_in_ram
) {
2476 /* We used to allocate some extra space for RSDP revision 2 but
2477 * only used the RSDP revision 0 space. The extra bytes were
2478 * zeroed out and not used.
2479 * Here we continue wasting those extra 16 bytes to make sure we
2480 * don't break migration for machine types 2.2 and older due to
2481 * RSDP blob size mismatch.
2483 build_append_int_noprefix(tables
->rsdp
, 0, 16);
2487 /* We'll expose it all to Guest so we want to reduce
2488 * chance of size changes.
2490 * We used to align the tables to 4k, but of course this would
2491 * too simple to be enough. 4k turned out to be too small an
2492 * alignment very soon, and in fact it is almost impossible to
2493 * keep the table size stable for all (max_cpus, max_memory_slots)
2494 * combinations. So the table size is always 64k for pc-i440fx-2.1
2495 * and we give an error if the table grows beyond that limit.
2497 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2498 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2499 * than 2.0 and we can always pad the smaller tables with zeros. We can
2500 * then use the exact size of the 2.0 tables.
2502 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2504 if (pcmc
->legacy_acpi_table_size
) {
2505 /* Subtracting aml_len gives the size of fixed tables. Then add the
2506 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2508 int legacy_aml_len
=
2509 pcmc
->legacy_acpi_table_size
+
2510 ACPI_BUILD_LEGACY_CPU_AML_SIZE
* x86ms
->apic_id_limit
;
2511 int legacy_table_size
=
2512 ROUND_UP(tables_blob
->len
- aml_len
+ legacy_aml_len
,
2513 ACPI_BUILD_ALIGN_SIZE
);
2514 if (tables_blob
->len
> legacy_table_size
) {
2515 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2516 warn_report("ACPI table size %u exceeds %d bytes,"
2517 " migration may not work",
2518 tables_blob
->len
, legacy_table_size
);
2519 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2520 " or PCI bridges.");
2522 g_array_set_size(tables_blob
, legacy_table_size
);
2524 /* Make sure we have a buffer in case we need to resize the tables. */
2525 if (tables_blob
->len
> ACPI_BUILD_TABLE_SIZE
/ 2) {
2526 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2527 warn_report("ACPI table size %u exceeds %d bytes,"
2528 " migration may not work",
2529 tables_blob
->len
, ACPI_BUILD_TABLE_SIZE
/ 2);
2530 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2531 " or PCI bridges.");
2533 acpi_align_size(tables_blob
, ACPI_BUILD_TABLE_SIZE
);
2536 acpi_align_size(tables
->linker
->cmd_blob
, ACPI_BUILD_ALIGN_SIZE
);
2538 /* Cleanup memory that's no longer used. */
2539 g_array_free(table_offsets
, true);
2542 static void acpi_ram_update(MemoryRegion
*mr
, GArray
*data
)
2544 uint32_t size
= acpi_data_len(data
);
2546 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2547 memory_region_ram_resize(mr
, size
, &error_abort
);
2549 memcpy(memory_region_get_ram_ptr(mr
), data
->data
, size
);
2550 memory_region_set_dirty(mr
, 0, size
);
2553 static void acpi_build_update(void *build_opaque
)
2555 AcpiBuildState
*build_state
= build_opaque
;
2556 AcpiBuildTables tables
;
2558 /* No state to update or already patched? Nothing to do. */
2559 if (!build_state
|| build_state
->patched
) {
2562 build_state
->patched
= 1;
2564 acpi_build_tables_init(&tables
);
2566 acpi_build(&tables
, MACHINE(qdev_get_machine()));
2568 acpi_ram_update(build_state
->table_mr
, tables
.table_data
);
2570 if (build_state
->rsdp
) {
2571 memcpy(build_state
->rsdp
, tables
.rsdp
->data
, acpi_data_len(tables
.rsdp
));
2573 acpi_ram_update(build_state
->rsdp_mr
, tables
.rsdp
);
2576 acpi_ram_update(build_state
->linker_mr
, tables
.linker
->cmd_blob
);
2577 acpi_build_tables_cleanup(&tables
, true);
2580 static void acpi_build_reset(void *build_opaque
)
2582 AcpiBuildState
*build_state
= build_opaque
;
2583 build_state
->patched
= 0;
2586 static const VMStateDescription vmstate_acpi_build
= {
2587 .name
= "acpi_build",
2589 .minimum_version_id
= 1,
2590 .fields
= (VMStateField
[]) {
2591 VMSTATE_UINT8(patched
, AcpiBuildState
),
2592 VMSTATE_END_OF_LIST()
2596 void acpi_setup(void)
2598 PCMachineState
*pcms
= PC_MACHINE(qdev_get_machine());
2599 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2600 X86MachineState
*x86ms
= X86_MACHINE(pcms
);
2601 AcpiBuildTables tables
;
2602 AcpiBuildState
*build_state
;
2603 Object
*vmgenid_dev
;
2605 static FwCfgTPMConfig tpm_config
;
2607 if (!x86ms
->fw_cfg
) {
2608 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2612 if (!pcms
->acpi_build_enabled
) {
2613 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2617 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms
))) {
2618 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2622 build_state
= g_malloc0(sizeof *build_state
);
2624 acpi_build_tables_init(&tables
);
2625 acpi_build(&tables
, MACHINE(pcms
));
2627 /* Now expose it all to Guest */
2628 build_state
->table_mr
= acpi_add_rom_blob(acpi_build_update
,
2629 build_state
, tables
.table_data
,
2630 ACPI_BUILD_TABLE_FILE
);
2631 assert(build_state
->table_mr
!= NULL
);
2633 build_state
->linker_mr
=
2634 acpi_add_rom_blob(acpi_build_update
, build_state
,
2635 tables
.linker
->cmd_blob
, ACPI_BUILD_LOADER_FILE
);
2637 fw_cfg_add_file(x86ms
->fw_cfg
, ACPI_BUILD_TPMLOG_FILE
,
2638 tables
.tcpalog
->data
, acpi_data_len(tables
.tcpalog
));
2641 if (tpm
&& object_property_get_bool(OBJECT(tpm
), "ppi", &error_abort
)) {
2642 tpm_config
= (FwCfgTPMConfig
) {
2643 .tpmppi_address
= cpu_to_le32(TPM_PPI_ADDR_BASE
),
2644 .tpm_version
= tpm_get_version(tpm
),
2645 .tpmppi_version
= TPM_PPI_VERSION_1_30
2647 fw_cfg_add_file(x86ms
->fw_cfg
, "etc/tpm/config",
2648 &tpm_config
, sizeof tpm_config
);
2651 vmgenid_dev
= find_vmgenid_dev();
2653 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev
), x86ms
->fw_cfg
,
2657 if (!pcmc
->rsdp_in_ram
) {
2659 * Keep for compatibility with old machine types.
2660 * Though RSDP is small, its contents isn't immutable, so
2661 * we'll update it along with the rest of tables on guest access.
2663 uint32_t rsdp_size
= acpi_data_len(tables
.rsdp
);
2665 build_state
->rsdp
= g_memdup(tables
.rsdp
->data
, rsdp_size
);
2666 fw_cfg_add_file_callback(x86ms
->fw_cfg
, ACPI_BUILD_RSDP_FILE
,
2667 acpi_build_update
, NULL
, build_state
,
2668 build_state
->rsdp
, rsdp_size
, true);
2669 build_state
->rsdp_mr
= NULL
;
2671 build_state
->rsdp
= NULL
;
2672 build_state
->rsdp_mr
= acpi_add_rom_blob(acpi_build_update
,
2673 build_state
, tables
.rsdp
,
2674 ACPI_BUILD_RSDP_FILE
);
2677 qemu_register_reset(acpi_build_reset
, build_state
);
2678 acpi_build_reset(build_state
);
2679 vmstate_register(NULL
, 0, &vmstate_acpi_build
, build_state
);
2681 /* Cleanup tables but don't free the memory: we track it
2684 acpi_build_tables_cleanup(&tables
, false);