hw/arm/s3c24xx_timers.c

   1 /* hw/s3c24xx_timers.c
   2  *
   3  * Samsung S3C24XX PWM emulation
   4  *
   5  * Copyright 2009 Daniel Silverstone and Vincent Sanders
   6  *
   7  * Copyright 2010, 2013 Stefan Weil
   8  *
   9  * This file is under the terms of the GNU General Public License Version 2.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "cpu.h"
  14 #include "hw/hw.h"
  15 #include "exec/address-spaces.h" /* get_system_memory */
  16 #include "qemu/timer.h"
  17
  18 #include "s3c24xx.h"
  19
  20 /* The S3c24xx timer peripheral has five separate timers. The first four (0-3)
  21  * have physical external connections and can be used for PWM control. The
  22  * fifth has no external connection but can generate interrupts because of this
  23  * it is almost always used to generate the Operating system clock tick
  24  * interrupt.
  25  *
  26  * The timers can be fed from the peripheral clock (pclk) or from one of two
  27  * external inputs (tclk0 and 1). The external inputs are split so tclk0 is
  28  * used for timer 0 and 1 and tclk1 feeds the remaining three timers.
  29  *
  30  * The emulation presented here only iplements the fifth timer (timer 4) as
  31  * there is no sensible way to interpret the external physical PWM signals from
  32  * timers 0 to 4 yet.
  33  *
  34  * ticks_per_sec is ticks per second for the qemu clocks
  35  * TCLK1 is the assumed input for timer4
  36  * Thus, period in ticks of timer4 is:
  37  *
  38  * (timer4_period * ticks_per_sec) / TCLK1
  39  */
  40
  41 /* Timer configuration 0 */
  42 #define S3C_TIMERS_TCFG0 0
  43 /* Timer configuration 1 */
  44 #define S3C_TIMERS_TCFG1 1
  45 /* Timer control */
  46 #define S3C_TIMERS_TCON 2
  47 /* Timer count buffer 0 */
  48 #define S3C_TIMERS_TCNTB0 3
  49 /* Timer compare buffer 0 */
  50 #define S3C_TIMERS_TCMPB0 4
  51 /* Timer count observation 0 */
  52 #define S3C_TIMERS_TCNTO0 5
  53 /* Timer count buffer 1 */
  54 #define S3C_TIMERS_TCNTB1 6
  55 /* Timer compare buffer 1 */
  56 #define S3C_TIMERS_TCMPB1 7
  57 /* Timer count observation 1 */
  58 #define S3C_TIMERS_TCNTO1 8
  59 /* Timer count buffer 2 */
  60 #define S3C_TIMERS_TCNTB2 9
  61 /* Timer compare buffer 2 */
  62 #define S3C_TIMERS_TCMPB2 10
  63 /* Timer count observation 2 */
  64 #define S3C_TIMERS_TCNTO2 11
  65 /* Timer count buffer 3 */
  66 #define S3C_TIMERS_TCNTB3 12
  67 /* Timer compare buffer 3 */
  68 #define S3C_TIMERS_TCMPB3 13
  69 /* Timer count observation 3 */
  70 #define S3C_TIMERS_TCNTO3 14
  71 /* Timer count buffer 4 */
  72 #define S3C_TIMERS_TCNTB4 15
  73 /* Timer count observation 4 */
  74 #define S3C_TIMERS_TCNTO4 16
  75
  76 /* timer controller state */
  77 struct s3c24xx_timers_state_s {
  78     MemoryRegion mmio;
  79     uint32_t tclk0; /* first timer clock source frequency */
  80     uint32_t tclk1; /* second timer clock source frequency */
  81
  82     uint32_t timers_reg[17]; /* registers */
  83
  84     /* resources for each timer */
  85     QEMUTimer *timer[5];
  86     qemu_irq irqs[5];
  87     uint32_t timer_reload_value[5];
  88     int64_t timer_last_ticked[5];
  89
  90 };
  91
  92
  93 static void
  94 s3c24xx_schedule_timer(struct s3c24xx_timers_state_s *s, int num)
  95 {
  96     s->timers_reg[S3C_TIMERS_TCNTB4] = s->timer_reload_value[num];
  97     s->timer_last_ticked[num] = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  98     timer_mod(s->timer[num],
  99                    s->timer_last_ticked[num] +
 100                    ((s->timer_reload_value[num] * NANOSECONDS_PER_SECOND) / s->tclk1));
 101 }
 102
 103 static void
 104 s3c24xx_timer4_tick(void *opaque)
 105 {
 106     struct s3c24xx_timers_state_s *s = (struct s3c24xx_timers_state_s *)opaque;
 107
 108     /* set IRQ */
 109     qemu_set_irq(s->irqs[4], 1);
 110
 111     /* if auto reload is set rescedule the next tick */
 112     if (s->timers_reg[S3C_TIMERS_TCON] & (1<<22)) {
 113         s3c24xx_schedule_timer(s, 4);
 114     }
 115 }
 116
 117 static void s3c24xx_timers_write_f(void *opaque, hwaddr addr_,
 118                                    uint64_t value, unsigned size)
 119 {
 120     struct s3c24xx_timers_state_s *s = opaque;
 121     int addr = (addr_ >> 2) & 0x1f;
 122
 123     s->timers_reg[addr] = value;
 124
 125     if (addr == S3C_TIMERS_TCON) {
 126         if (value & (1 << 21)) {
 127             /* Timer4 manual update is set, copy in the reload value */
 128             s->timer_reload_value[4] = s->timers_reg[S3C_TIMERS_TCNTB4];
 129         } else {
 130             /* Timer4 manual update is not set */
 131             if (value & (1 << 20)) {
 132                 /* The timer is supposed to be running so start it  */
 133                 s3c24xx_schedule_timer(s, 4);
 134             }
 135         }
 136     }
 137 }
 138
 139 static uint64_t
 140 s3c24xx_timers_read_f(void *opaque, hwaddr addr_, unsigned size)
 141 {
 142     struct s3c24xx_timers_state_s *s = opaque;
 143     int addr = (addr_ >> 2) & 0x1f;
 144
 145     if (addr == S3C_TIMERS_TCNTO4 ) {
 146         return s->timer_reload_value[4] -
 147             (((qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->timer_last_ticked[4]) * s->tclk1) / NANOSECONDS_PER_SECOND);
 148     }
 149     return s->timers_reg[addr];
 150 }
 151
 152 static const MemoryRegionOps s3c24xx_timers_ops = {
 153     .read = s3c24xx_timers_read_f,
 154     .write = s3c24xx_timers_write_f,
 155     .endianness = DEVICE_NATIVE_ENDIAN,
 156     .valid = {
 157         .min_access_size = 1,
 158         .max_access_size = 4
 159     }
 160 };
 161
 162 static void s3c24xx_timers_save(QEMUFile *f, void *opaque)
 163 {
 164     struct s3c24xx_timers_state_s *s = (struct s3c24xx_timers_state_s *)opaque;
 165     int i;
 166
 167     for (i = 0; i < 17; i ++)
 168         qemu_put_be32s(f, &s->timers_reg[i]);
 169 }
 170
 171 static int s3c24xx_timers_load(QEMUFile *f, void *opaque, int version_id)
 172 {
 173     struct s3c24xx_timers_state_s *s = (struct s3c24xx_timers_state_s *)opaque;
 174     int i;
 175
 176     for (i = 0; i < 17; i ++)
 177         qemu_get_be32s(f, &s->timers_reg[i]);
 178
 179     return 0;
 180 }
 181
 182 /* S3c24xx timer initialisation */
 183 struct s3c24xx_timers_state_s *
 184 s3c24xx_timers_init(S3CState *soc, hwaddr base_addr, uint32_t tclk0, uint32_t tclk1)
 185 {
 186     MemoryRegion *system_memory = get_system_memory();
 187     struct s3c24xx_timers_state_s *s;
 188     int i;
 189
 190     s = g_malloc0(sizeof(struct s3c24xx_timers_state_s));
 191
 192     memory_region_init_io(&s->mmio, OBJECT(s),
 193                           &s3c24xx_timers_ops, s, "s3c24xx-timers", 17 * 4);
 194     memory_region_add_subregion(system_memory, base_addr, &s->mmio);
 195
 196     register_savevm(NULL, "s3c24xx_timers", 0, 0, s3c24xx_timers_save, s3c24xx_timers_load, s);
 197
 198     s->tclk0 = tclk0;
 199     s->tclk1 = tclk1;
 200
 201     /* set up per timer values */
 202     for (i = 0; i < 5; i++) {
 203         s->irqs[i] = s3c24xx_get_irq(soc->irq, 10 + i);
 204         s->timer_reload_value[i] = 0;
 205         s->timer_last_ticked[i] = 0;
 206     }
 207
 208     s->timer[4] = timer_new_ns(QEMU_CLOCK_VIRTUAL, s3c24xx_timer4_tick, s);
 209
 210     return s;
 211 }