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Merge remote-tracking branch 'qemu/master'
[qemu/ar7.git] / target-mips / op_helper.c
blob8e651bb320afef35284a2eea2a4b64398445c301
1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "cpu.h"
21 #include "qemu/host-utils.h"
22 #include "exec/helper-proto.h"
23 #include "exec/cpu_ldst.h"
24
25 #ifndef CONFIG_USER_ONLY
26 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
27 #endif
28
29 /*****************************************************************************/
30 /* Exceptions processing helpers */
31
32 static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
33 uint32_t exception,
34 int error_code,
35 uintptr_t pc)
36 {
37 CPUState *cs = CPU(mips_env_get_cpu(env));
38
39 if (exception < EXCP_SC) {
40 qemu_log("%s: %d %d\n", __func__, exception, error_code);
41 }
42 cs->exception_index = exception;
43 env->error_code = error_code;
44
45 if (pc) {
46 /* now we have a real cpu fault */
47 cpu_restore_state(cs, pc);
48 }
49
50 cpu_loop_exit(cs);
51 }
52
53 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
54 uint32_t exception,
55 uintptr_t pc)
56 {
57 do_raise_exception_err(env, exception, 0, pc);
58 }
59
60 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
61 int error_code)
62 {
63 do_raise_exception_err(env, exception, error_code, 0);
64 }
65
66 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
67 {
68 do_raise_exception(env, exception, 0);
69 }
70
71 #if defined(CONFIG_USER_ONLY)
72 #define HELPER_LD(name, insn, type) \
73 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
74 int mem_idx) \
75 { \
76 return (type) insn##_raw(addr); \
77 }
78 #else
79 #define HELPER_LD(name, insn, type) \
80 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
81 int mem_idx) \
82 { \
83 switch (mem_idx) \
84 { \
85 case 0: return (type) cpu_##insn##_kernel(env, addr); break; \
86 case 1: return (type) cpu_##insn##_super(env, addr); break; \
87 default: \
88 case 2: return (type) cpu_##insn##_user(env, addr); break; \
89 } \
90 }
91 #endif
92 HELPER_LD(lbu, ldub, uint8_t)
93 HELPER_LD(lw, ldl, int32_t)
94 #ifdef TARGET_MIPS64
95 HELPER_LD(ld, ldq, int64_t)
96 #endif
97 #undef HELPER_LD
98
99 #if defined(CONFIG_USER_ONLY)
100 #define HELPER_ST(name, insn, type) \
101 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
102 type val, int mem_idx) \
103 { \
104 insn##_raw(addr, val); \
105 }
106 #else
107 #define HELPER_ST(name, insn, type) \
108 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
109 type val, int mem_idx) \
110 { \
111 switch (mem_idx) \
112 { \
113 case 0: cpu_##insn##_kernel(env, addr, val); break; \
114 case 1: cpu_##insn##_super(env, addr, val); break; \
115 default: \
116 case 2: cpu_##insn##_user(env, addr, val); break; \
117 } \
118 }
119 #endif
120 HELPER_ST(sb, stb, uint8_t)
121 HELPER_ST(sw, stl, uint32_t)
122 #ifdef TARGET_MIPS64
123 HELPER_ST(sd, stq, uint64_t)
124 #endif
125 #undef HELPER_ST
126
127 target_ulong helper_clo (target_ulong arg1)
128 {
129 return clo32(arg1);
130 }
131
132 target_ulong helper_clz (target_ulong arg1)
133 {
134 return clz32(arg1);
135 }
136
137 #if defined(TARGET_MIPS64)
138 target_ulong helper_dclo (target_ulong arg1)
139 {
140 return clo64(arg1);
141 }
142
143 target_ulong helper_dclz (target_ulong arg1)
144 {
145 return clz64(arg1);
146 }
147 #endif /* TARGET_MIPS64 */
148
149 /* 64 bits arithmetic for 32 bits hosts */
150 static inline uint64_t get_HILO(CPUMIPSState *env)
151 {
152 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
153 }
154
155 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
156 {
157 target_ulong tmp;
158 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
159 tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
160 return tmp;
161 }
162
163 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
164 {
165 target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
166 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
167 return tmp;
168 }
169
170 /* Multiplication variants of the vr54xx. */
171 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
172 target_ulong arg2)
173 {
174 return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
175 (int64_t)(int32_t)arg2));
176 }
177
178 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
179 target_ulong arg2)
180 {
181 return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
182 (uint64_t)(uint32_t)arg2);
183 }
184
185 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
186 target_ulong arg2)
187 {
188 return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
189 (int64_t)(int32_t)arg2);
190 }
191
192 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
193 target_ulong arg2)
194 {
195 return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
196 (int64_t)(int32_t)arg2);
197 }
198
199 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
200 target_ulong arg2)
201 {
202 return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
203 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
204 }
205
206 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
207 target_ulong arg2)
208 {
209 return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
210 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
211 }
212
213 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
214 target_ulong arg2)
215 {
216 return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
217 (int64_t)(int32_t)arg2);
218 }
219
220 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
221 target_ulong arg2)
222 {
223 return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
224 (int64_t)(int32_t)arg2);
225 }
226
227 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
228 target_ulong arg2)
229 {
230 return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
231 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
232 }
233
234 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
235 target_ulong arg2)
236 {
237 return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
238 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
239 }
240
241 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
242 target_ulong arg2)
243 {
244 return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
245 }
246
247 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
248 target_ulong arg2)
249 {
250 return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
251 (uint64_t)(uint32_t)arg2);
252 }
253
254 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
255 target_ulong arg2)
256 {
257 return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
258 (int64_t)(int32_t)arg2);
259 }
260
261 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
262 target_ulong arg2)
263 {
264 return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
265 (uint64_t)(uint32_t)arg2);
266 }
267
268 #ifndef CONFIG_USER_ONLY
269
270 static inline hwaddr do_translate_address(CPUMIPSState *env,
271 target_ulong address,
272 int rw)
273 {
274 hwaddr lladdr;
275
276 lladdr = cpu_mips_translate_address(env, address, rw);
277
278 if (lladdr == -1LL) {
279 cpu_loop_exit(CPU(mips_env_get_cpu(env)));
280 } else {
281 return lladdr;
282 }
283 }
284
285 #define HELPER_LD_ATOMIC(name, insn) \
286 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
287 { \
288 env->lladdr = do_translate_address(env, arg, 0); \
289 env->llval = do_##insn(env, arg, mem_idx); \
290 return env->llval; \
291 }
292 HELPER_LD_ATOMIC(ll, lw)
293 #ifdef TARGET_MIPS64
294 HELPER_LD_ATOMIC(lld, ld)
295 #endif
296 #undef HELPER_LD_ATOMIC
297
298 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
299 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
300 target_ulong arg2, int mem_idx) \
301 { \
302 target_long tmp; \
303 \
304 if (arg2 & almask) { \
305 env->CP0_BadVAddr = arg2; \
306 helper_raise_exception(env, EXCP_AdES); \
307 } \
308 if (do_translate_address(env, arg2, 1) == env->lladdr) { \
309 tmp = do_##ld_insn(env, arg2, mem_idx); \
310 if (tmp == env->llval) { \
311 do_##st_insn(env, arg2, arg1, mem_idx); \
312 return 1; \
313 } \
314 } \
315 return 0; \
316 }
317 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
318 #ifdef TARGET_MIPS64
319 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
320 #endif
321 #undef HELPER_ST_ATOMIC
322 #endif
323
324 #ifdef TARGET_WORDS_BIGENDIAN
325 #define GET_LMASK(v) ((v) & 3)
326 #define GET_OFFSET(addr, offset) (addr + (offset))
327 #else
328 #define GET_LMASK(v) (((v) & 3) ^ 3)
329 #define GET_OFFSET(addr, offset) (addr - (offset))
330 #endif
331
332 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
333 int mem_idx)
334 {
335 do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
336
337 if (GET_LMASK(arg2) <= 2)
338 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
339
340 if (GET_LMASK(arg2) <= 1)
341 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
342
343 if (GET_LMASK(arg2) == 0)
344 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
345 }
346
347 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
348 int mem_idx)
349 {
350 do_sb(env, arg2, (uint8_t)arg1, mem_idx);
351
352 if (GET_LMASK(arg2) >= 1)
353 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
354
355 if (GET_LMASK(arg2) >= 2)
356 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
357
358 if (GET_LMASK(arg2) == 3)
359 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
360 }
361
362 #if defined(TARGET_MIPS64)
363 /* "half" load and stores. We must do the memory access inline,
364 or fault handling won't work. */
365
366 #ifdef TARGET_WORDS_BIGENDIAN
367 #define GET_LMASK64(v) ((v) & 7)
368 #else
369 #define GET_LMASK64(v) (((v) & 7) ^ 7)
370 #endif
371
372 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
373 int mem_idx)
374 {
375 do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
376
377 if (GET_LMASK64(arg2) <= 6)
378 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
379
380 if (GET_LMASK64(arg2) <= 5)
381 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
382
383 if (GET_LMASK64(arg2) <= 4)
384 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
385
386 if (GET_LMASK64(arg2) <= 3)
387 do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
388
389 if (GET_LMASK64(arg2) <= 2)
390 do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
391
392 if (GET_LMASK64(arg2) <= 1)
393 do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
394
395 if (GET_LMASK64(arg2) <= 0)
396 do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
397 }
398
399 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
400 int mem_idx)
401 {
402 do_sb(env, arg2, (uint8_t)arg1, mem_idx);
403
404 if (GET_LMASK64(arg2) >= 1)
405 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
406
407 if (GET_LMASK64(arg2) >= 2)
408 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
409
410 if (GET_LMASK64(arg2) >= 3)
411 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
412
413 if (GET_LMASK64(arg2) >= 4)
414 do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
415
416 if (GET_LMASK64(arg2) >= 5)
417 do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
418
419 if (GET_LMASK64(arg2) >= 6)
420 do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
421
422 if (GET_LMASK64(arg2) == 7)
423 do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
424 }
425 #endif /* TARGET_MIPS64 */
426
427 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
428
429 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
430 uint32_t mem_idx)
431 {
432 target_ulong base_reglist = reglist & 0xf;
433 target_ulong do_r31 = reglist & 0x10;
434
435 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
436 target_ulong i;
437
438 for (i = 0; i < base_reglist; i++) {
439 env->active_tc.gpr[multiple_regs[i]] =
440 (target_long)do_lw(env, addr, mem_idx);
441 addr += 4;
442 }
443 }
444
445 if (do_r31) {
446 env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx);
447 }
448 }
449
450 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
451 uint32_t mem_idx)
452 {
453 target_ulong base_reglist = reglist & 0xf;
454 target_ulong do_r31 = reglist & 0x10;
455
456 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
457 target_ulong i;
458
459 for (i = 0; i < base_reglist; i++) {
460 do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
461 addr += 4;
462 }
463 }
464
465 if (do_r31) {
466 do_sw(env, addr, env->active_tc.gpr[31], mem_idx);
467 }
468 }
469
470 #if defined(TARGET_MIPS64)
471 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
472 uint32_t mem_idx)
473 {
474 target_ulong base_reglist = reglist & 0xf;
475 target_ulong do_r31 = reglist & 0x10;
476
477 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
478 target_ulong i;
479
480 for (i = 0; i < base_reglist; i++) {
481 env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx);
482 addr += 8;
483 }
484 }
485
486 if (do_r31) {
487 env->active_tc.gpr[31] = do_ld(env, addr, mem_idx);
488 }
489 }
490
491 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
492 uint32_t mem_idx)
493 {
494 target_ulong base_reglist = reglist & 0xf;
495 target_ulong do_r31 = reglist & 0x10;
496
497 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
498 target_ulong i;
499
500 for (i = 0; i < base_reglist; i++) {
501 do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
502 addr += 8;
503 }
504 }
505
506 if (do_r31) {
507 do_sd(env, addr, env->active_tc.gpr[31], mem_idx);
508 }
509 }
510 #endif
511
512 #ifndef CONFIG_USER_ONLY
513 /* SMP helpers. */
514 static bool mips_vpe_is_wfi(MIPSCPU *c)
515 {
516 CPUState *cpu = CPU(c);
517 CPUMIPSState *env = &c->env;
518
519 /* If the VPE is halted but otherwise active, it means it's waiting for
520 an interrupt. */
521 return cpu->halted && mips_vpe_active(env);
522 }
523
524 static inline void mips_vpe_wake(MIPSCPU *c)
525 {
526 /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
527 because there might be other conditions that state that c should
528 be sleeping. */
529 cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
530 }
531
532 static inline void mips_vpe_sleep(MIPSCPU *cpu)
533 {
534 CPUState *cs = CPU(cpu);
535
536 /* The VPE was shut off, really go to bed.
537 Reset any old _WAKE requests. */
538 cs->halted = 1;
539 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
540 }
541
542 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
543 {
544 CPUMIPSState *c = &cpu->env;
545
546 /* FIXME: TC reschedule. */
547 if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
548 mips_vpe_wake(cpu);
549 }
550 }
551
552 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
553 {
554 CPUMIPSState *c = &cpu->env;
555
556 /* FIXME: TC reschedule. */
557 if (!mips_vpe_active(c)) {
558 mips_vpe_sleep(cpu);
559 }
560 }
561
562 /**
563 * mips_cpu_map_tc:
564 * @env: CPU from which mapping is performed.
565 * @tc: Should point to an int with the value of the global TC index.
566 *
567 * This function will transform @tc into a local index within the
568 * returned #CPUMIPSState.
569 */
570 /* FIXME: This code assumes that all VPEs have the same number of TCs,
571 which depends on runtime setup. Can probably be fixed by
572 walking the list of CPUMIPSStates. */
573 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
574 {
575 MIPSCPU *cpu;
576 CPUState *cs;
577 CPUState *other_cs;
578 int vpe_idx;
579 int tc_idx = *tc;
580
581 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
582 /* Not allowed to address other CPUs. */
583 *tc = env->current_tc;
584 return env;
585 }
586
587 cs = CPU(mips_env_get_cpu(env));
588 vpe_idx = tc_idx / cs->nr_threads;
589 *tc = tc_idx % cs->nr_threads;
590 other_cs = qemu_get_cpu(vpe_idx);
591 if (other_cs == NULL) {
592 return env;
593 }
594 cpu = MIPS_CPU(other_cs);
595 return &cpu->env;
596 }
597
598 /* The per VPE CP0_Status register shares some fields with the per TC
599 CP0_TCStatus registers. These fields are wired to the same registers,
600 so changes to either of them should be reflected on both registers.
601
602 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
603
604 These helper call synchronizes the regs for a given cpu. */
605
606 /* Called for updates to CP0_Status. */
607 static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
608 {
609 int32_t tcstatus, *tcst;
610 uint32_t v = cpu->CP0_Status;
611 uint32_t cu, mx, asid, ksu;
612 uint32_t mask = ((1 << CP0TCSt_TCU3)
613 | (1 << CP0TCSt_TCU2)
614 | (1 << CP0TCSt_TCU1)
615 | (1 << CP0TCSt_TCU0)
616 | (1 << CP0TCSt_TMX)
617 | (3 << CP0TCSt_TKSU)
618 | (0xff << CP0TCSt_TASID));
619
620 cu = (v >> CP0St_CU0) & 0xf;
621 mx = (v >> CP0St_MX) & 0x1;
622 ksu = (v >> CP0St_KSU) & 0x3;
623 asid = env->CP0_EntryHi & 0xff;
624
625 tcstatus = cu << CP0TCSt_TCU0;
626 tcstatus |= mx << CP0TCSt_TMX;
627 tcstatus |= ksu << CP0TCSt_TKSU;
628 tcstatus |= asid;
629
630 if (tc == cpu->current_tc) {
631 tcst = &cpu->active_tc.CP0_TCStatus;
632 } else {
633 tcst = &cpu->tcs[tc].CP0_TCStatus;
634 }
635
636 *tcst &= ~mask;
637 *tcst |= tcstatus;
638 compute_hflags(cpu);
639 }
640
641 /* Called for updates to CP0_TCStatus. */
642 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
643 target_ulong v)
644 {
645 uint32_t status;
646 uint32_t tcu, tmx, tasid, tksu;
647 uint32_t mask = ((1U << CP0St_CU3)
648 | (1 << CP0St_CU2)
649 | (1 << CP0St_CU1)
650 | (1 << CP0St_CU0)
651 | (1 << CP0St_MX)
652 | (3 << CP0St_KSU));
653
654 tcu = (v >> CP0TCSt_TCU0) & 0xf;
655 tmx = (v >> CP0TCSt_TMX) & 0x1;
656 tasid = v & 0xff;
657 tksu = (v >> CP0TCSt_TKSU) & 0x3;
658
659 status = tcu << CP0St_CU0;
660 status |= tmx << CP0St_MX;
661 status |= tksu << CP0St_KSU;
662
663 cpu->CP0_Status &= ~mask;
664 cpu->CP0_Status |= status;
665
666 /* Sync the TASID with EntryHi. */
667 cpu->CP0_EntryHi &= ~0xff;
668 cpu->CP0_EntryHi = tasid;
669
670 compute_hflags(cpu);
671 }
672
673 /* Called for updates to CP0_EntryHi. */
674 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
675 {
676 int32_t *tcst;
677 uint32_t asid, v = cpu->CP0_EntryHi;
678
679 asid = v & 0xff;
680
681 if (tc == cpu->current_tc) {
682 tcst = &cpu->active_tc.CP0_TCStatus;
683 } else {
684 tcst = &cpu->tcs[tc].CP0_TCStatus;
685 }
686
687 *tcst &= ~0xff;
688 *tcst |= asid;
689 }
690
691 /* CP0 helpers */
692 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
693 {
694 return env->mvp->CP0_MVPControl;
695 }
696
697 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
698 {
699 return env->mvp->CP0_MVPConf0;
700 }
701
702 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
703 {
704 return env->mvp->CP0_MVPConf1;
705 }
706
707 target_ulong helper_mfc0_random(CPUMIPSState *env)
708 {
709 return (int32_t)cpu_mips_get_random(env);
710 }
711
712 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
713 {
714 return env->active_tc.CP0_TCStatus;
715 }
716
717 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
718 {
719 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
720 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
721
722 if (other_tc == other->current_tc)
723 return other->active_tc.CP0_TCStatus;
724 else
725 return other->tcs[other_tc].CP0_TCStatus;
726 }
727
728 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
729 {
730 return env->active_tc.CP0_TCBind;
731 }
732
733 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
734 {
735 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
736 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
737
738 if (other_tc == other->current_tc)
739 return other->active_tc.CP0_TCBind;
740 else
741 return other->tcs[other_tc].CP0_TCBind;
742 }
743
744 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
745 {
746 return env->active_tc.PC;
747 }
748
749 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
750 {
751 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
752 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
753
754 if (other_tc == other->current_tc)
755 return other->active_tc.PC;
756 else
757 return other->tcs[other_tc].PC;
758 }
759
760 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
761 {
762 return env->active_tc.CP0_TCHalt;
763 }
764
765 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
766 {
767 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
768 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
769
770 if (other_tc == other->current_tc)
771 return other->active_tc.CP0_TCHalt;
772 else
773 return other->tcs[other_tc].CP0_TCHalt;
774 }
775
776 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
777 {
778 return env->active_tc.CP0_TCContext;
779 }
780
781 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
782 {
783 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
784 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
785
786 if (other_tc == other->current_tc)
787 return other->active_tc.CP0_TCContext;
788 else
789 return other->tcs[other_tc].CP0_TCContext;
790 }
791
792 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
793 {
794 return env->active_tc.CP0_TCSchedule;
795 }
796
797 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
798 {
799 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
800 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
801
802 if (other_tc == other->current_tc)
803 return other->active_tc.CP0_TCSchedule;
804 else
805 return other->tcs[other_tc].CP0_TCSchedule;
806 }
807
808 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
809 {
810 return env->active_tc.CP0_TCScheFBack;
811 }
812
813 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
814 {
815 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
816 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
817
818 if (other_tc == other->current_tc)
819 return other->active_tc.CP0_TCScheFBack;
820 else
821 return other->tcs[other_tc].CP0_TCScheFBack;
822 }
823
824 target_ulong helper_mfc0_count(CPUMIPSState *env)
825 {
826 return (int32_t)cpu_mips_get_count(env);
827 }
828
829 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
830 {
831 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
832 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
833
834 return other->CP0_EntryHi;
835 }
836
837 target_ulong helper_mftc0_cause(CPUMIPSState *env)
838 {
839 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
840 int32_t tccause;
841 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
842
843 if (other_tc == other->current_tc) {
844 tccause = other->CP0_Cause;
845 } else {
846 tccause = other->CP0_Cause;
847 }
848
849 return tccause;
850 }
851
852 target_ulong helper_mftc0_status(CPUMIPSState *env)
853 {
854 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
855 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
856
857 return other->CP0_Status;
858 }
859
860 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
861 {
862 return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
863 }
864
865 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
866 {
867 return (int32_t)env->CP0_WatchLo[sel];
868 }
869
870 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
871 {
872 return env->CP0_WatchHi[sel];
873 }
874
875 target_ulong helper_mfc0_debug(CPUMIPSState *env)
876 {
877 target_ulong t0 = env->CP0_Debug;
878 if (env->hflags & MIPS_HFLAG_DM)
879 t0 |= 1 << CP0DB_DM;
880
881 return t0;
882 }
883
884 target_ulong helper_mftc0_debug(CPUMIPSState *env)
885 {
886 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
887 int32_t tcstatus;
888 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
889
890 if (other_tc == other->current_tc)
891 tcstatus = other->active_tc.CP0_Debug_tcstatus;
892 else
893 tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
894
895 /* XXX: Might be wrong, check with EJTAG spec. */
896 return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
897 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
898 }
899
900 #if defined(TARGET_MIPS64)
901 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
902 {
903 return env->active_tc.PC;
904 }
905
906 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
907 {
908 return env->active_tc.CP0_TCHalt;
909 }
910
911 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
912 {
913 return env->active_tc.CP0_TCContext;
914 }
915
916 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
917 {
918 return env->active_tc.CP0_TCSchedule;
919 }
920
921 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
922 {
923 return env->active_tc.CP0_TCScheFBack;
924 }
925
926 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
927 {
928 return env->lladdr >> env->CP0_LLAddr_shift;
929 }
930
931 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
932 {
933 return env->CP0_WatchLo[sel];
934 }
935 #endif /* TARGET_MIPS64 */
936
937 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
938 {
939 int num = 1;
940 unsigned int tmp = env->tlb->nb_tlb;
941
942 do {
943 tmp >>= 1;
944 num <<= 1;
945 } while (tmp);
946 env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
947 }
948
949 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
950 {
951 uint32_t mask = 0;
952 uint32_t newval;
953
954 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
955 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
956 (1 << CP0MVPCo_EVP);
957 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
958 mask |= (1 << CP0MVPCo_STLB);
959 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
960
961 // TODO: Enable/disable shared TLB, enable/disable VPEs.
962
963 env->mvp->CP0_MVPControl = newval;
964 }
965
966 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
967 {
968 uint32_t mask;
969 uint32_t newval;
970
971 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
972 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
973 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
974
975 /* Yield scheduler intercept not implemented. */
976 /* Gating storage scheduler intercept not implemented. */
977
978 // TODO: Enable/disable TCs.
979
980 env->CP0_VPEControl = newval;
981 }
982
983 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
984 {
985 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
986 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
987 uint32_t mask;
988 uint32_t newval;
989
990 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
991 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
992 newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
993
994 /* TODO: Enable/disable TCs. */
995
996 other->CP0_VPEControl = newval;
997 }
998
999 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1000 {
1001 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1002 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1003 /* FIXME: Mask away return zero on read bits. */
1004 return other->CP0_VPEControl;
1005 }
1006
1007 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1008 {
1009 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1010 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1011
1012 return other->CP0_VPEConf0;
1013 }
1014
1015 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1016 {
1017 uint32_t mask = 0;
1018 uint32_t newval;
1019
1020 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1021 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1022 mask |= (0xff << CP0VPEC0_XTC);
1023 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1024 }
1025 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1026
1027 // TODO: TC exclusive handling due to ERL/EXL.
1028
1029 env->CP0_VPEConf0 = newval;
1030 }
1031
1032 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1033 {
1034 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1035 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1036 uint32_t mask = 0;
1037 uint32_t newval;
1038
1039 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1040 newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1041
1042 /* TODO: TC exclusive handling due to ERL/EXL. */
1043 other->CP0_VPEConf0 = newval;
1044 }
1045
1046 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1047 {
1048 uint32_t mask = 0;
1049 uint32_t newval;
1050
1051 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1052 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1053 (0xff << CP0VPEC1_NCP1);
1054 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1055
1056 /* UDI not implemented. */
1057 /* CP2 not implemented. */
1058
1059 // TODO: Handle FPU (CP1) binding.
1060
1061 env->CP0_VPEConf1 = newval;
1062 }
1063
1064 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1065 {
1066 /* Yield qualifier inputs not implemented. */
1067 env->CP0_YQMask = 0x00000000;
1068 }
1069
1070 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1071 {
1072 env->CP0_VPEOpt = arg1 & 0x0000ffff;
1073 }
1074
1075 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1076 {
1077 /* Large physaddr (PABITS) not implemented */
1078 /* 1k pages not implemented */
1079 env->CP0_EntryLo0 = arg1 & 0x3FFFFFFF;
1080 }
1081
1082 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1083 {
1084 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1085 uint32_t newval;
1086
1087 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1088
1089 env->active_tc.CP0_TCStatus = newval;
1090 sync_c0_tcstatus(env, env->current_tc, newval);
1091 }
1092
1093 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1094 {
1095 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1096 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1097
1098 if (other_tc == other->current_tc)
1099 other->active_tc.CP0_TCStatus = arg1;
1100 else
1101 other->tcs[other_tc].CP0_TCStatus = arg1;
1102 sync_c0_tcstatus(other, other_tc, arg1);
1103 }
1104
1105 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1106 {
1107 uint32_t mask = (1 << CP0TCBd_TBE);
1108 uint32_t newval;
1109
1110 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1111 mask |= (1 << CP0TCBd_CurVPE);
1112 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1113 env->active_tc.CP0_TCBind = newval;
1114 }
1115
1116 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1117 {
1118 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1119 uint32_t mask = (1 << CP0TCBd_TBE);
1120 uint32_t newval;
1121 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1122
1123 if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1124 mask |= (1 << CP0TCBd_CurVPE);
1125 if (other_tc == other->current_tc) {
1126 newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1127 other->active_tc.CP0_TCBind = newval;
1128 } else {
1129 newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1130 other->tcs[other_tc].CP0_TCBind = newval;
1131 }
1132 }
1133
1134 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1135 {
1136 env->active_tc.PC = arg1;
1137 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1138 env->lladdr = 0ULL;
1139 /* MIPS16 not implemented. */
1140 }
1141
1142 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1143 {
1144 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1145 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1146
1147 if (other_tc == other->current_tc) {
1148 other->active_tc.PC = arg1;
1149 other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1150 other->lladdr = 0ULL;
1151 /* MIPS16 not implemented. */
1152 } else {
1153 other->tcs[other_tc].PC = arg1;
1154 other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1155 other->lladdr = 0ULL;
1156 /* MIPS16 not implemented. */
1157 }
1158 }
1159
1160 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1161 {
1162 MIPSCPU *cpu = mips_env_get_cpu(env);
1163
1164 env->active_tc.CP0_TCHalt = arg1 & 0x1;
1165
1166 // TODO: Halt TC / Restart (if allocated+active) TC.
1167 if (env->active_tc.CP0_TCHalt & 1) {
1168 mips_tc_sleep(cpu, env->current_tc);
1169 } else {
1170 mips_tc_wake(cpu, env->current_tc);
1171 }
1172 }
1173
1174 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1175 {
1176 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1177 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1178 MIPSCPU *other_cpu = mips_env_get_cpu(other);
1179
1180 // TODO: Halt TC / Restart (if allocated+active) TC.
1181
1182 if (other_tc == other->current_tc)
1183 other->active_tc.CP0_TCHalt = arg1;
1184 else
1185 other->tcs[other_tc].CP0_TCHalt = arg1;
1186
1187 if (arg1 & 1) {
1188 mips_tc_sleep(other_cpu, other_tc);
1189 } else {
1190 mips_tc_wake(other_cpu, other_tc);
1191 }
1192 }
1193
1194 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1195 {
1196 env->active_tc.CP0_TCContext = arg1;
1197 }
1198
1199 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1200 {
1201 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1202 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1203
1204 if (other_tc == other->current_tc)
1205 other->active_tc.CP0_TCContext = arg1;
1206 else
1207 other->tcs[other_tc].CP0_TCContext = arg1;
1208 }
1209
1210 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1211 {
1212 env->active_tc.CP0_TCSchedule = arg1;
1213 }
1214
1215 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1216 {
1217 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1218 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1219
1220 if (other_tc == other->current_tc)
1221 other->active_tc.CP0_TCSchedule = arg1;
1222 else
1223 other->tcs[other_tc].CP0_TCSchedule = arg1;
1224 }
1225
1226 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1227 {
1228 env->active_tc.CP0_TCScheFBack = arg1;
1229 }
1230
1231 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1232 {
1233 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1234 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1235
1236 if (other_tc == other->current_tc)
1237 other->active_tc.CP0_TCScheFBack = arg1;
1238 else
1239 other->tcs[other_tc].CP0_TCScheFBack = arg1;
1240 }
1241
1242 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1243 {
1244 /* Large physaddr (PABITS) not implemented */
1245 /* 1k pages not implemented */
1246 env->CP0_EntryLo1 = arg1 & 0x3FFFFFFF;
1247 }
1248
1249 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1250 {
1251 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1252 }
1253
1254 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1255 {
1256 /* 1k pages not implemented */
1257 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1258 }
1259
1260 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1261 {
1262 /* SmartMIPS not implemented */
1263 /* Large physaddr (PABITS) not implemented */
1264 /* 1k pages not implemented */
1265 env->CP0_PageGrain = 0;
1266 }
1267
1268 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1269 {
1270 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1271 }
1272
1273 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1274 {
1275 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1276 }
1277
1278 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1279 {
1280 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1281 }
1282
1283 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1284 {
1285 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1286 }
1287
1288 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1289 {
1290 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1291 }
1292
1293 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1294 {
1295 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1296 }
1297
1298 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1299 {
1300 uint32_t mask = 0x0000000F;
1301
1302 if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1303 mask |= (1 << 29);
1304
1305 if (arg1 & (1 << 29)) {
1306 env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1307 } else {
1308 env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1309 }
1310 }
1311
1312 env->CP0_HWREna = arg1 & mask;
1313 }
1314
1315 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1316 {
1317 cpu_mips_store_count(env, arg1);
1318 }
1319
1320 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1321 {
1322 target_ulong old, val;
1323
1324 /* 1k pages not implemented */
1325 val = arg1 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1326 #if defined(TARGET_MIPS64)
1327 val &= env->SEGMask;
1328 #endif
1329 old = env->CP0_EntryHi;
1330 env->CP0_EntryHi = val;
1331 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1332 sync_c0_entryhi(env, env->current_tc);
1333 }
1334 /* If the ASID changes, flush qemu's TLB. */
1335 if ((old & 0xFF) != (val & 0xFF))
1336 cpu_mips_tlb_flush(env, 1);
1337 }
1338
1339 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1340 {
1341 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1342 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1343
1344 other->CP0_EntryHi = arg1;
1345 sync_c0_entryhi(other, other_tc);
1346 }
1347
1348 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1349 {
1350 cpu_mips_store_compare(env, arg1);
1351 }
1352
1353 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1354 {
1355 MIPSCPU *cpu = mips_env_get_cpu(env);
1356 uint32_t val, old;
1357 uint32_t mask = env->CP0_Status_rw_bitmask;
1358
1359 val = arg1 & mask;
1360 old = env->CP0_Status;
1361 env->CP0_Status = (env->CP0_Status & ~mask) | val;
1362 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1363 sync_c0_status(env, env, env->current_tc);
1364 } else {
1365 compute_hflags(env);
1366 }
1367
1368 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1369 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1370 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1371 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1372 env->CP0_Cause);
1373 switch (env->hflags & MIPS_HFLAG_KSU) {
1374 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1375 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1376 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1377 default:
1378 cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1379 break;
1380 }
1381 }
1382 }
1383
1384 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1385 {
1386 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1387 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1388
1389 other->CP0_Status = arg1 & ~0xf1000018;
1390 sync_c0_status(env, other, other_tc);
1391 }
1392
1393 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1394 {
1395 /* vectored interrupts not implemented, no performance counters. */
1396 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1397 }
1398
1399 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1400 {
1401 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1402 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1403 }
1404
1405 static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1)
1406 {
1407 uint32_t mask = 0x00C00300;
1408 uint32_t old = cpu->CP0_Cause;
1409 int i;
1410
1411 if (cpu->insn_flags & ISA_MIPS32R2) {
1412 mask |= 1 << CP0Ca_DC;
1413 mask |= 1 << CP0Ca_PCI;
1414 }
1415
1416 cpu->CP0_Cause = (cpu->CP0_Cause & ~mask) | (arg1 & mask);
1417
1418 if ((old ^ cpu->CP0_Cause) & (1 << CP0Ca_DC)) {
1419 if (cpu->CP0_Cause & (1 << CP0Ca_DC)) {
1420 cpu_mips_stop_count(cpu);
1421 } else {
1422 cpu_mips_start_count(cpu);
1423 }
1424 }
1425
1426 /* Set/reset software interrupts */
1427 for (i = 0 ; i < 2 ; i++) {
1428 if ((old ^ cpu->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
1429 cpu_mips_soft_irq(cpu, i, cpu->CP0_Cause & (1 << (CP0Ca_IP + i)));
1430 }
1431 }
1432 }
1433
1434 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1435 {
1436 mtc0_cause(env, arg1);
1437 }
1438
1439 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1440 {
1441 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1442 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1443
1444 mtc0_cause(other, arg1);
1445 }
1446
1447 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1448 {
1449 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1450 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1451
1452 return other->CP0_EPC;
1453 }
1454
1455 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1456 {
1457 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1458 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1459
1460 return other->CP0_EBase;
1461 }
1462
1463 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1464 {
1465 /* vectored interrupts not implemented */
1466 env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1467 }
1468
1469 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1470 {
1471 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1472 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1473 other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1474 }
1475
1476 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1477 {
1478 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1479 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1480
1481 switch (idx) {
1482 case 0: return other->CP0_Config0;
1483 case 1: return other->CP0_Config1;
1484 case 2: return other->CP0_Config2;
1485 case 3: return other->CP0_Config3;
1486 /* 4 and 5 are reserved. */
1487 case 6: return other->CP0_Config6;
1488 case 7: return other->CP0_Config7;
1489 default:
1490 break;
1491 }
1492 return 0;
1493 }
1494
1495 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1496 {
1497 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1498 }
1499
1500 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1501 {
1502 /* tertiary/secondary caches not implemented */
1503 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1504 }
1505
1506 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1507 {
1508 env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1509 (arg1 & env->CP0_Config4_rw_bitmask);
1510 }
1511
1512 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1513 {
1514 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1515 (arg1 & env->CP0_Config5_rw_bitmask);
1516 }
1517
1518 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1519 {
1520 target_long mask = env->CP0_LLAddr_rw_bitmask;
1521 arg1 = arg1 << env->CP0_LLAddr_shift;
1522 env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1523 }
1524
1525 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1526 {
1527 /* Watch exceptions for instructions, data loads, data stores
1528 not implemented. */
1529 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1530 }
1531
1532 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1533 {
1534 env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1535 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1536 }
1537
1538 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1539 {
1540 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1541 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1542 }
1543
1544 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1545 {
1546 env->CP0_Framemask = arg1; /* XXX */
1547 }
1548
1549 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1550 {
1551 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1552 if (arg1 & (1 << CP0DB_DM))
1553 env->hflags |= MIPS_HFLAG_DM;
1554 else
1555 env->hflags &= ~MIPS_HFLAG_DM;
1556 }
1557
1558 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1559 {
1560 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1561 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1562 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1563
1564 /* XXX: Might be wrong, check with EJTAG spec. */
1565 if (other_tc == other->current_tc)
1566 other->active_tc.CP0_Debug_tcstatus = val;
1567 else
1568 other->tcs[other_tc].CP0_Debug_tcstatus = val;
1569 other->CP0_Debug = (other->CP0_Debug &
1570 ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1571 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1572 }
1573
1574 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1575 {
1576 env->CP0_Performance0 = arg1 & 0x000007ff;
1577 }
1578
1579 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1580 {
1581 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1582 }
1583
1584 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1585 {
1586 env->CP0_DataLo = arg1; /* XXX */
1587 }
1588
1589 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1590 {
1591 env->CP0_TagHi = arg1; /* XXX */
1592 }
1593
1594 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1595 {
1596 env->CP0_DataHi = arg1; /* XXX */
1597 }
1598
1599 /* MIPS MT functions */
1600 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1601 {
1602 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1603 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1604
1605 if (other_tc == other->current_tc)
1606 return other->active_tc.gpr[sel];
1607 else
1608 return other->tcs[other_tc].gpr[sel];
1609 }
1610
1611 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1612 {
1613 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1614 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1615
1616 if (other_tc == other->current_tc)
1617 return other->active_tc.LO[sel];
1618 else
1619 return other->tcs[other_tc].LO[sel];
1620 }
1621
1622 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1623 {
1624 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1625 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1626
1627 if (other_tc == other->current_tc)
1628 return other->active_tc.HI[sel];
1629 else
1630 return other->tcs[other_tc].HI[sel];
1631 }
1632
1633 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1634 {
1635 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1636 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1637
1638 if (other_tc == other->current_tc)
1639 return other->active_tc.ACX[sel];
1640 else
1641 return other->tcs[other_tc].ACX[sel];
1642 }
1643
1644 target_ulong helper_mftdsp(CPUMIPSState *env)
1645 {
1646 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1647 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1648
1649 if (other_tc == other->current_tc)
1650 return other->active_tc.DSPControl;
1651 else
1652 return other->tcs[other_tc].DSPControl;
1653 }
1654
1655 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1656 {
1657 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1658 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1659
1660 if (other_tc == other->current_tc)
1661 other->active_tc.gpr[sel] = arg1;
1662 else
1663 other->tcs[other_tc].gpr[sel] = arg1;
1664 }
1665
1666 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1667 {
1668 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1669 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1670
1671 if (other_tc == other->current_tc)
1672 other->active_tc.LO[sel] = arg1;
1673 else
1674 other->tcs[other_tc].LO[sel] = arg1;
1675 }
1676
1677 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1678 {
1679 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1680 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1681
1682 if (other_tc == other->current_tc)
1683 other->active_tc.HI[sel] = arg1;
1684 else
1685 other->tcs[other_tc].HI[sel] = arg1;
1686 }
1687
1688 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1689 {
1690 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1691 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1692
1693 if (other_tc == other->current_tc)
1694 other->active_tc.ACX[sel] = arg1;
1695 else
1696 other->tcs[other_tc].ACX[sel] = arg1;
1697 }
1698
1699 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1700 {
1701 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1702 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1703
1704 if (other_tc == other->current_tc)
1705 other->active_tc.DSPControl = arg1;
1706 else
1707 other->tcs[other_tc].DSPControl = arg1;
1708 }
1709
1710 /* MIPS MT functions */
1711 target_ulong helper_dmt(void)
1712 {
1713 // TODO
1714 return 0;
1715 }
1716
1717 target_ulong helper_emt(void)
1718 {
1719 // TODO
1720 return 0;
1721 }
1722
1723 target_ulong helper_dvpe(CPUMIPSState *env)
1724 {
1725 CPUState *other_cs = first_cpu;
1726 target_ulong prev = env->mvp->CP0_MVPControl;
1727
1728 CPU_FOREACH(other_cs) {
1729 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1730 /* Turn off all VPEs except the one executing the dvpe. */
1731 if (&other_cpu->env != env) {
1732 other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1733 mips_vpe_sleep(other_cpu);
1734 }
1735 }
1736 return prev;
1737 }
1738
1739 target_ulong helper_evpe(CPUMIPSState *env)
1740 {
1741 CPUState *other_cs = first_cpu;
1742 target_ulong prev = env->mvp->CP0_MVPControl;
1743
1744 CPU_FOREACH(other_cs) {
1745 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1746
1747 if (&other_cpu->env != env
1748 /* If the VPE is WFI, don't disturb its sleep. */
1749 && !mips_vpe_is_wfi(other_cpu)) {
1750 /* Enable the VPE. */
1751 other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1752 mips_vpe_wake(other_cpu); /* And wake it up. */
1753 }
1754 }
1755 return prev;
1756 }
1757 #endif /* !CONFIG_USER_ONLY */
1758
1759 void helper_fork(target_ulong arg1, target_ulong arg2)
1760 {
1761 fprintf(stderr, "%s:%u - %s\n", __FILE__, __LINE__, __func__);
1762 // arg1 = rt, arg2 = rs
1763 // TODO: store to TC register, assert to detect test cases.
1764 g_assert_not_reached();
1765 }
1766
1767 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1768 {
1769 target_long arg1 = arg;
1770
1771 if (arg1 < 0) {
1772 /* No scheduling policy implemented. */
1773 if (arg1 != -2) {
1774 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1775 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1776 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1777 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1778 helper_raise_exception(env, EXCP_THREAD);
1779 }
1780 }
1781 } else if (arg1 == 0) {
1782 if (0 /* TODO: TC underflow */) {
1783 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1784 helper_raise_exception(env, EXCP_THREAD);
1785 } else {
1786 // TODO: Deallocate TC
1787 }
1788 } else if (arg1 > 0) {
1789 /* Yield qualifier inputs not implemented. */
1790 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1791 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1792 helper_raise_exception(env, EXCP_THREAD);
1793 }
1794 return env->CP0_YQMask;
1795 }
1796
1797 #ifndef CONFIG_USER_ONLY
1798 /* TLB management */
1799 static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1800 {
1801 MIPSCPU *cpu = mips_env_get_cpu(env);
1802
1803 /* Flush qemu's TLB and discard all shadowed entries. */
1804 tlb_flush(CPU(cpu), flush_global);
1805 env->tlb->tlb_in_use = env->tlb->nb_tlb;
1806 }
1807
1808 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1809 {
1810 /* Discard entries from env->tlb[first] onwards. */
1811 while (env->tlb->tlb_in_use > first) {
1812 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1813 }
1814 }
1815
1816 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1817 {
1818 r4k_tlb_t *tlb;
1819
1820 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1821 tlb = &env->tlb->mmu.r4k.tlb[idx];
1822 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1823 #if defined(TARGET_MIPS64)
1824 tlb->VPN &= env->SEGMask;
1825 #endif
1826 tlb->ASID = env->CP0_EntryHi & 0xFF;
1827 tlb->PageMask = env->CP0_PageMask;
1828 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1829 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1830 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1831 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1832 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1833 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1834 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1835 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1836 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1837 }
1838
1839 void r4k_helper_tlbwi(CPUMIPSState *env)
1840 {
1841 r4k_tlb_t *tlb;
1842 int idx;
1843 target_ulong VPN;
1844 uint8_t ASID;
1845 bool G, V0, D0, V1, D1;
1846
1847 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1848 tlb = &env->tlb->mmu.r4k.tlb[idx];
1849 VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1850 #if defined(TARGET_MIPS64)
1851 VPN &= env->SEGMask;
1852 #endif
1853 ASID = env->CP0_EntryHi & 0xff;
1854 G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1855 V0 = (env->CP0_EntryLo0 & 2) != 0;
1856 D0 = (env->CP0_EntryLo0 & 4) != 0;
1857 V1 = (env->CP0_EntryLo1 & 2) != 0;
1858 D1 = (env->CP0_EntryLo1 & 4) != 0;
1859
1860 /* Discard cached TLB entries, unless tlbwi is just upgrading access
1861 permissions on the current entry. */
1862 if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
1863 (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
1864 (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
1865 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1866 }
1867
1868 r4k_invalidate_tlb(env, idx, 0);
1869 r4k_fill_tlb(env, idx);
1870 }
1871
1872 void r4k_helper_tlbwr(CPUMIPSState *env)
1873 {
1874 int r = cpu_mips_get_random(env);
1875
1876 r4k_invalidate_tlb(env, r, 1);
1877 r4k_fill_tlb(env, r);
1878 }
1879
1880 void r4k_helper_tlbp(CPUMIPSState *env)
1881 {
1882 r4k_tlb_t *tlb;
1883 target_ulong mask;
1884 target_ulong tag;
1885 target_ulong VPN;
1886 uint8_t ASID;
1887 int i;
1888
1889 ASID = env->CP0_EntryHi & 0xFF;
1890 for (i = 0; i < env->tlb->nb_tlb; i++) {
1891 tlb = &env->tlb->mmu.r4k.tlb[i];
1892 /* 1k pages are not supported. */
1893 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1894 tag = env->CP0_EntryHi & ~mask;
1895 VPN = tlb->VPN & ~mask;
1896 #if defined(TARGET_MIPS64)
1897 tag &= env->SEGMask;
1898 #endif
1899 /* Check ASID, virtual page number & size */
1900 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1901 /* TLB match */
1902 env->CP0_Index = i;
1903 break;
1904 }
1905 }
1906 if (i == env->tlb->nb_tlb) {
1907 /* No match. Discard any shadow entries, if any of them match. */
1908 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1909 tlb = &env->tlb->mmu.r4k.tlb[i];
1910 /* 1k pages are not supported. */
1911 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1912 tag = env->CP0_EntryHi & ~mask;
1913 VPN = tlb->VPN & ~mask;
1914 #if defined(TARGET_MIPS64)
1915 tag &= env->SEGMask;
1916 #endif
1917 /* Check ASID, virtual page number & size */
1918 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1919 r4k_mips_tlb_flush_extra (env, i);
1920 break;
1921 }
1922 }
1923
1924 env->CP0_Index |= 0x80000000;
1925 }
1926 }
1927
1928 void r4k_helper_tlbr(CPUMIPSState *env)
1929 {
1930 r4k_tlb_t *tlb;
1931 uint8_t ASID;
1932 int idx;
1933
1934 ASID = env->CP0_EntryHi & 0xFF;
1935 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1936 tlb = &env->tlb->mmu.r4k.tlb[idx];
1937
1938 /* If this will change the current ASID, flush qemu's TLB. */
1939 if (ASID != tlb->ASID)
1940 cpu_mips_tlb_flush (env, 1);
1941
1942 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1943
1944 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
1945 env->CP0_PageMask = tlb->PageMask;
1946 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1947 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1948 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1949 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
1950 }
1951
1952 void helper_tlbwi(CPUMIPSState *env)
1953 {
1954 env->tlb->helper_tlbwi(env);
1955 }
1956
1957 void helper_tlbwr(CPUMIPSState *env)
1958 {
1959 env->tlb->helper_tlbwr(env);
1960 }
1961
1962 void helper_tlbp(CPUMIPSState *env)
1963 {
1964 env->tlb->helper_tlbp(env);
1965 }
1966
1967 void helper_tlbr(CPUMIPSState *env)
1968 {
1969 env->tlb->helper_tlbr(env);
1970 }
1971
1972 /* Specials */
1973 target_ulong helper_di(CPUMIPSState *env)
1974 {
1975 target_ulong t0 = env->CP0_Status;
1976
1977 env->CP0_Status = t0 & ~(1 << CP0St_IE);
1978 return t0;
1979 }
1980
1981 target_ulong helper_ei(CPUMIPSState *env)
1982 {
1983 target_ulong t0 = env->CP0_Status;
1984
1985 env->CP0_Status = t0 | (1 << CP0St_IE);
1986 return t0;
1987 }
1988
1989 static void debug_pre_eret(CPUMIPSState *env)
1990 {
1991 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1992 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1993 env->active_tc.PC, env->CP0_EPC);
1994 if (env->CP0_Status & (1 << CP0St_ERL))
1995 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1996 if (env->hflags & MIPS_HFLAG_DM)
1997 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1998 qemu_log("\n");
1999 }
2000 }
2001
2002 static void debug_post_eret(CPUMIPSState *env)
2003 {
2004 MIPSCPU *cpu = mips_env_get_cpu(env);
2005
2006 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2007 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2008 env->active_tc.PC, env->CP0_EPC);
2009 if (env->CP0_Status & (1 << CP0St_ERL))
2010 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2011 if (env->hflags & MIPS_HFLAG_DM)
2012 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2013 switch (env->hflags & MIPS_HFLAG_KSU) {
2014 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2015 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2016 case MIPS_HFLAG_KM: qemu_log("\n"); break;
2017 default:
2018 cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2019 break;
2020 }
2021 }
2022 }
2023
2024 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2025 {
2026 env->active_tc.PC = error_pc & ~(target_ulong)1;
2027 if (error_pc & 1) {
2028 env->hflags |= MIPS_HFLAG_M16;
2029 } else {
2030 env->hflags &= ~(MIPS_HFLAG_M16);
2031 }
2032 }
2033
2034 void helper_eret(CPUMIPSState *env)
2035 {
2036 debug_pre_eret(env);
2037 if (env->CP0_Status & (1 << CP0St_ERL)) {
2038 set_pc(env, env->CP0_ErrorEPC);
2039 env->CP0_Status &= ~(1 << CP0St_ERL);
2040 } else {
2041 set_pc(env, env->CP0_EPC);
2042 env->CP0_Status &= ~(1 << CP0St_EXL);
2043 }
2044 compute_hflags(env);
2045 debug_post_eret(env);
2046 env->lladdr = 1;
2047 }
2048
2049 void helper_deret(CPUMIPSState *env)
2050 {
2051 debug_pre_eret(env);
2052 set_pc(env, env->CP0_DEPC);
2053
2054 env->hflags &= MIPS_HFLAG_DM;
2055 compute_hflags(env);
2056 debug_post_eret(env);
2057 env->lladdr = 1;
2058 }
2059 #endif /* !CONFIG_USER_ONLY */
2060
2061 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2062 {
2063 if ((env->hflags & MIPS_HFLAG_CP0) ||
2064 (env->CP0_HWREna & (1 << 0)))
2065 return env->CP0_EBase & 0x3ff;
2066 else
2067 helper_raise_exception(env, EXCP_RI);
2068
2069 return 0;
2070 }
2071
2072 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2073 {
2074 if ((env->hflags & MIPS_HFLAG_CP0) ||
2075 (env->CP0_HWREna & (1 << 1)))
2076 return env->SYNCI_Step;
2077 else
2078 helper_raise_exception(env, EXCP_RI);
2079
2080 return 0;
2081 }
2082
2083 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2084 {
2085 if ((env->hflags & MIPS_HFLAG_CP0) ||
2086 (env->CP0_HWREna & (1 << 2)))
2087 return env->CP0_Count;
2088 else
2089 helper_raise_exception(env, EXCP_RI);
2090
2091 return 0;
2092 }
2093
2094 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2095 {
2096 if ((env->hflags & MIPS_HFLAG_CP0) ||
2097 (env->CP0_HWREna & (1 << 3)))
2098 return env->CCRes;
2099 else
2100 helper_raise_exception(env, EXCP_RI);
2101
2102 return 0;
2103 }
2104
2105 void helper_pmon(CPUMIPSState *env, int function)
2106 {
2107 function /= 2;
2108 switch (function) {
2109 case 2: /* TODO: char inbyte(int waitflag); */
2110 if (env->active_tc.gpr[4] == 0)
2111 env->active_tc.gpr[2] = -1;
2112 /* Fall through */
2113 case 11: /* TODO: char inbyte (void); */
2114 env->active_tc.gpr[2] = -1;
2115 break;
2116 case 3:
2117 case 12:
2118 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2119 break;
2120 case 17:
2121 break;
2122 #ifndef CONFIG_USER_ONLY
2123 case 158:
2124 {
2125 unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2126 printf("%s", fmt);
2127 }
2128 break;
2129 #endif
2130 }
2131 }
2132
2133 void QEMU_NORETURN helper_wait(CPUMIPSState *env)
2134 {
2135 CPUState *cs = CPU(mips_env_get_cpu(env));
2136
2137 cs->halted = 1;
2138 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2139 helper_raise_exception(env, EXCP_HLT);
2140 }
2141
2142 #if !defined(CONFIG_USER_ONLY)
2143
2144 void QEMU_NORETURN mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2145 int is_write, int is_user, uintptr_t retaddr)
2146 {
2147 MIPSCPU *cpu = MIPS_CPU(cs);
2148 CPUMIPSState *env = &cpu->env;
2149
2150 env->CP0_BadVAddr = addr;
2151 do_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL, retaddr);
2152 }
2153
2154 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
2155 uintptr_t retaddr)
2156 {
2157 int ret;
2158
2159 ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
2160 if (ret) {
2161 MIPSCPU *cpu = MIPS_CPU(cs);
2162 CPUMIPSState *env = &cpu->env;
2163
2164 do_raise_exception_err(env, cs->exception_index,
2165 env->error_code, retaddr);
2166 }
2167 }
2168
2169 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2170 bool is_write, bool is_exec, int unused,
2171 unsigned size)
2172 {
2173 MIPSCPU *cpu = MIPS_CPU(cs);
2174 CPUMIPSState *env = &cpu->env;
2175
2176 if (is_exec) {
2177 helper_raise_exception(env, EXCP_IBE);
2178 } else {
2179 helper_raise_exception(env, EXCP_DBE);
2180 }
2181 }
2182 #endif /* !CONFIG_USER_ONLY */
2183
2184 /* Complex FPU operations which may need stack space. */
2185
2186 #define FLOAT_TWO32 make_float32(1 << 30)
2187 #define FLOAT_TWO64 make_float64(1ULL << 62)
2188 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2189 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2190
2191 /* convert MIPS rounding mode in FCR31 to IEEE library */
2192 static unsigned int ieee_rm[] = {
2193 float_round_nearest_even,
2194 float_round_to_zero,
2195 float_round_up,
2196 float_round_down
2197 };
2198
2199 static inline void restore_rounding_mode(CPUMIPSState *env)
2200 {
2201 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
2202 &env->active_fpu.fp_status);
2203 }
2204
2205 static inline void restore_flush_mode(CPUMIPSState *env)
2206 {
2207 set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
2208 &env->active_fpu.fp_status);
2209 }
2210
2211 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2212 {
2213 target_ulong arg1 = 0;
2214
2215 switch (reg) {
2216 case 0:
2217 arg1 = (int32_t)env->active_fpu.fcr0;
2218 break;
2219 case 1:
2220 /* UFR Support - Read Status FR */
2221 if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2222 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2223 arg1 = (int32_t)
2224 ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR);
2225 } else {
2226 helper_raise_exception(env, EXCP_RI);
2227 }
2228 }
2229 break;
2230 case 25:
2231 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2232 break;
2233 case 26:
2234 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2235 break;
2236 case 28:
2237 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2238 break;
2239 default:
2240 arg1 = (int32_t)env->active_fpu.fcr31;
2241 break;
2242 }
2243
2244 return arg1;
2245 }
2246
2247 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2248 {
2249 switch (fs) {
2250 case 1:
2251 /* UFR Alias - Reset Status FR */
2252 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2253 return;
2254 }
2255 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2256 env->CP0_Status &= ~(1 << CP0St_FR);
2257 compute_hflags(env);
2258 } else {
2259 helper_raise_exception(env, EXCP_RI);
2260 }
2261 break;
2262 case 4:
2263 /* UNFR Alias - Set Status FR */
2264 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2265 return;
2266 }
2267 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2268 env->CP0_Status |= (1 << CP0St_FR);
2269 compute_hflags(env);
2270 } else {
2271 helper_raise_exception(env, EXCP_RI);
2272 }
2273 break;
2274 case 25:
2275 if (arg1 & 0xffffff00)
2276 return;
2277 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2278 ((arg1 & 0x1) << 23);
2279 break;
2280 case 26:
2281 if (arg1 & 0x007c0000)
2282 return;
2283 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2284 break;
2285 case 28:
2286 if (arg1 & 0x007c0000)
2287 return;
2288 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2289 ((arg1 & 0x4) << 22);
2290 break;
2291 case 31:
2292 if (arg1 & 0x007c0000)
2293 return;
2294 env->active_fpu.fcr31 = arg1;
2295 break;
2296 default:
2297 return;
2298 }
2299 /* set rounding mode */
2300 restore_rounding_mode(env);
2301 /* set flush-to-zero mode */
2302 restore_flush_mode(env);
2303 set_float_exception_flags(0, &env->active_fpu.fp_status);
2304 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31)) {
2305 do_raise_exception(env, EXCP_FPE, GETPC());
2306 }
2307 }
2308
2309 static int ieee_ex_to_mips(int xcpt)
2310 {
2311 int ret = 0;
2312 if (xcpt) {
2313 if (xcpt & float_flag_invalid) {
2314 ret |= FP_INVALID;
2315 }
2316 if (xcpt & float_flag_overflow) {
2317 ret |= FP_OVERFLOW;
2318 }
2319 if (xcpt & float_flag_underflow) {
2320 ret |= FP_UNDERFLOW;
2321 }
2322 if (xcpt & float_flag_divbyzero) {
2323 ret |= FP_DIV0;
2324 }
2325 if (xcpt & float_flag_inexact) {
2326 ret |= FP_INEXACT;
2327 }
2328 }
2329 return ret;
2330 }
2331
2332 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2333 {
2334 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2335
2336 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2337
2338 if (tmp) {
2339 set_float_exception_flags(0, &env->active_fpu.fp_status);
2340
2341 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2342 do_raise_exception(env, EXCP_FPE, pc);
2343 } else {
2344 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2345 }
2346 }
2347 }
2348
2349 /* Float support.
2350 Single precition routines have a "s" suffix, double precision a
2351 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2352 paired single lower "pl", paired single upper "pu". */
2353
2354 /* unary operations, modifying fp status */
2355 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2356 {
2357 fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2358 update_fcr31(env, GETPC());
2359 return fdt0;
2360 }
2361
2362 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2363 {
2364 fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2365 update_fcr31(env, GETPC());
2366 return fst0;
2367 }
2368
2369 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2370 {
2371 uint64_t fdt2;
2372
2373 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2374 update_fcr31(env, GETPC());
2375 return fdt2;
2376 }
2377
2378 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2379 {
2380 uint64_t fdt2;
2381
2382 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2383 update_fcr31(env, GETPC());
2384 return fdt2;
2385 }
2386
2387 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2388 {
2389 uint64_t fdt2;
2390
2391 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2392 update_fcr31(env, GETPC());
2393 return fdt2;
2394 }
2395
2396 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2397 {
2398 uint64_t dt2;
2399
2400 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2401 if (get_float_exception_flags(&env->active_fpu.fp_status)
2402 & (float_flag_invalid | float_flag_overflow)) {
2403 dt2 = FP_TO_INT64_OVERFLOW;
2404 }
2405 update_fcr31(env, GETPC());
2406 return dt2;
2407 }
2408
2409 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2410 {
2411 uint64_t dt2;
2412
2413 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2414 if (get_float_exception_flags(&env->active_fpu.fp_status)
2415 & (float_flag_invalid | float_flag_overflow)) {
2416 dt2 = FP_TO_INT64_OVERFLOW;
2417 }
2418 update_fcr31(env, GETPC());
2419 return dt2;
2420 }
2421
2422 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2423 {
2424 uint32_t fst2;
2425 uint32_t fsth2;
2426
2427 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2428 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2429 update_fcr31(env, GETPC());
2430 return ((uint64_t)fsth2 << 32) | fst2;
2431 }
2432
2433 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2434 {
2435 uint32_t wt2;
2436 uint32_t wth2;
2437 int excp, excph;
2438
2439 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2440 excp = get_float_exception_flags(&env->active_fpu.fp_status);
2441 if (excp & (float_flag_overflow | float_flag_invalid)) {
2442 wt2 = FP_TO_INT32_OVERFLOW;
2443 }
2444
2445 set_float_exception_flags(0, &env->active_fpu.fp_status);
2446 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2447 excph = get_float_exception_flags(&env->active_fpu.fp_status);
2448 if (excph & (float_flag_overflow | float_flag_invalid)) {
2449 wth2 = FP_TO_INT32_OVERFLOW;
2450 }
2451
2452 set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2453 update_fcr31(env, GETPC());
2454
2455 return ((uint64_t)wth2 << 32) | wt2;
2456 }
2457
2458 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2459 {
2460 uint32_t fst2;
2461
2462 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2463 update_fcr31(env, GETPC());
2464 return fst2;
2465 }
2466
2467 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2468 {
2469 uint32_t fst2;
2470
2471 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2472 update_fcr31(env, GETPC());
2473 return fst2;
2474 }
2475
2476 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2477 {
2478 uint32_t fst2;
2479
2480 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2481 update_fcr31(env, GETPC());
2482 return fst2;
2483 }
2484
2485 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2486 {
2487 uint32_t wt2;
2488
2489 wt2 = wt0;
2490 update_fcr31(env, GETPC());
2491 return wt2;
2492 }
2493
2494 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2495 {
2496 uint32_t wt2;
2497
2498 wt2 = wth0;
2499 update_fcr31(env, GETPC());
2500 return wt2;
2501 }
2502
2503 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2504 {
2505 uint32_t wt2;
2506
2507 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2508 update_fcr31(env, GETPC());
2509 if (get_float_exception_flags(&env->active_fpu.fp_status)
2510 & (float_flag_invalid | float_flag_overflow)) {
2511 wt2 = FP_TO_INT32_OVERFLOW;
2512 }
2513 return wt2;
2514 }
2515
2516 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2517 {
2518 uint32_t wt2;
2519
2520 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2521 if (get_float_exception_flags(&env->active_fpu.fp_status)
2522 & (float_flag_invalid | float_flag_overflow)) {
2523 wt2 = FP_TO_INT32_OVERFLOW;
2524 }
2525 update_fcr31(env, GETPC());
2526 return wt2;
2527 }
2528
2529 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2530 {
2531 uint64_t dt2;
2532
2533 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2534 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2535 restore_rounding_mode(env);
2536 if (get_float_exception_flags(&env->active_fpu.fp_status)
2537 & (float_flag_invalid | float_flag_overflow)) {
2538 dt2 = FP_TO_INT64_OVERFLOW;
2539 }
2540 update_fcr31(env, GETPC());
2541 return dt2;
2542 }
2543
2544 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2545 {
2546 uint64_t dt2;
2547
2548 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2549 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2550 restore_rounding_mode(env);
2551 if (get_float_exception_flags(&env->active_fpu.fp_status)
2552 & (float_flag_invalid | float_flag_overflow)) {
2553 dt2 = FP_TO_INT64_OVERFLOW;
2554 }
2555 update_fcr31(env, GETPC());
2556 return dt2;
2557 }
2558
2559 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2560 {
2561 uint32_t wt2;
2562
2563 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2564 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2565 restore_rounding_mode(env);
2566 if (get_float_exception_flags(&env->active_fpu.fp_status)
2567 & (float_flag_invalid | float_flag_overflow)) {
2568 wt2 = FP_TO_INT32_OVERFLOW;
2569 }
2570 update_fcr31(env, GETPC());
2571 return wt2;
2572 }
2573
2574 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2575 {
2576 uint32_t wt2;
2577
2578 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2579 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2580 restore_rounding_mode(env);
2581 if (get_float_exception_flags(&env->active_fpu.fp_status)
2582 & (float_flag_invalid | float_flag_overflow)) {
2583 wt2 = FP_TO_INT32_OVERFLOW;
2584 }
2585 update_fcr31(env, GETPC());
2586 return wt2;
2587 }
2588
2589 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2590 {
2591 uint64_t dt2;
2592
2593 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2594 if (get_float_exception_flags(&env->active_fpu.fp_status)
2595 & (float_flag_invalid | float_flag_overflow)) {
2596 dt2 = FP_TO_INT64_OVERFLOW;
2597 }
2598 update_fcr31(env, GETPC());
2599 return dt2;
2600 }
2601
2602 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2603 {
2604 uint64_t dt2;
2605
2606 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2607 if (get_float_exception_flags(&env->active_fpu.fp_status)
2608 & (float_flag_invalid | float_flag_overflow)) {
2609 dt2 = FP_TO_INT64_OVERFLOW;
2610 }
2611 update_fcr31(env, GETPC());
2612 return dt2;
2613 }
2614
2615 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2616 {
2617 uint32_t wt2;
2618
2619 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2620 if (get_float_exception_flags(&env->active_fpu.fp_status)
2621 & (float_flag_invalid | float_flag_overflow)) {
2622 wt2 = FP_TO_INT32_OVERFLOW;
2623 }
2624 update_fcr31(env, GETPC());
2625 return wt2;
2626 }
2627
2628 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2629 {
2630 uint32_t wt2;
2631
2632 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2633 if (get_float_exception_flags(&env->active_fpu.fp_status)
2634 & (float_flag_invalid | float_flag_overflow)) {
2635 wt2 = FP_TO_INT32_OVERFLOW;
2636 }
2637 update_fcr31(env, GETPC());
2638 return wt2;
2639 }
2640
2641 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2642 {
2643 uint64_t dt2;
2644
2645 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2646 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2647 restore_rounding_mode(env);
2648 if (get_float_exception_flags(&env->active_fpu.fp_status)
2649 & (float_flag_invalid | float_flag_overflow)) {
2650 dt2 = FP_TO_INT64_OVERFLOW;
2651 }
2652 update_fcr31(env, GETPC());
2653 return dt2;
2654 }
2655
2656 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2657 {
2658 uint64_t dt2;
2659
2660 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2661 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2662 restore_rounding_mode(env);
2663 if (get_float_exception_flags(&env->active_fpu.fp_status)
2664 & (float_flag_invalid | float_flag_overflow)) {
2665 dt2 = FP_TO_INT64_OVERFLOW;
2666 }
2667 update_fcr31(env, GETPC());
2668 return dt2;
2669 }
2670
2671 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2672 {
2673 uint32_t wt2;
2674
2675 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2676 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2677 restore_rounding_mode(env);
2678 if (get_float_exception_flags(&env->active_fpu.fp_status)
2679 & (float_flag_invalid | float_flag_overflow)) {
2680 wt2 = FP_TO_INT32_OVERFLOW;
2681 }
2682 update_fcr31(env, GETPC());
2683 return wt2;
2684 }
2685
2686 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2687 {
2688 uint32_t wt2;
2689
2690 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2691 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2692 restore_rounding_mode(env);
2693 if (get_float_exception_flags(&env->active_fpu.fp_status)
2694 & (float_flag_invalid | float_flag_overflow)) {
2695 wt2 = FP_TO_INT32_OVERFLOW;
2696 }
2697 update_fcr31(env, GETPC());
2698 return wt2;
2699 }
2700
2701 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2702 {
2703 uint64_t dt2;
2704
2705 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2706 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2707 restore_rounding_mode(env);
2708 if (get_float_exception_flags(&env->active_fpu.fp_status)
2709 & (float_flag_invalid | float_flag_overflow)) {
2710 dt2 = FP_TO_INT64_OVERFLOW;
2711 }
2712 update_fcr31(env, GETPC());
2713 return dt2;
2714 }
2715
2716 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2717 {
2718 uint64_t dt2;
2719
2720 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2721 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2722 restore_rounding_mode(env);
2723 if (get_float_exception_flags(&env->active_fpu.fp_status)
2724 & (float_flag_invalid | float_flag_overflow)) {
2725 dt2 = FP_TO_INT64_OVERFLOW;
2726 }
2727 update_fcr31(env, GETPC());
2728 return dt2;
2729 }
2730
2731 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2732 {
2733 uint32_t wt2;
2734
2735 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2736 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2737 restore_rounding_mode(env);
2738 if (get_float_exception_flags(&env->active_fpu.fp_status)
2739 & (float_flag_invalid | float_flag_overflow)) {
2740 wt2 = FP_TO_INT32_OVERFLOW;
2741 }
2742 update_fcr31(env, GETPC());
2743 return wt2;
2744 }
2745
2746 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2747 {
2748 uint32_t wt2;
2749
2750 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2751 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2752 restore_rounding_mode(env);
2753 if (get_float_exception_flags(&env->active_fpu.fp_status)
2754 & (float_flag_invalid | float_flag_overflow)) {
2755 wt2 = FP_TO_INT32_OVERFLOW;
2756 }
2757 update_fcr31(env, GETPC());
2758 return wt2;
2759 }
2760
2761 /* unary operations, not modifying fp status */
2762 #define FLOAT_UNOP(name) \
2763 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
2764 { \
2765 return float64_ ## name(fdt0); \
2766 } \
2767 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
2768 { \
2769 return float32_ ## name(fst0); \
2770 } \
2771 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
2772 { \
2773 uint32_t wt0; \
2774 uint32_t wth0; \
2775 \
2776 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
2777 wth0 = float32_ ## name(fdt0 >> 32); \
2778 return ((uint64_t)wth0 << 32) | wt0; \
2779 }
2780 FLOAT_UNOP(abs)
2781 FLOAT_UNOP(chs)
2782 #undef FLOAT_UNOP
2783
2784 /* MIPS specific unary operations */
2785 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
2786 {
2787 uint64_t fdt2;
2788
2789 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2790 update_fcr31(env, GETPC());
2791 return fdt2;
2792 }
2793
2794 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
2795 {
2796 uint32_t fst2;
2797
2798 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2799 update_fcr31(env, GETPC());
2800 return fst2;
2801 }
2802
2803 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
2804 {
2805 uint64_t fdt2;
2806
2807 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2808 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2809 update_fcr31(env, GETPC());
2810 return fdt2;
2811 }
2812
2813 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
2814 {
2815 uint32_t fst2;
2816
2817 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2818 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2819 update_fcr31(env, GETPC());
2820 return fst2;
2821 }
2822
2823 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
2824 {
2825 uint64_t fdt2;
2826
2827 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
2828 update_fcr31(env, GETPC());
2829 return fdt2;
2830 }
2831
2832 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
2833 {
2834 uint32_t fst2;
2835
2836 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
2837 update_fcr31(env, GETPC());
2838 return fst2;
2839 }
2840
2841 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
2842 {
2843 uint32_t fst2;
2844 uint32_t fsth2;
2845
2846 fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2847 fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
2848 update_fcr31(env, GETPC());
2849 return ((uint64_t)fsth2 << 32) | fst2;
2850 }
2851
2852 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
2853 {
2854 uint64_t fdt2;
2855
2856 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2857 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
2858 update_fcr31(env, GETPC());
2859 return fdt2;
2860 }
2861
2862 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
2863 {
2864 uint32_t fst2;
2865
2866 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2867 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2868 update_fcr31(env, GETPC());
2869 return fst2;
2870 }
2871
2872 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
2873 {
2874 uint32_t fst2;
2875 uint32_t fsth2;
2876
2877 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2878 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2879 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
2880 fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
2881 update_fcr31(env, GETPC());
2882 return ((uint64_t)fsth2 << 32) | fst2;
2883 }
2884
2885 #define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env)
2886
2887 /* binary operations */
2888 #define FLOAT_BINOP(name) \
2889 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
2890 uint64_t fdt0, uint64_t fdt1) \
2891 { \
2892 uint64_t dt2; \
2893 \
2894 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
2895 update_fcr31(env, GETPC()); \
2896 return dt2; \
2897 } \
2898 \
2899 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
2900 uint32_t fst0, uint32_t fst1) \
2901 { \
2902 uint32_t wt2; \
2903 \
2904 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2905 update_fcr31(env, GETPC()); \
2906 return wt2; \
2907 } \
2908 \
2909 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
2910 uint64_t fdt0, \
2911 uint64_t fdt1) \
2912 { \
2913 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2914 uint32_t fsth0 = fdt0 >> 32; \
2915 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2916 uint32_t fsth1 = fdt1 >> 32; \
2917 uint32_t wt2; \
2918 uint32_t wth2; \
2919 \
2920 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2921 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
2922 update_fcr31(env, GETPC()); \
2923 return ((uint64_t)wth2 << 32) | wt2; \
2924 }
2925
2926 FLOAT_BINOP(add)
2927 FLOAT_BINOP(sub)
2928 FLOAT_BINOP(mul)
2929 FLOAT_BINOP(div)
2930 #undef FLOAT_BINOP
2931
2932 #define UNFUSED_FMA(prefix, a, b, c, flags) \
2933 { \
2934 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
2935 if ((flags) & float_muladd_negate_c) { \
2936 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
2937 } else { \
2938 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
2939 } \
2940 if ((flags) & float_muladd_negate_result) { \
2941 a = prefix##_chs(a); \
2942 } \
2943 }
2944
2945 /* FMA based operations */
2946 #define FLOAT_FMA(name, type) \
2947 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
2948 uint64_t fdt0, uint64_t fdt1, \
2949 uint64_t fdt2) \
2950 { \
2951 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
2952 update_fcr31(env, GETPC()); \
2953 return fdt0; \
2954 } \
2955 \
2956 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
2957 uint32_t fst0, uint32_t fst1, \
2958 uint32_t fst2) \
2959 { \
2960 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
2961 update_fcr31(env, GETPC()); \
2962 return fst0; \
2963 } \
2964 \
2965 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
2966 uint64_t fdt0, uint64_t fdt1, \
2967 uint64_t fdt2) \
2968 { \
2969 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2970 uint32_t fsth0 = fdt0 >> 32; \
2971 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2972 uint32_t fsth1 = fdt1 >> 32; \
2973 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
2974 uint32_t fsth2 = fdt2 >> 32; \
2975 \
2976 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
2977 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
2978 update_fcr31(env, GETPC()); \
2979 return ((uint64_t)fsth0 << 32) | fst0; \
2980 }
2981 FLOAT_FMA(madd, 0)
2982 FLOAT_FMA(msub, float_muladd_negate_c)
2983 FLOAT_FMA(nmadd, float_muladd_negate_result)
2984 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
2985 #undef FLOAT_FMA
2986
2987 /* MIPS specific binary operations */
2988 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
2989 {
2990 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2991 fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
2992 update_fcr31(env, GETPC());
2993 return fdt2;
2994 }
2995
2996 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
2997 {
2998 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2999 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3000 update_fcr31(env, GETPC());
3001 return fst2;
3002 }
3003
3004 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3005 {
3006 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3007 uint32_t fsth0 = fdt0 >> 32;
3008 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3009 uint32_t fsth2 = fdt2 >> 32;
3010
3011 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3012 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3013 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3014 fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3015 update_fcr31(env, GETPC());
3016 return ((uint64_t)fsth2 << 32) | fst2;
3017 }
3018
3019 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3020 {
3021 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3022 fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3023 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3024 update_fcr31(env, GETPC());
3025 return fdt2;
3026 }
3027
3028 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3029 {
3030 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3031 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3032 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3033 update_fcr31(env, GETPC());
3034 return fst2;
3035 }
3036
3037 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3038 {
3039 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3040 uint32_t fsth0 = fdt0 >> 32;
3041 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3042 uint32_t fsth2 = fdt2 >> 32;
3043
3044 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3045 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3046 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3047 fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3048 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3049 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3050 update_fcr31(env, GETPC());
3051 return ((uint64_t)fsth2 << 32) | fst2;
3052 }
3053
3054 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3055 {
3056 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3057 uint32_t fsth0 = fdt0 >> 32;
3058 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3059 uint32_t fsth1 = fdt1 >> 32;
3060 uint32_t fst2;
3061 uint32_t fsth2;
3062
3063 fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3064 fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3065 update_fcr31(env, GETPC());
3066 return ((uint64_t)fsth2 << 32) | fst2;
3067 }
3068
3069 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3070 {
3071 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3072 uint32_t fsth0 = fdt0 >> 32;
3073 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3074 uint32_t fsth1 = fdt1 >> 32;
3075 uint32_t fst2;
3076 uint32_t fsth2;
3077
3078 fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3079 fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3080 update_fcr31(env, GETPC());
3081 return ((uint64_t)fsth2 << 32) | fst2;
3082 }
3083
3084 /* compare operations */
3085 #define FOP_COND_D(op, cond) \
3086 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3087 uint64_t fdt1, int cc) \
3088 { \
3089 int c; \
3090 c = cond; \
3091 update_fcr31(env, GETPC()); \
3092 if (c) \
3093 SET_FP_COND(cc, env->active_fpu); \
3094 else \
3095 CLEAR_FP_COND(cc, env->active_fpu); \
3096 } \
3097 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3098 uint64_t fdt1, int cc) \
3099 { \
3100 int c; \
3101 fdt0 = float64_abs(fdt0); \
3102 fdt1 = float64_abs(fdt1); \
3103 c = cond; \
3104 update_fcr31(env, GETPC()); \
3105 if (c) \
3106 SET_FP_COND(cc, env->active_fpu); \
3107 else \
3108 CLEAR_FP_COND(cc, env->active_fpu); \
3109 }
3110
3111 /* NOTE: the comma operator will make "cond" to eval to false,
3112 * but float64_unordered_quiet() is still called. */
3113 FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3114 FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3115 FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3116 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3117 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3118 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3119 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3120 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3121 /* NOTE: the comma operator will make "cond" to eval to false,
3122 * but float64_unordered() is still called. */
3123 FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3124 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3125 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3126 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3127 FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3128 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3129 FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3130 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3131
3132 #define FOP_COND_S(op, cond) \
3133 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3134 uint32_t fst1, int cc) \
3135 { \
3136 int c; \
3137 c = cond; \
3138 update_fcr31(env, GETPC()); \
3139 if (c) \
3140 SET_FP_COND(cc, env->active_fpu); \
3141 else \
3142 CLEAR_FP_COND(cc, env->active_fpu); \
3143 } \
3144 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3145 uint32_t fst1, int cc) \
3146 { \
3147 int c; \
3148 fst0 = float32_abs(fst0); \
3149 fst1 = float32_abs(fst1); \
3150 c = cond; \
3151 update_fcr31(env, GETPC()); \
3152 if (c) \
3153 SET_FP_COND(cc, env->active_fpu); \
3154 else \
3155 CLEAR_FP_COND(cc, env->active_fpu); \
3156 }
3157
3158 /* NOTE: the comma operator will make "cond" to eval to false,
3159 * but float32_unordered_quiet() is still called. */
3160 FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3161 FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3162 FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3163 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3164 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3165 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3166 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3167 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3168 /* NOTE: the comma operator will make "cond" to eval to false,
3169 * but float32_unordered() is still called. */
3170 FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3171 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3172 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3173 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3174 FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3175 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3176 FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status))
3177 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3178
3179 #define FOP_COND_PS(op, condl, condh) \
3180 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3181 uint64_t fdt1, int cc) \
3182 { \
3183 uint32_t fst0, fsth0, fst1, fsth1; \
3184 int ch, cl; \
3185 fst0 = fdt0 & 0XFFFFFFFF; \
3186 fsth0 = fdt0 >> 32; \
3187 fst1 = fdt1 & 0XFFFFFFFF; \
3188 fsth1 = fdt1 >> 32; \
3189 cl = condl; \
3190 ch = condh; \
3191 update_fcr31(env, GETPC()); \
3192 if (cl) \
3193 SET_FP_COND(cc, env->active_fpu); \
3194 else \
3195 CLEAR_FP_COND(cc, env->active_fpu); \
3196 if (ch) \
3197 SET_FP_COND(cc + 1, env->active_fpu); \
3198 else \
3199 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3200 } \
3201 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3202 uint64_t fdt1, int cc) \
3203 { \
3204 uint32_t fst0, fsth0, fst1, fsth1; \
3205 int ch, cl; \
3206 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
3207 fsth0 = float32_abs(fdt0 >> 32); \
3208 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
3209 fsth1 = float32_abs(fdt1 >> 32); \
3210 cl = condl; \
3211 ch = condh; \
3212 update_fcr31(env, GETPC()); \
3213 if (cl) \
3214 SET_FP_COND(cc, env->active_fpu); \
3215 else \
3216 CLEAR_FP_COND(cc, env->active_fpu); \
3217 if (ch) \
3218 SET_FP_COND(cc + 1, env->active_fpu); \
3219 else \
3220 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3221 }
3222
3223 /* NOTE: the comma operator will make "cond" to eval to false,
3224 * but float32_unordered_quiet() is still called. */
3225 FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3226 (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3227 FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3228 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3229 FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3230 float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3231 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3232 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3233 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3234 float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3235 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3236 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3237 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3238 float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3239 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3240 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3241 /* NOTE: the comma operator will make "cond" to eval to false,
3242 * but float32_unordered() is still called. */
3243 FOP_COND_PS(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3244 (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3245 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3246 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3247 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3248 float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3249 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3250 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3251 FOP_COND_PS(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3252 float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3253 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3254 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3255 FOP_COND_PS(le, float32_le(fst0, fst1, &env->active_fpu.fp_status),
3256 float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3257 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3258 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
AR7 emulation for QEMU