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megasas: add MegaRAID SAS 2108 emulation
[qemu/ar7.git] / tci.c
blob4711ee4817fb39bd4780d2d333270a02892b163c
1 /*
2 * Tiny Code Interpreter for QEMU
3 *
4 * Copyright (c) 2009, 2011 Stefan Weil
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "config.h"
21
22 /* Defining NDEBUG disables assertions (which makes the code faster). */
23 #if !defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG)
24 # define NDEBUG
25 #endif
26
27 #include "qemu-common.h"
28 #include "exec/exec-all.h" /* MAX_OPC_PARAM_IARGS */
29 #include "exec/cpu_ldst.h"
30 #include "tcg-op.h"
31
32 /* Marker for missing code. */
33 #define TODO() \
34 do { \
35 fprintf(stderr, "TODO %s:%u: %s()\n", \
36 __FILE__, __LINE__, __func__); \
37 tcg_abort(); \
38 } while (0)
39
40 #if MAX_OPC_PARAM_IARGS != 5
41 # error Fix needed, number of supported input arguments changed!
42 #endif
43 #if TCG_TARGET_REG_BITS == 32
44 typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
45 tcg_target_ulong, tcg_target_ulong,
46 tcg_target_ulong, tcg_target_ulong,
47 tcg_target_ulong, tcg_target_ulong,
48 tcg_target_ulong, tcg_target_ulong);
49 #else
50 typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
51 tcg_target_ulong, tcg_target_ulong,
52 tcg_target_ulong);
53 #endif
54
55 /* Targets which don't use GETPC also don't need tci_tb_ptr
56 which makes them a little faster. */
57 #if defined(GETPC)
58 uintptr_t tci_tb_ptr;
59 #endif
60
61 static tcg_target_ulong tci_reg[TCG_TARGET_NB_REGS];
62
63 static tcg_target_ulong tci_read_reg(TCGReg index)
64 {
65 assert(index < ARRAY_SIZE(tci_reg));
66 return tci_reg[index];
67 }
68
69 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
70 static int8_t tci_read_reg8s(TCGReg index)
71 {
72 return (int8_t)tci_read_reg(index);
73 }
74 #endif
75
76 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
77 static int16_t tci_read_reg16s(TCGReg index)
78 {
79 return (int16_t)tci_read_reg(index);
80 }
81 #endif
82
83 #if TCG_TARGET_REG_BITS == 64
84 static int32_t tci_read_reg32s(TCGReg index)
85 {
86 return (int32_t)tci_read_reg(index);
87 }
88 #endif
89
90 static uint8_t tci_read_reg8(TCGReg index)
91 {
92 return (uint8_t)tci_read_reg(index);
93 }
94
95 static uint16_t tci_read_reg16(TCGReg index)
96 {
97 return (uint16_t)tci_read_reg(index);
98 }
99
100 static uint32_t tci_read_reg32(TCGReg index)
101 {
102 return (uint32_t)tci_read_reg(index);
103 }
104
105 #if TCG_TARGET_REG_BITS == 64
106 static uint64_t tci_read_reg64(TCGReg index)
107 {
108 return tci_read_reg(index);
109 }
110 #endif
111
112 static void tci_write_reg(TCGReg index, tcg_target_ulong value)
113 {
114 assert(index < ARRAY_SIZE(tci_reg));
115 assert(index != TCG_AREG0);
116 assert(index != TCG_REG_CALL_STACK);
117 tci_reg[index] = value;
118 }
119
120 #if TCG_TARGET_REG_BITS == 64
121 static void tci_write_reg32s(TCGReg index, int32_t value)
122 {
123 tci_write_reg(index, value);
124 }
125 #endif
126
127 static void tci_write_reg8(TCGReg index, uint8_t value)
128 {
129 tci_write_reg(index, value);
130 }
131
132 static void tci_write_reg32(TCGReg index, uint32_t value)
133 {
134 tci_write_reg(index, value);
135 }
136
137 #if TCG_TARGET_REG_BITS == 32
138 static void tci_write_reg64(uint32_t high_index, uint32_t low_index,
139 uint64_t value)
140 {
141 tci_write_reg(low_index, value);
142 tci_write_reg(high_index, value >> 32);
143 }
144 #elif TCG_TARGET_REG_BITS == 64
145 static void tci_write_reg64(TCGReg index, uint64_t value)
146 {
147 tci_write_reg(index, value);
148 }
149 #endif
150
151 #if TCG_TARGET_REG_BITS == 32
152 /* Create a 64 bit value from two 32 bit values. */
153 static uint64_t tci_uint64(uint32_t high, uint32_t low)
154 {
155 return ((uint64_t)high << 32) + low;
156 }
157 #endif
158
159 /* Read constant (native size) from bytecode. */
160 static tcg_target_ulong tci_read_i(uint8_t **tb_ptr)
161 {
162 tcg_target_ulong value = *(tcg_target_ulong *)(*tb_ptr);
163 *tb_ptr += sizeof(value);
164 return value;
165 }
166
167 /* Read unsigned constant (32 bit) from bytecode. */
168 static uint32_t tci_read_i32(uint8_t **tb_ptr)
169 {
170 uint32_t value = *(uint32_t *)(*tb_ptr);
171 *tb_ptr += sizeof(value);
172 return value;
173 }
174
175 /* Read signed constant (32 bit) from bytecode. */
176 static int32_t tci_read_s32(uint8_t **tb_ptr)
177 {
178 int32_t value = *(int32_t *)(*tb_ptr);
179 *tb_ptr += sizeof(value);
180 return value;
181 }
182
183 #if TCG_TARGET_REG_BITS == 64
184 /* Read constant (64 bit) from bytecode. */
185 static uint64_t tci_read_i64(uint8_t **tb_ptr)
186 {
187 uint64_t value = *(uint64_t *)(*tb_ptr);
188 *tb_ptr += sizeof(value);
189 return value;
190 }
191 #endif
192
193 /* Read indexed register (native size) from bytecode. */
194 static tcg_target_ulong tci_read_r(uint8_t **tb_ptr)
195 {
196 tcg_target_ulong value = tci_read_reg(**tb_ptr);
197 *tb_ptr += 1;
198 return value;
199 }
200
201 /* Read indexed register (8 bit) from bytecode. */
202 static uint8_t tci_read_r8(uint8_t **tb_ptr)
203 {
204 uint8_t value = tci_read_reg8(**tb_ptr);
205 *tb_ptr += 1;
206 return value;
207 }
208
209 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
210 /* Read indexed register (8 bit signed) from bytecode. */
211 static int8_t tci_read_r8s(uint8_t **tb_ptr)
212 {
213 int8_t value = tci_read_reg8s(**tb_ptr);
214 *tb_ptr += 1;
215 return value;
216 }
217 #endif
218
219 /* Read indexed register (16 bit) from bytecode. */
220 static uint16_t tci_read_r16(uint8_t **tb_ptr)
221 {
222 uint16_t value = tci_read_reg16(**tb_ptr);
223 *tb_ptr += 1;
224 return value;
225 }
226
227 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
228 /* Read indexed register (16 bit signed) from bytecode. */
229 static int16_t tci_read_r16s(uint8_t **tb_ptr)
230 {
231 int16_t value = tci_read_reg16s(**tb_ptr);
232 *tb_ptr += 1;
233 return value;
234 }
235 #endif
236
237 /* Read indexed register (32 bit) from bytecode. */
238 static uint32_t tci_read_r32(uint8_t **tb_ptr)
239 {
240 uint32_t value = tci_read_reg32(**tb_ptr);
241 *tb_ptr += 1;
242 return value;
243 }
244
245 #if TCG_TARGET_REG_BITS == 32
246 /* Read two indexed registers (2 * 32 bit) from bytecode. */
247 static uint64_t tci_read_r64(uint8_t **tb_ptr)
248 {
249 uint32_t low = tci_read_r32(tb_ptr);
250 return tci_uint64(tci_read_r32(tb_ptr), low);
251 }
252 #elif TCG_TARGET_REG_BITS == 64
253 /* Read indexed register (32 bit signed) from bytecode. */
254 static int32_t tci_read_r32s(uint8_t **tb_ptr)
255 {
256 int32_t value = tci_read_reg32s(**tb_ptr);
257 *tb_ptr += 1;
258 return value;
259 }
260
261 /* Read indexed register (64 bit) from bytecode. */
262 static uint64_t tci_read_r64(uint8_t **tb_ptr)
263 {
264 uint64_t value = tci_read_reg64(**tb_ptr);
265 *tb_ptr += 1;
266 return value;
267 }
268 #endif
269
270 /* Read indexed register(s) with target address from bytecode. */
271 static target_ulong tci_read_ulong(uint8_t **tb_ptr)
272 {
273 target_ulong taddr = tci_read_r(tb_ptr);
274 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
275 taddr += (uint64_t)tci_read_r(tb_ptr) << 32;
276 #endif
277 return taddr;
278 }
279
280 /* Read indexed register or constant (native size) from bytecode. */
281 static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr)
282 {
283 tcg_target_ulong value;
284 TCGReg r = **tb_ptr;
285 *tb_ptr += 1;
286 if (r == TCG_CONST) {
287 value = tci_read_i(tb_ptr);
288 } else {
289 value = tci_read_reg(r);
290 }
291 return value;
292 }
293
294 /* Read indexed register or constant (32 bit) from bytecode. */
295 static uint32_t tci_read_ri32(uint8_t **tb_ptr)
296 {
297 uint32_t value;
298 TCGReg r = **tb_ptr;
299 *tb_ptr += 1;
300 if (r == TCG_CONST) {
301 value = tci_read_i32(tb_ptr);
302 } else {
303 value = tci_read_reg32(r);
304 }
305 return value;
306 }
307
308 #if TCG_TARGET_REG_BITS == 32
309 /* Read two indexed registers or constants (2 * 32 bit) from bytecode. */
310 static uint64_t tci_read_ri64(uint8_t **tb_ptr)
311 {
312 uint32_t low = tci_read_ri32(tb_ptr);
313 return tci_uint64(tci_read_ri32(tb_ptr), low);
314 }
315 #elif TCG_TARGET_REG_BITS == 64
316 /* Read indexed register or constant (64 bit) from bytecode. */
317 static uint64_t tci_read_ri64(uint8_t **tb_ptr)
318 {
319 uint64_t value;
320 TCGReg r = **tb_ptr;
321 *tb_ptr += 1;
322 if (r == TCG_CONST) {
323 value = tci_read_i64(tb_ptr);
324 } else {
325 value = tci_read_reg64(r);
326 }
327 return value;
328 }
329 #endif
330
331 static tcg_target_ulong tci_read_label(uint8_t **tb_ptr)
332 {
333 tcg_target_ulong label = tci_read_i(tb_ptr);
334 assert(label != 0);
335 return label;
336 }
337
338 static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition)
339 {
340 bool result = false;
341 int32_t i0 = u0;
342 int32_t i1 = u1;
343 switch (condition) {
344 case TCG_COND_EQ:
345 result = (u0 == u1);
346 break;
347 case TCG_COND_NE:
348 result = (u0 != u1);
349 break;
350 case TCG_COND_LT:
351 result = (i0 < i1);
352 break;
353 case TCG_COND_GE:
354 result = (i0 >= i1);
355 break;
356 case TCG_COND_LE:
357 result = (i0 <= i1);
358 break;
359 case TCG_COND_GT:
360 result = (i0 > i1);
361 break;
362 case TCG_COND_LTU:
363 result = (u0 < u1);
364 break;
365 case TCG_COND_GEU:
366 result = (u0 >= u1);
367 break;
368 case TCG_COND_LEU:
369 result = (u0 <= u1);
370 break;
371 case TCG_COND_GTU:
372 result = (u0 > u1);
373 break;
374 default:
375 TODO();
376 }
377 return result;
378 }
379
380 static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
381 {
382 bool result = false;
383 int64_t i0 = u0;
384 int64_t i1 = u1;
385 switch (condition) {
386 case TCG_COND_EQ:
387 result = (u0 == u1);
388 break;
389 case TCG_COND_NE:
390 result = (u0 != u1);
391 break;
392 case TCG_COND_LT:
393 result = (i0 < i1);
394 break;
395 case TCG_COND_GE:
396 result = (i0 >= i1);
397 break;
398 case TCG_COND_LE:
399 result = (i0 <= i1);
400 break;
401 case TCG_COND_GT:
402 result = (i0 > i1);
403 break;
404 case TCG_COND_LTU:
405 result = (u0 < u1);
406 break;
407 case TCG_COND_GEU:
408 result = (u0 >= u1);
409 break;
410 case TCG_COND_LEU:
411 result = (u0 <= u1);
412 break;
413 case TCG_COND_GTU:
414 result = (u0 > u1);
415 break;
416 default:
417 TODO();
418 }
419 return result;
420 }
421
422 #ifdef CONFIG_SOFTMMU
423 # define mmuidx tci_read_i(&tb_ptr)
424 # define qemu_ld_ub \
425 helper_ret_ldub_mmu(env, taddr, mmuidx, (uintptr_t)tb_ptr)
426 # define qemu_ld_leuw \
427 helper_le_lduw_mmu(env, taddr, mmuidx, (uintptr_t)tb_ptr)
428 # define qemu_ld_leul \
429 helper_le_ldul_mmu(env, taddr, mmuidx, (uintptr_t)tb_ptr)
430 # define qemu_ld_leq \
431 helper_le_ldq_mmu(env, taddr, mmuidx, (uintptr_t)tb_ptr)
432 # define qemu_ld_beuw \
433 helper_be_lduw_mmu(env, taddr, mmuidx, (uintptr_t)tb_ptr)
434 # define qemu_ld_beul \
435 helper_be_ldul_mmu(env, taddr, mmuidx, (uintptr_t)tb_ptr)
436 # define qemu_ld_beq \
437 helper_be_ldq_mmu(env, taddr, mmuidx, (uintptr_t)tb_ptr)
438 # define qemu_st_b(X) \
439 helper_ret_stb_mmu(env, taddr, X, mmuidx, (uintptr_t)tb_ptr)
440 # define qemu_st_lew(X) \
441 helper_le_stw_mmu(env, taddr, X, mmuidx, (uintptr_t)tb_ptr)
442 # define qemu_st_lel(X) \
443 helper_le_stl_mmu(env, taddr, X, mmuidx, (uintptr_t)tb_ptr)
444 # define qemu_st_leq(X) \
445 helper_le_stq_mmu(env, taddr, X, mmuidx, (uintptr_t)tb_ptr)
446 # define qemu_st_bew(X) \
447 helper_be_stw_mmu(env, taddr, X, mmuidx, (uintptr_t)tb_ptr)
448 # define qemu_st_bel(X) \
449 helper_be_stl_mmu(env, taddr, X, mmuidx, (uintptr_t)tb_ptr)
450 # define qemu_st_beq(X) \
451 helper_be_stq_mmu(env, taddr, X, mmuidx, (uintptr_t)tb_ptr)
452 #else
453 # define qemu_ld_ub ldub_p(g2h(taddr))
454 # define qemu_ld_leuw lduw_le_p(g2h(taddr))
455 # define qemu_ld_leul (uint32_t)ldl_le_p(g2h(taddr))
456 # define qemu_ld_leq ldq_le_p(g2h(taddr))
457 # define qemu_ld_beuw lduw_be_p(g2h(taddr))
458 # define qemu_ld_beul (uint32_t)ldl_be_p(g2h(taddr))
459 # define qemu_ld_beq ldq_be_p(g2h(taddr))
460 # define qemu_st_b(X) stb_p(g2h(taddr), X)
461 # define qemu_st_lew(X) stw_le_p(g2h(taddr), X)
462 # define qemu_st_lel(X) stl_le_p(g2h(taddr), X)
463 # define qemu_st_leq(X) stq_le_p(g2h(taddr), X)
464 # define qemu_st_bew(X) stw_be_p(g2h(taddr), X)
465 # define qemu_st_bel(X) stl_be_p(g2h(taddr), X)
466 # define qemu_st_beq(X) stq_be_p(g2h(taddr), X)
467 #endif
468
469 /* Interpret pseudo code in tb. */
470 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
471 {
472 long tcg_temps[CPU_TEMP_BUF_NLONGS];
473 uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS);
474 uintptr_t next_tb = 0;
475
476 tci_reg[TCG_AREG0] = (tcg_target_ulong)env;
477 tci_reg[TCG_REG_CALL_STACK] = sp_value;
478 assert(tb_ptr);
479
480 for (;;) {
481 TCGOpcode opc = tb_ptr[0];
482 #if !defined(NDEBUG)
483 uint8_t op_size = tb_ptr[1];
484 uint8_t *old_code_ptr = tb_ptr;
485 #endif
486 tcg_target_ulong t0;
487 tcg_target_ulong t1;
488 tcg_target_ulong t2;
489 tcg_target_ulong label;
490 TCGCond condition;
491 target_ulong taddr;
492 uint8_t tmp8;
493 uint16_t tmp16;
494 uint32_t tmp32;
495 uint64_t tmp64;
496 #if TCG_TARGET_REG_BITS == 32
497 uint64_t v64;
498 #endif
499 TCGMemOp memop;
500
501 #if defined(GETPC)
502 tci_tb_ptr = (uintptr_t)tb_ptr;
503 #endif
504
505 /* Skip opcode and size entry. */
506 tb_ptr += 2;
507
508 switch (opc) {
509 case INDEX_op_end:
510 case INDEX_op_nop:
511 break;
512 case INDEX_op_nop1:
513 case INDEX_op_nop2:
514 case INDEX_op_nop3:
515 case INDEX_op_nopn:
516 case INDEX_op_discard:
517 TODO();
518 break;
519 case INDEX_op_set_label:
520 TODO();
521 break;
522 case INDEX_op_call:
523 t0 = tci_read_ri(&tb_ptr);
524 #if TCG_TARGET_REG_BITS == 32
525 tmp64 = ((helper_function)t0)(tci_read_reg(TCG_REG_R0),
526 tci_read_reg(TCG_REG_R1),
527 tci_read_reg(TCG_REG_R2),
528 tci_read_reg(TCG_REG_R3),
529 tci_read_reg(TCG_REG_R5),
530 tci_read_reg(TCG_REG_R6),
531 tci_read_reg(TCG_REG_R7),
532 tci_read_reg(TCG_REG_R8),
533 tci_read_reg(TCG_REG_R9),
534 tci_read_reg(TCG_REG_R10));
535 tci_write_reg(TCG_REG_R0, tmp64);
536 tci_write_reg(TCG_REG_R1, tmp64 >> 32);
537 #else
538 tmp64 = ((helper_function)t0)(tci_read_reg(TCG_REG_R0),
539 tci_read_reg(TCG_REG_R1),
540 tci_read_reg(TCG_REG_R2),
541 tci_read_reg(TCG_REG_R3),
542 tci_read_reg(TCG_REG_R5));
543 tci_write_reg(TCG_REG_R0, tmp64);
544 #endif
545 break;
546 case INDEX_op_br:
547 label = tci_read_label(&tb_ptr);
548 assert(tb_ptr == old_code_ptr + op_size);
549 tb_ptr = (uint8_t *)label;
550 continue;
551 case INDEX_op_setcond_i32:
552 t0 = *tb_ptr++;
553 t1 = tci_read_r32(&tb_ptr);
554 t2 = tci_read_ri32(&tb_ptr);
555 condition = *tb_ptr++;
556 tci_write_reg32(t0, tci_compare32(t1, t2, condition));
557 break;
558 #if TCG_TARGET_REG_BITS == 32
559 case INDEX_op_setcond2_i32:
560 t0 = *tb_ptr++;
561 tmp64 = tci_read_r64(&tb_ptr);
562 v64 = tci_read_ri64(&tb_ptr);
563 condition = *tb_ptr++;
564 tci_write_reg32(t0, tci_compare64(tmp64, v64, condition));
565 break;
566 #elif TCG_TARGET_REG_BITS == 64
567 case INDEX_op_setcond_i64:
568 t0 = *tb_ptr++;
569 t1 = tci_read_r64(&tb_ptr);
570 t2 = tci_read_ri64(&tb_ptr);
571 condition = *tb_ptr++;
572 tci_write_reg64(t0, tci_compare64(t1, t2, condition));
573 break;
574 #endif
575 case INDEX_op_mov_i32:
576 t0 = *tb_ptr++;
577 t1 = tci_read_r32(&tb_ptr);
578 tci_write_reg32(t0, t1);
579 break;
580 case INDEX_op_movi_i32:
581 t0 = *tb_ptr++;
582 t1 = tci_read_i32(&tb_ptr);
583 tci_write_reg32(t0, t1);
584 break;
585
586 /* Load/store operations (32 bit). */
587
588 case INDEX_op_ld8u_i32:
589 t0 = *tb_ptr++;
590 t1 = tci_read_r(&tb_ptr);
591 t2 = tci_read_s32(&tb_ptr);
592 tci_write_reg8(t0, *(uint8_t *)(t1 + t2));
593 break;
594 case INDEX_op_ld8s_i32:
595 case INDEX_op_ld16u_i32:
596 TODO();
597 break;
598 case INDEX_op_ld16s_i32:
599 TODO();
600 break;
601 case INDEX_op_ld_i32:
602 t0 = *tb_ptr++;
603 t1 = tci_read_r(&tb_ptr);
604 t2 = tci_read_s32(&tb_ptr);
605 tci_write_reg32(t0, *(uint32_t *)(t1 + t2));
606 break;
607 case INDEX_op_st8_i32:
608 t0 = tci_read_r8(&tb_ptr);
609 t1 = tci_read_r(&tb_ptr);
610 t2 = tci_read_s32(&tb_ptr);
611 *(uint8_t *)(t1 + t2) = t0;
612 break;
613 case INDEX_op_st16_i32:
614 t0 = tci_read_r16(&tb_ptr);
615 t1 = tci_read_r(&tb_ptr);
616 t2 = tci_read_s32(&tb_ptr);
617 *(uint16_t *)(t1 + t2) = t0;
618 break;
619 case INDEX_op_st_i32:
620 t0 = tci_read_r32(&tb_ptr);
621 t1 = tci_read_r(&tb_ptr);
622 t2 = tci_read_s32(&tb_ptr);
623 assert(t1 != sp_value || (int32_t)t2 < 0);
624 *(uint32_t *)(t1 + t2) = t0;
625 break;
626
627 /* Arithmetic operations (32 bit). */
628
629 case INDEX_op_add_i32:
630 t0 = *tb_ptr++;
631 t1 = tci_read_ri32(&tb_ptr);
632 t2 = tci_read_ri32(&tb_ptr);
633 tci_write_reg32(t0, t1 + t2);
634 break;
635 case INDEX_op_sub_i32:
636 t0 = *tb_ptr++;
637 t1 = tci_read_ri32(&tb_ptr);
638 t2 = tci_read_ri32(&tb_ptr);
639 tci_write_reg32(t0, t1 - t2);
640 break;
641 case INDEX_op_mul_i32:
642 t0 = *tb_ptr++;
643 t1 = tci_read_ri32(&tb_ptr);
644 t2 = tci_read_ri32(&tb_ptr);
645 tci_write_reg32(t0, t1 * t2);
646 break;
647 #if TCG_TARGET_HAS_div_i32
648 case INDEX_op_div_i32:
649 t0 = *tb_ptr++;
650 t1 = tci_read_ri32(&tb_ptr);
651 t2 = tci_read_ri32(&tb_ptr);
652 tci_write_reg32(t0, (int32_t)t1 / (int32_t)t2);
653 break;
654 case INDEX_op_divu_i32:
655 t0 = *tb_ptr++;
656 t1 = tci_read_ri32(&tb_ptr);
657 t2 = tci_read_ri32(&tb_ptr);
658 tci_write_reg32(t0, t1 / t2);
659 break;
660 case INDEX_op_rem_i32:
661 t0 = *tb_ptr++;
662 t1 = tci_read_ri32(&tb_ptr);
663 t2 = tci_read_ri32(&tb_ptr);
664 tci_write_reg32(t0, (int32_t)t1 % (int32_t)t2);
665 break;
666 case INDEX_op_remu_i32:
667 t0 = *tb_ptr++;
668 t1 = tci_read_ri32(&tb_ptr);
669 t2 = tci_read_ri32(&tb_ptr);
670 tci_write_reg32(t0, t1 % t2);
671 break;
672 #elif TCG_TARGET_HAS_div2_i32
673 case INDEX_op_div2_i32:
674 case INDEX_op_divu2_i32:
675 TODO();
676 break;
677 #endif
678 case INDEX_op_and_i32:
679 t0 = *tb_ptr++;
680 t1 = tci_read_ri32(&tb_ptr);
681 t2 = tci_read_ri32(&tb_ptr);
682 tci_write_reg32(t0, t1 & t2);
683 break;
684 case INDEX_op_or_i32:
685 t0 = *tb_ptr++;
686 t1 = tci_read_ri32(&tb_ptr);
687 t2 = tci_read_ri32(&tb_ptr);
688 tci_write_reg32(t0, t1 | t2);
689 break;
690 case INDEX_op_xor_i32:
691 t0 = *tb_ptr++;
692 t1 = tci_read_ri32(&tb_ptr);
693 t2 = tci_read_ri32(&tb_ptr);
694 tci_write_reg32(t0, t1 ^ t2);
695 break;
696
697 /* Shift/rotate operations (32 bit). */
698
699 case INDEX_op_shl_i32:
700 t0 = *tb_ptr++;
701 t1 = tci_read_ri32(&tb_ptr);
702 t2 = tci_read_ri32(&tb_ptr);
703 tci_write_reg32(t0, t1 << (t2 & 31));
704 break;
705 case INDEX_op_shr_i32:
706 t0 = *tb_ptr++;
707 t1 = tci_read_ri32(&tb_ptr);
708 t2 = tci_read_ri32(&tb_ptr);
709 tci_write_reg32(t0, t1 >> (t2 & 31));
710 break;
711 case INDEX_op_sar_i32:
712 t0 = *tb_ptr++;
713 t1 = tci_read_ri32(&tb_ptr);
714 t2 = tci_read_ri32(&tb_ptr);
715 tci_write_reg32(t0, ((int32_t)t1 >> (t2 & 31)));
716 break;
717 #if TCG_TARGET_HAS_rot_i32
718 case INDEX_op_rotl_i32:
719 t0 = *tb_ptr++;
720 t1 = tci_read_ri32(&tb_ptr);
721 t2 = tci_read_ri32(&tb_ptr);
722 tci_write_reg32(t0, rol32(t1, t2 & 31));
723 break;
724 case INDEX_op_rotr_i32:
725 t0 = *tb_ptr++;
726 t1 = tci_read_ri32(&tb_ptr);
727 t2 = tci_read_ri32(&tb_ptr);
728 tci_write_reg32(t0, ror32(t1, t2 & 31));
729 break;
730 #endif
731 #if TCG_TARGET_HAS_deposit_i32
732 case INDEX_op_deposit_i32:
733 t0 = *tb_ptr++;
734 t1 = tci_read_r32(&tb_ptr);
735 t2 = tci_read_r32(&tb_ptr);
736 tmp16 = *tb_ptr++;
737 tmp8 = *tb_ptr++;
738 tmp32 = (((1 << tmp8) - 1) << tmp16);
739 tci_write_reg32(t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32));
740 break;
741 #endif
742 case INDEX_op_brcond_i32:
743 t0 = tci_read_r32(&tb_ptr);
744 t1 = tci_read_ri32(&tb_ptr);
745 condition = *tb_ptr++;
746 label = tci_read_label(&tb_ptr);
747 if (tci_compare32(t0, t1, condition)) {
748 assert(tb_ptr == old_code_ptr + op_size);
749 tb_ptr = (uint8_t *)label;
750 continue;
751 }
752 break;
753 #if TCG_TARGET_REG_BITS == 32
754 case INDEX_op_add2_i32:
755 t0 = *tb_ptr++;
756 t1 = *tb_ptr++;
757 tmp64 = tci_read_r64(&tb_ptr);
758 tmp64 += tci_read_r64(&tb_ptr);
759 tci_write_reg64(t1, t0, tmp64);
760 break;
761 case INDEX_op_sub2_i32:
762 t0 = *tb_ptr++;
763 t1 = *tb_ptr++;
764 tmp64 = tci_read_r64(&tb_ptr);
765 tmp64 -= tci_read_r64(&tb_ptr);
766 tci_write_reg64(t1, t0, tmp64);
767 break;
768 case INDEX_op_brcond2_i32:
769 tmp64 = tci_read_r64(&tb_ptr);
770 v64 = tci_read_ri64(&tb_ptr);
771 condition = *tb_ptr++;
772 label = tci_read_label(&tb_ptr);
773 if (tci_compare64(tmp64, v64, condition)) {
774 assert(tb_ptr == old_code_ptr + op_size);
775 tb_ptr = (uint8_t *)label;
776 continue;
777 }
778 break;
779 case INDEX_op_mulu2_i32:
780 t0 = *tb_ptr++;
781 t1 = *tb_ptr++;
782 t2 = tci_read_r32(&tb_ptr);
783 tmp64 = tci_read_r32(&tb_ptr);
784 tci_write_reg64(t1, t0, t2 * tmp64);
785 break;
786 #endif /* TCG_TARGET_REG_BITS == 32 */
787 #if TCG_TARGET_HAS_ext8s_i32
788 case INDEX_op_ext8s_i32:
789 t0 = *tb_ptr++;
790 t1 = tci_read_r8s(&tb_ptr);
791 tci_write_reg32(t0, t1);
792 break;
793 #endif
794 #if TCG_TARGET_HAS_ext16s_i32
795 case INDEX_op_ext16s_i32:
796 t0 = *tb_ptr++;
797 t1 = tci_read_r16s(&tb_ptr);
798 tci_write_reg32(t0, t1);
799 break;
800 #endif
801 #if TCG_TARGET_HAS_ext8u_i32
802 case INDEX_op_ext8u_i32:
803 t0 = *tb_ptr++;
804 t1 = tci_read_r8(&tb_ptr);
805 tci_write_reg32(t0, t1);
806 break;
807 #endif
808 #if TCG_TARGET_HAS_ext16u_i32
809 case INDEX_op_ext16u_i32:
810 t0 = *tb_ptr++;
811 t1 = tci_read_r16(&tb_ptr);
812 tci_write_reg32(t0, t1);
813 break;
814 #endif
815 #if TCG_TARGET_HAS_bswap16_i32
816 case INDEX_op_bswap16_i32:
817 t0 = *tb_ptr++;
818 t1 = tci_read_r16(&tb_ptr);
819 tci_write_reg32(t0, bswap16(t1));
820 break;
821 #endif
822 #if TCG_TARGET_HAS_bswap32_i32
823 case INDEX_op_bswap32_i32:
824 t0 = *tb_ptr++;
825 t1 = tci_read_r32(&tb_ptr);
826 tci_write_reg32(t0, bswap32(t1));
827 break;
828 #endif
829 #if TCG_TARGET_HAS_not_i32
830 case INDEX_op_not_i32:
831 t0 = *tb_ptr++;
832 t1 = tci_read_r32(&tb_ptr);
833 tci_write_reg32(t0, ~t1);
834 break;
835 #endif
836 #if TCG_TARGET_HAS_neg_i32
837 case INDEX_op_neg_i32:
838 t0 = *tb_ptr++;
839 t1 = tci_read_r32(&tb_ptr);
840 tci_write_reg32(t0, -t1);
841 break;
842 #endif
843 #if TCG_TARGET_REG_BITS == 64
844 case INDEX_op_mov_i64:
845 t0 = *tb_ptr++;
846 t1 = tci_read_r64(&tb_ptr);
847 tci_write_reg64(t0, t1);
848 break;
849 case INDEX_op_movi_i64:
850 t0 = *tb_ptr++;
851 t1 = tci_read_i64(&tb_ptr);
852 tci_write_reg64(t0, t1);
853 break;
854
855 /* Load/store operations (64 bit). */
856
857 case INDEX_op_ld8u_i64:
858 t0 = *tb_ptr++;
859 t1 = tci_read_r(&tb_ptr);
860 t2 = tci_read_s32(&tb_ptr);
861 tci_write_reg8(t0, *(uint8_t *)(t1 + t2));
862 break;
863 case INDEX_op_ld8s_i64:
864 case INDEX_op_ld16u_i64:
865 case INDEX_op_ld16s_i64:
866 TODO();
867 break;
868 case INDEX_op_ld32u_i64:
869 t0 = *tb_ptr++;
870 t1 = tci_read_r(&tb_ptr);
871 t2 = tci_read_s32(&tb_ptr);
872 tci_write_reg32(t0, *(uint32_t *)(t1 + t2));
873 break;
874 case INDEX_op_ld32s_i64:
875 t0 = *tb_ptr++;
876 t1 = tci_read_r(&tb_ptr);
877 t2 = tci_read_s32(&tb_ptr);
878 tci_write_reg32s(t0, *(int32_t *)(t1 + t2));
879 break;
880 case INDEX_op_ld_i64:
881 t0 = *tb_ptr++;
882 t1 = tci_read_r(&tb_ptr);
883 t2 = tci_read_s32(&tb_ptr);
884 tci_write_reg64(t0, *(uint64_t *)(t1 + t2));
885 break;
886 case INDEX_op_st8_i64:
887 t0 = tci_read_r8(&tb_ptr);
888 t1 = tci_read_r(&tb_ptr);
889 t2 = tci_read_s32(&tb_ptr);
890 *(uint8_t *)(t1 + t2) = t0;
891 break;
892 case INDEX_op_st16_i64:
893 t0 = tci_read_r16(&tb_ptr);
894 t1 = tci_read_r(&tb_ptr);
895 t2 = tci_read_s32(&tb_ptr);
896 *(uint16_t *)(t1 + t2) = t0;
897 break;
898 case INDEX_op_st32_i64:
899 t0 = tci_read_r32(&tb_ptr);
900 t1 = tci_read_r(&tb_ptr);
901 t2 = tci_read_s32(&tb_ptr);
902 *(uint32_t *)(t1 + t2) = t0;
903 break;
904 case INDEX_op_st_i64:
905 t0 = tci_read_r64(&tb_ptr);
906 t1 = tci_read_r(&tb_ptr);
907 t2 = tci_read_s32(&tb_ptr);
908 assert(t1 != sp_value || (int32_t)t2 < 0);
909 *(uint64_t *)(t1 + t2) = t0;
910 break;
911
912 /* Arithmetic operations (64 bit). */
913
914 case INDEX_op_add_i64:
915 t0 = *tb_ptr++;
916 t1 = tci_read_ri64(&tb_ptr);
917 t2 = tci_read_ri64(&tb_ptr);
918 tci_write_reg64(t0, t1 + t2);
919 break;
920 case INDEX_op_sub_i64:
921 t0 = *tb_ptr++;
922 t1 = tci_read_ri64(&tb_ptr);
923 t2 = tci_read_ri64(&tb_ptr);
924 tci_write_reg64(t0, t1 - t2);
925 break;
926 case INDEX_op_mul_i64:
927 t0 = *tb_ptr++;
928 t1 = tci_read_ri64(&tb_ptr);
929 t2 = tci_read_ri64(&tb_ptr);
930 tci_write_reg64(t0, t1 * t2);
931 break;
932 #if TCG_TARGET_HAS_div_i64
933 case INDEX_op_div_i64:
934 case INDEX_op_divu_i64:
935 case INDEX_op_rem_i64:
936 case INDEX_op_remu_i64:
937 TODO();
938 break;
939 #elif TCG_TARGET_HAS_div2_i64
940 case INDEX_op_div2_i64:
941 case INDEX_op_divu2_i64:
942 TODO();
943 break;
944 #endif
945 case INDEX_op_and_i64:
946 t0 = *tb_ptr++;
947 t1 = tci_read_ri64(&tb_ptr);
948 t2 = tci_read_ri64(&tb_ptr);
949 tci_write_reg64(t0, t1 & t2);
950 break;
951 case INDEX_op_or_i64:
952 t0 = *tb_ptr++;
953 t1 = tci_read_ri64(&tb_ptr);
954 t2 = tci_read_ri64(&tb_ptr);
955 tci_write_reg64(t0, t1 | t2);
956 break;
957 case INDEX_op_xor_i64:
958 t0 = *tb_ptr++;
959 t1 = tci_read_ri64(&tb_ptr);
960 t2 = tci_read_ri64(&tb_ptr);
961 tci_write_reg64(t0, t1 ^ t2);
962 break;
963
964 /* Shift/rotate operations (64 bit). */
965
966 case INDEX_op_shl_i64:
967 t0 = *tb_ptr++;
968 t1 = tci_read_ri64(&tb_ptr);
969 t2 = tci_read_ri64(&tb_ptr);
970 tci_write_reg64(t0, t1 << (t2 & 63));
971 break;
972 case INDEX_op_shr_i64:
973 t0 = *tb_ptr++;
974 t1 = tci_read_ri64(&tb_ptr);
975 t2 = tci_read_ri64(&tb_ptr);
976 tci_write_reg64(t0, t1 >> (t2 & 63));
977 break;
978 case INDEX_op_sar_i64:
979 t0 = *tb_ptr++;
980 t1 = tci_read_ri64(&tb_ptr);
981 t2 = tci_read_ri64(&tb_ptr);
982 tci_write_reg64(t0, ((int64_t)t1 >> (t2 & 63)));
983 break;
984 #if TCG_TARGET_HAS_rot_i64
985 case INDEX_op_rotl_i64:
986 t0 = *tb_ptr++;
987 t1 = tci_read_ri64(&tb_ptr);
988 t2 = tci_read_ri64(&tb_ptr);
989 tci_write_reg64(t0, rol64(t1, t2 & 63));
990 break;
991 case INDEX_op_rotr_i64:
992 t0 = *tb_ptr++;
993 t1 = tci_read_ri64(&tb_ptr);
994 t2 = tci_read_ri64(&tb_ptr);
995 tci_write_reg64(t0, ror64(t1, t2 & 63));
996 break;
997 #endif
998 #if TCG_TARGET_HAS_deposit_i64
999 case INDEX_op_deposit_i64:
1000 t0 = *tb_ptr++;
1001 t1 = tci_read_r64(&tb_ptr);
1002 t2 = tci_read_r64(&tb_ptr);
1003 tmp16 = *tb_ptr++;
1004 tmp8 = *tb_ptr++;
1005 tmp64 = (((1ULL << tmp8) - 1) << tmp16);
1006 tci_write_reg64(t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64));
1007 break;
1008 #endif
1009 case INDEX_op_brcond_i64:
1010 t0 = tci_read_r64(&tb_ptr);
1011 t1 = tci_read_ri64(&tb_ptr);
1012 condition = *tb_ptr++;
1013 label = tci_read_label(&tb_ptr);
1014 if (tci_compare64(t0, t1, condition)) {
1015 assert(tb_ptr == old_code_ptr + op_size);
1016 tb_ptr = (uint8_t *)label;
1017 continue;
1018 }
1019 break;
1020 #if TCG_TARGET_HAS_ext8u_i64
1021 case INDEX_op_ext8u_i64:
1022 t0 = *tb_ptr++;
1023 t1 = tci_read_r8(&tb_ptr);
1024 tci_write_reg64(t0, t1);
1025 break;
1026 #endif
1027 #if TCG_TARGET_HAS_ext8s_i64
1028 case INDEX_op_ext8s_i64:
1029 t0 = *tb_ptr++;
1030 t1 = tci_read_r8s(&tb_ptr);
1031 tci_write_reg64(t0, t1);
1032 break;
1033 #endif
1034 #if TCG_TARGET_HAS_ext16s_i64
1035 case INDEX_op_ext16s_i64:
1036 t0 = *tb_ptr++;
1037 t1 = tci_read_r16s(&tb_ptr);
1038 tci_write_reg64(t0, t1);
1039 break;
1040 #endif
1041 #if TCG_TARGET_HAS_ext16u_i64
1042 case INDEX_op_ext16u_i64:
1043 t0 = *tb_ptr++;
1044 t1 = tci_read_r16(&tb_ptr);
1045 tci_write_reg64(t0, t1);
1046 break;
1047 #endif
1048 #if TCG_TARGET_HAS_ext32s_i64
1049 case INDEX_op_ext32s_i64:
1050 t0 = *tb_ptr++;
1051 t1 = tci_read_r32s(&tb_ptr);
1052 tci_write_reg64(t0, t1);
1053 break;
1054 #endif
1055 #if TCG_TARGET_HAS_ext32u_i64
1056 case INDEX_op_ext32u_i64:
1057 t0 = *tb_ptr++;
1058 t1 = tci_read_r32(&tb_ptr);
1059 tci_write_reg64(t0, t1);
1060 break;
1061 #endif
1062 #if TCG_TARGET_HAS_bswap16_i64
1063 case INDEX_op_bswap16_i64:
1064 TODO();
1065 t0 = *tb_ptr++;
1066 t1 = tci_read_r16(&tb_ptr);
1067 tci_write_reg64(t0, bswap16(t1));
1068 break;
1069 #endif
1070 #if TCG_TARGET_HAS_bswap32_i64
1071 case INDEX_op_bswap32_i64:
1072 t0 = *tb_ptr++;
1073 t1 = tci_read_r32(&tb_ptr);
1074 tci_write_reg64(t0, bswap32(t1));
1075 break;
1076 #endif
1077 #if TCG_TARGET_HAS_bswap64_i64
1078 case INDEX_op_bswap64_i64:
1079 t0 = *tb_ptr++;
1080 t1 = tci_read_r64(&tb_ptr);
1081 tci_write_reg64(t0, bswap64(t1));
1082 break;
1083 #endif
1084 #if TCG_TARGET_HAS_not_i64
1085 case INDEX_op_not_i64:
1086 t0 = *tb_ptr++;
1087 t1 = tci_read_r64(&tb_ptr);
1088 tci_write_reg64(t0, ~t1);
1089 break;
1090 #endif
1091 #if TCG_TARGET_HAS_neg_i64
1092 case INDEX_op_neg_i64:
1093 t0 = *tb_ptr++;
1094 t1 = tci_read_r64(&tb_ptr);
1095 tci_write_reg64(t0, -t1);
1096 break;
1097 #endif
1098 #endif /* TCG_TARGET_REG_BITS == 64 */
1099
1100 /* QEMU specific operations. */
1101
1102 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
1103 case INDEX_op_debug_insn_start:
1104 TODO();
1105 break;
1106 #else
1107 case INDEX_op_debug_insn_start:
1108 TODO();
1109 break;
1110 #endif
1111 case INDEX_op_exit_tb:
1112 next_tb = *(uint64_t *)tb_ptr;
1113 goto exit;
1114 break;
1115 case INDEX_op_goto_tb:
1116 t0 = tci_read_i32(&tb_ptr);
1117 assert(tb_ptr == old_code_ptr + op_size);
1118 tb_ptr += (int32_t)t0;
1119 continue;
1120 case INDEX_op_qemu_ld_i32:
1121 t0 = *tb_ptr++;
1122 taddr = tci_read_ulong(&tb_ptr);
1123 memop = tci_read_i(&tb_ptr);
1124 switch (memop) {
1125 case MO_UB:
1126 tmp32 = qemu_ld_ub;
1127 break;
1128 case MO_SB:
1129 tmp32 = (int8_t)qemu_ld_ub;
1130 break;
1131 case MO_LEUW:
1132 tmp32 = qemu_ld_leuw;
1133 break;
1134 case MO_LESW:
1135 tmp32 = (int16_t)qemu_ld_leuw;
1136 break;
1137 case MO_LEUL:
1138 tmp32 = qemu_ld_leul;
1139 break;
1140 case MO_BEUW:
1141 tmp32 = qemu_ld_beuw;
1142 break;
1143 case MO_BESW:
1144 tmp32 = (int16_t)qemu_ld_beuw;
1145 break;
1146 case MO_BEUL:
1147 tmp32 = qemu_ld_beul;
1148 break;
1149 default:
1150 tcg_abort();
1151 }
1152 tci_write_reg(t0, tmp32);
1153 break;
1154 case INDEX_op_qemu_ld_i64:
1155 t0 = *tb_ptr++;
1156 if (TCG_TARGET_REG_BITS == 32) {
1157 t1 = *tb_ptr++;
1158 }
1159 taddr = tci_read_ulong(&tb_ptr);
1160 memop = tci_read_i(&tb_ptr);
1161 switch (memop) {
1162 case MO_UB:
1163 tmp64 = qemu_ld_ub;
1164 break;
1165 case MO_SB:
1166 tmp64 = (int8_t)qemu_ld_ub;
1167 break;
1168 case MO_LEUW:
1169 tmp64 = qemu_ld_leuw;
1170 break;
1171 case MO_LESW:
1172 tmp64 = (int16_t)qemu_ld_leuw;
1173 break;
1174 case MO_LEUL:
1175 tmp64 = qemu_ld_leul;
1176 break;
1177 case MO_LESL:
1178 tmp64 = (int32_t)qemu_ld_leul;
1179 break;
1180 case MO_LEQ:
1181 tmp64 = qemu_ld_leq;
1182 break;
1183 case MO_BEUW:
1184 tmp64 = qemu_ld_beuw;
1185 break;
1186 case MO_BESW:
1187 tmp64 = (int16_t)qemu_ld_beuw;
1188 break;
1189 case MO_BEUL:
1190 tmp64 = qemu_ld_beul;
1191 break;
1192 case MO_BESL:
1193 tmp64 = (int32_t)qemu_ld_beul;
1194 break;
1195 case MO_BEQ:
1196 tmp64 = qemu_ld_beq;
1197 break;
1198 default:
1199 tcg_abort();
1200 }
1201 tci_write_reg(t0, tmp64);
1202 if (TCG_TARGET_REG_BITS == 32) {
1203 tci_write_reg(t1, tmp64 >> 32);
1204 }
1205 break;
1206 case INDEX_op_qemu_st_i32:
1207 t0 = tci_read_r(&tb_ptr);
1208 taddr = tci_read_ulong(&tb_ptr);
1209 memop = tci_read_i(&tb_ptr);
1210 switch (memop) {
1211 case MO_UB:
1212 qemu_st_b(t0);
1213 break;
1214 case MO_LEUW:
1215 qemu_st_lew(t0);
1216 break;
1217 case MO_LEUL:
1218 qemu_st_lel(t0);
1219 break;
1220 case MO_BEUW:
1221 qemu_st_bew(t0);
1222 break;
1223 case MO_BEUL:
1224 qemu_st_bel(t0);
1225 break;
1226 default:
1227 tcg_abort();
1228 }
1229 break;
1230 case INDEX_op_qemu_st_i64:
1231 tmp64 = tci_read_r64(&tb_ptr);
1232 taddr = tci_read_ulong(&tb_ptr);
1233 memop = tci_read_i(&tb_ptr);
1234 switch (memop) {
1235 case MO_UB:
1236 qemu_st_b(tmp64);
1237 break;
1238 case MO_LEUW:
1239 qemu_st_lew(tmp64);
1240 break;
1241 case MO_LEUL:
1242 qemu_st_lel(tmp64);
1243 break;
1244 case MO_LEQ:
1245 qemu_st_leq(tmp64);
1246 break;
1247 case MO_BEUW:
1248 qemu_st_bew(tmp64);
1249 break;
1250 case MO_BEUL:
1251 qemu_st_bel(tmp64);
1252 break;
1253 case MO_BEQ:
1254 qemu_st_beq(tmp64);
1255 break;
1256 default:
1257 tcg_abort();
1258 }
1259 break;
1260 default:
1261 TODO();
1262 break;
1263 }
1264 assert(tb_ptr == old_code_ptr + op_size);
1265 }
1266 exit:
1267 return next_tb;
1268 }
AR7 emulation for QEMU