4 * Copyright (c) 2005 Samuel Tardieu
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "exec/helper-proto.h"
22 #include "exec/cpu_ldst.h"
24 #ifndef CONFIG_USER_ONLY
26 void tlb_fill(CPUState
*cs
, target_ulong addr
, int is_write
, int mmu_idx
,
31 ret
= superh_cpu_handle_mmu_fault(cs
, addr
, is_write
, mmu_idx
);
33 /* now we have a real cpu fault */
35 cpu_restore_state(cs
, retaddr
);
43 #ifdef CONFIG_USER_ONLY
44 void QEMU_NORETURN
helper_ldtlb(CPUSH4State
*env
)
46 void helper_ldtlb(CPUSH4State
*env
)
49 #ifdef CONFIG_USER_ONLY
50 SuperHCPU
*cpu
= sh_env_get_cpu(env
);
53 cpu_abort(CPU(cpu
), "Unhandled ldtlb");
59 static inline void QEMU_NORETURN
raise_exception(CPUSH4State
*env
, int index
,
62 CPUState
*cs
= CPU(sh_env_get_cpu(env
));
64 cs
->exception_index
= index
;
66 cpu_restore_state(cs
, retaddr
);
71 void QEMU_NORETURN
helper_raise_illegal_instruction(CPUSH4State
*env
)
73 raise_exception(env
, 0x180, 0);
76 void QEMU_NORETURN
helper_raise_slot_illegal_instruction(CPUSH4State
*env
)
78 raise_exception(env
, 0x1a0, 0);
81 void QEMU_NORETURN
helper_raise_fpu_disable(CPUSH4State
*env
)
83 raise_exception(env
, 0x800, 0);
86 void QEMU_NORETURN
helper_raise_slot_fpu_disable(CPUSH4State
*env
)
88 raise_exception(env
, 0x820, 0);
91 void QEMU_NORETURN
helper_debug(CPUSH4State
*env
)
93 raise_exception(env
, EXCP_DEBUG
, 0);
96 void QEMU_NORETURN
helper_sleep(CPUSH4State
*env
)
98 CPUState
*cs
= CPU(sh_env_get_cpu(env
));
102 raise_exception(env
, EXCP_HLT
, 0);
105 void QEMU_NORETURN
helper_trapa(CPUSH4State
*env
, uint32_t tra
)
108 raise_exception(env
, 0x160, 0);
111 void helper_movcal(CPUSH4State
*env
, uint32_t address
, uint32_t value
)
113 if (cpu_sh4_is_cached (env
, address
))
115 memory_content
*r
= malloc (sizeof(memory_content
));
116 r
->address
= address
;
120 *(env
->movcal_backup_tail
) = r
;
121 env
->movcal_backup_tail
= &(r
->next
);
125 void helper_discard_movcal_backup(CPUSH4State
*env
)
127 memory_content
*current
= env
->movcal_backup
;
131 memory_content
*next
= current
->next
;
133 env
->movcal_backup
= current
= next
;
135 env
->movcal_backup_tail
= &(env
->movcal_backup
);
139 void helper_ocbi(CPUSH4State
*env
, uint32_t address
)
141 memory_content
**current
= &(env
->movcal_backup
);
144 uint32_t a
= (*current
)->address
;
145 if ((a
& ~0x1F) == (address
& ~0x1F))
147 memory_content
*next
= (*current
)->next
;
148 cpu_stl_data(env
, a
, (*current
)->value
);
152 env
->movcal_backup_tail
= current
;
162 #define T (env->sr & SR_T)
163 #define Q (env->sr & SR_Q ? 1 : 0)
164 #define M (env->sr & SR_M ? 1 : 0)
165 #define SETT env->sr |= SR_T
166 #define CLRT env->sr &= ~SR_T
167 #define SETQ env->sr |= SR_Q
168 #define CLRQ env->sr &= ~SR_Q
169 #define SETM env->sr |= SR_M
170 #define CLRM env->sr &= ~SR_M
172 uint32_t helper_div1(CPUSH4State
*env
, uint32_t arg0
, uint32_t arg1
)
175 uint8_t old_q
, tmp1
= 0xff;
177 //printf("div1 arg0=0x%08x arg1=0x%08x M=%d Q=%d T=%d\n", arg0, arg1, M, Q, T);
179 if ((0x80000000 & arg1
) != 0)
276 //printf("Output: arg1=0x%08x M=%d Q=%d T=%d\n", arg1, M, Q, T);
280 void helper_macl(CPUSH4State
*env
, uint32_t arg0
, uint32_t arg1
)
284 res
= ((uint64_t) env
->mach
<< 32) | env
->macl
;
285 res
+= (int64_t) (int32_t) arg0
*(int64_t) (int32_t) arg1
;
286 env
->mach
= (res
>> 32) & 0xffffffff;
287 env
->macl
= res
& 0xffffffff;
288 if (env
->sr
& SR_S
) {
290 env
->mach
|= 0xffff0000;
292 env
->mach
&= 0x00007fff;
296 void helper_macw(CPUSH4State
*env
, uint32_t arg0
, uint32_t arg1
)
300 res
= ((uint64_t) env
->mach
<< 32) | env
->macl
;
301 res
+= (int64_t) (int16_t) arg0
*(int64_t) (int16_t) arg1
;
302 env
->mach
= (res
>> 32) & 0xffffffff;
303 env
->macl
= res
& 0xffffffff;
304 if (env
->sr
& SR_S
) {
305 if (res
< -0x80000000) {
307 env
->macl
= 0x80000000;
308 } else if (res
> 0x000000007fffffff) {
310 env
->macl
= 0x7fffffff;
315 static inline void set_t(CPUSH4State
*env
)
320 static inline void clr_t(CPUSH4State
*env
)
325 void helper_ld_fpscr(CPUSH4State
*env
, uint32_t val
)
327 env
->fpscr
= val
& FPSCR_MASK
;
328 if ((val
& FPSCR_RM_MASK
) == FPSCR_RM_ZERO
) {
329 set_float_rounding_mode(float_round_to_zero
, &env
->fp_status
);
331 set_float_rounding_mode(float_round_nearest_even
, &env
->fp_status
);
333 set_flush_to_zero((val
& FPSCR_DN
) != 0, &env
->fp_status
);
336 static void update_fpscr(CPUSH4State
*env
, uintptr_t retaddr
)
338 int xcpt
, cause
, enable
;
340 xcpt
= get_float_exception_flags(&env
->fp_status
);
342 /* Clear the flag entries */
343 env
->fpscr
&= ~FPSCR_FLAG_MASK
;
345 if (unlikely(xcpt
)) {
346 if (xcpt
& float_flag_invalid
) {
347 env
->fpscr
|= FPSCR_FLAG_V
;
349 if (xcpt
& float_flag_divbyzero
) {
350 env
->fpscr
|= FPSCR_FLAG_Z
;
352 if (xcpt
& float_flag_overflow
) {
353 env
->fpscr
|= FPSCR_FLAG_O
;
355 if (xcpt
& float_flag_underflow
) {
356 env
->fpscr
|= FPSCR_FLAG_U
;
358 if (xcpt
& float_flag_inexact
) {
359 env
->fpscr
|= FPSCR_FLAG_I
;
362 /* Accumulate in cause entries */
363 env
->fpscr
|= (env
->fpscr
& FPSCR_FLAG_MASK
)
364 << (FPSCR_CAUSE_SHIFT
- FPSCR_FLAG_SHIFT
);
366 /* Generate an exception if enabled */
367 cause
= (env
->fpscr
& FPSCR_CAUSE_MASK
) >> FPSCR_CAUSE_SHIFT
;
368 enable
= (env
->fpscr
& FPSCR_ENABLE_MASK
) >> FPSCR_ENABLE_SHIFT
;
369 if (cause
& enable
) {
370 raise_exception(env
, 0x120, retaddr
);
375 float32
helper_fabs_FT(float32 t0
)
377 return float32_abs(t0
);
380 float64
helper_fabs_DT(float64 t0
)
382 return float64_abs(t0
);
385 float32
helper_fadd_FT(CPUSH4State
*env
, float32 t0
, float32 t1
)
387 set_float_exception_flags(0, &env
->fp_status
);
388 t0
= float32_add(t0
, t1
, &env
->fp_status
);
389 update_fpscr(env
, GETPC());
393 float64
helper_fadd_DT(CPUSH4State
*env
, float64 t0
, float64 t1
)
395 set_float_exception_flags(0, &env
->fp_status
);
396 t0
= float64_add(t0
, t1
, &env
->fp_status
);
397 update_fpscr(env
, GETPC());
401 void helper_fcmp_eq_FT(CPUSH4State
*env
, float32 t0
, float32 t1
)
405 set_float_exception_flags(0, &env
->fp_status
);
406 relation
= float32_compare(t0
, t1
, &env
->fp_status
);
407 if (unlikely(relation
== float_relation_unordered
)) {
408 update_fpscr(env
, GETPC());
409 } else if (relation
== float_relation_equal
) {
416 void helper_fcmp_eq_DT(CPUSH4State
*env
, float64 t0
, float64 t1
)
420 set_float_exception_flags(0, &env
->fp_status
);
421 relation
= float64_compare(t0
, t1
, &env
->fp_status
);
422 if (unlikely(relation
== float_relation_unordered
)) {
423 update_fpscr(env
, GETPC());
424 } else if (relation
== float_relation_equal
) {
431 void helper_fcmp_gt_FT(CPUSH4State
*env
, float32 t0
, float32 t1
)
435 set_float_exception_flags(0, &env
->fp_status
);
436 relation
= float32_compare(t0
, t1
, &env
->fp_status
);
437 if (unlikely(relation
== float_relation_unordered
)) {
438 update_fpscr(env
, GETPC());
439 } else if (relation
== float_relation_greater
) {
446 void helper_fcmp_gt_DT(CPUSH4State
*env
, float64 t0
, float64 t1
)
450 set_float_exception_flags(0, &env
->fp_status
);
451 relation
= float64_compare(t0
, t1
, &env
->fp_status
);
452 if (unlikely(relation
== float_relation_unordered
)) {
453 update_fpscr(env
, GETPC());
454 } else if (relation
== float_relation_greater
) {
461 float64
helper_fcnvsd_FT_DT(CPUSH4State
*env
, float32 t0
)
464 set_float_exception_flags(0, &env
->fp_status
);
465 ret
= float32_to_float64(t0
, &env
->fp_status
);
466 update_fpscr(env
, GETPC());
470 float32
helper_fcnvds_DT_FT(CPUSH4State
*env
, float64 t0
)
473 set_float_exception_flags(0, &env
->fp_status
);
474 ret
= float64_to_float32(t0
, &env
->fp_status
);
475 update_fpscr(env
, GETPC());
479 float32
helper_fdiv_FT(CPUSH4State
*env
, float32 t0
, float32 t1
)
481 set_float_exception_flags(0, &env
->fp_status
);
482 t0
= float32_div(t0
, t1
, &env
->fp_status
);
483 update_fpscr(env
, GETPC());
487 float64
helper_fdiv_DT(CPUSH4State
*env
, float64 t0
, float64 t1
)
489 set_float_exception_flags(0, &env
->fp_status
);
490 t0
= float64_div(t0
, t1
, &env
->fp_status
);
491 update_fpscr(env
, GETPC());
495 float32
helper_float_FT(CPUSH4State
*env
, uint32_t t0
)
498 set_float_exception_flags(0, &env
->fp_status
);
499 ret
= int32_to_float32(t0
, &env
->fp_status
);
500 update_fpscr(env
, GETPC());
504 float64
helper_float_DT(CPUSH4State
*env
, uint32_t t0
)
507 set_float_exception_flags(0, &env
->fp_status
);
508 ret
= int32_to_float64(t0
, &env
->fp_status
);
509 update_fpscr(env
, GETPC());
513 float32
helper_fmac_FT(CPUSH4State
*env
, float32 t0
, float32 t1
, float32 t2
)
515 set_float_exception_flags(0, &env
->fp_status
);
516 t0
= float32_muladd(t0
, t1
, t2
, 0, &env
->fp_status
);
517 update_fpscr(env
, GETPC());
521 float32
helper_fmul_FT(CPUSH4State
*env
, float32 t0
, float32 t1
)
523 set_float_exception_flags(0, &env
->fp_status
);
524 t0
= float32_mul(t0
, t1
, &env
->fp_status
);
525 update_fpscr(env
, GETPC());
529 float64
helper_fmul_DT(CPUSH4State
*env
, float64 t0
, float64 t1
)
531 set_float_exception_flags(0, &env
->fp_status
);
532 t0
= float64_mul(t0
, t1
, &env
->fp_status
);
533 update_fpscr(env
, GETPC());
537 float32
helper_fneg_T(float32 t0
)
539 return float32_chs(t0
);
542 float32
helper_fsqrt_FT(CPUSH4State
*env
, float32 t0
)
544 set_float_exception_flags(0, &env
->fp_status
);
545 t0
= float32_sqrt(t0
, &env
->fp_status
);
546 update_fpscr(env
, GETPC());
550 float64
helper_fsqrt_DT(CPUSH4State
*env
, float64 t0
)
552 set_float_exception_flags(0, &env
->fp_status
);
553 t0
= float64_sqrt(t0
, &env
->fp_status
);
554 update_fpscr(env
, GETPC());
558 float32
helper_fsub_FT(CPUSH4State
*env
, float32 t0
, float32 t1
)
560 set_float_exception_flags(0, &env
->fp_status
);
561 t0
= float32_sub(t0
, t1
, &env
->fp_status
);
562 update_fpscr(env
, GETPC());
566 float64
helper_fsub_DT(CPUSH4State
*env
, float64 t0
, float64 t1
)
568 set_float_exception_flags(0, &env
->fp_status
);
569 t0
= float64_sub(t0
, t1
, &env
->fp_status
);
570 update_fpscr(env
, GETPC());
574 uint32_t helper_ftrc_FT(CPUSH4State
*env
, float32 t0
)
577 set_float_exception_flags(0, &env
->fp_status
);
578 ret
= float32_to_int32_round_to_zero(t0
, &env
->fp_status
);
579 update_fpscr(env
, GETPC());
583 uint32_t helper_ftrc_DT(CPUSH4State
*env
, float64 t0
)
586 set_float_exception_flags(0, &env
->fp_status
);
587 ret
= float64_to_int32_round_to_zero(t0
, &env
->fp_status
);
588 update_fpscr(env
, GETPC());
592 void helper_fipr(CPUSH4State
*env
, uint32_t m
, uint32_t n
)
597 bank
= (env
->sr
& FPSCR_FR
) ? 16 : 0;
599 set_float_exception_flags(0, &env
->fp_status
);
601 for (i
= 0 ; i
< 4 ; i
++) {
602 p
= float32_mul(env
->fregs
[bank
+ m
+ i
],
603 env
->fregs
[bank
+ n
+ i
],
605 r
= float32_add(r
, p
, &env
->fp_status
);
607 update_fpscr(env
, GETPC());
609 env
->fregs
[bank
+ n
+ 3] = r
;
612 void helper_ftrv(CPUSH4State
*env
, uint32_t n
)
614 int bank_matrix
, bank_vector
;
619 bank_matrix
= (env
->sr
& FPSCR_FR
) ? 0 : 16;
620 bank_vector
= (env
->sr
& FPSCR_FR
) ? 16 : 0;
621 set_float_exception_flags(0, &env
->fp_status
);
622 for (i
= 0 ; i
< 4 ; i
++) {
624 for (j
= 0 ; j
< 4 ; j
++) {
625 p
= float32_mul(env
->fregs
[bank_matrix
+ 4 * j
+ i
],
626 env
->fregs
[bank_vector
+ j
],
628 r
[i
] = float32_add(r
[i
], p
, &env
->fp_status
);
631 update_fpscr(env
, GETPC());
633 for (i
= 0 ; i
< 4 ; i
++) {
634 env
->fregs
[bank_vector
+ i
] = r
[i
];