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exec/memory: Use struct Object typedef
[qemu/ar7.git] / softmmu / memory.c
blob91f1bf47c301e6618a3ec75449b88684b4c5e7db
1 /*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
14 */
15
16 #include "qemu/osdep.h"
17 #include "qemu/log.h"
18 #include "qapi/error.h"
19 #include "cpu.h"
20 #include "exec/memory.h"
21 #include "exec/address-spaces.h"
22 #include "qapi/visitor.h"
23 #include "qemu/bitops.h"
24 #include "qemu/error-report.h"
25 #include "qemu/main-loop.h"
26 #include "qemu/qemu-print.h"
27 #include "qom/object.h"
28 #include "trace.h"
29
30 #include "exec/memory-internal.h"
31 #include "exec/ram_addr.h"
32 #include "sysemu/kvm.h"
33 #include "sysemu/runstate.h"
34 #include "sysemu/tcg.h"
35 #include "qemu/accel.h"
36 #include "hw/boards.h"
37 #include "migration/vmstate.h"
38
39 //#define DEBUG_UNASSIGNED
40
41 static unsigned memory_region_transaction_depth;
42 static bool memory_region_update_pending;
43 static bool ioeventfd_update_pending;
44 bool global_dirty_log;
45
46 static QTAILQ_HEAD(, MemoryListener) memory_listeners
47 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
48
49 static QTAILQ_HEAD(, AddressSpace) address_spaces
50 = QTAILQ_HEAD_INITIALIZER(address_spaces);
51
52 static GHashTable *flat_views;
53
54 typedef struct AddrRange AddrRange;
55
56 /*
57 * Note that signed integers are needed for negative offsetting in aliases
58 * (large MemoryRegion::alias_offset).
59 */
60 struct AddrRange {
61 Int128 start;
62 Int128 size;
63 };
64
65 static AddrRange addrrange_make(Int128 start, Int128 size)
66 {
67 return (AddrRange) { start, size };
68 }
69
70 static bool addrrange_equal(AddrRange r1, AddrRange r2)
71 {
72 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
73 }
74
75 static Int128 addrrange_end(AddrRange r)
76 {
77 return int128_add(r.start, r.size);
78 }
79
80 static AddrRange addrrange_shift(AddrRange range, Int128 delta)
81 {
82 int128_addto(&range.start, delta);
83 return range;
84 }
85
86 static bool addrrange_contains(AddrRange range, Int128 addr)
87 {
88 return int128_ge(addr, range.start)
89 && int128_lt(addr, addrrange_end(range));
90 }
91
92 static bool addrrange_intersects(AddrRange r1, AddrRange r2)
93 {
94 return addrrange_contains(r1, r2.start)
95 || addrrange_contains(r2, r1.start);
96 }
97
98 static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
99 {
100 Int128 start = int128_max(r1.start, r2.start);
101 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
102 return addrrange_make(start, int128_sub(end, start));
103 }
104
105 enum ListenerDirection { Forward, Reverse };
106
107 #define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
108 do { \
109 MemoryListener *_listener; \
110 \
111 switch (_direction) { \
112 case Forward: \
113 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
114 if (_listener->_callback) { \
115 _listener->_callback(_listener, ##_args); \
116 } \
117 } \
118 break; \
119 case Reverse: \
120 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, link) { \
121 if (_listener->_callback) { \
122 _listener->_callback(_listener, ##_args); \
123 } \
124 } \
125 break; \
126 default: \
127 abort(); \
128 } \
129 } while (0)
130
131 #define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
132 do { \
133 MemoryListener *_listener; \
134 \
135 switch (_direction) { \
136 case Forward: \
137 QTAILQ_FOREACH(_listener, &(_as)->listeners, link_as) { \
138 if (_listener->_callback) { \
139 _listener->_callback(_listener, _section, ##_args); \
140 } \
141 } \
142 break; \
143 case Reverse: \
144 QTAILQ_FOREACH_REVERSE(_listener, &(_as)->listeners, link_as) { \
145 if (_listener->_callback) { \
146 _listener->_callback(_listener, _section, ##_args); \
147 } \
148 } \
149 break; \
150 default: \
151 abort(); \
152 } \
153 } while (0)
154
155 /* No need to ref/unref .mr, the FlatRange keeps it alive. */
156 #define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
157 do { \
158 MemoryRegionSection mrs = section_from_flat_range(fr, \
159 address_space_to_flatview(as)); \
160 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
161 } while(0)
162
163 struct CoalescedMemoryRange {
164 AddrRange addr;
165 QTAILQ_ENTRY(CoalescedMemoryRange) link;
166 };
167
168 struct MemoryRegionIoeventfd {
169 AddrRange addr;
170 bool match_data;
171 uint64_t data;
172 EventNotifier *e;
173 };
174
175 static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd *a,
176 MemoryRegionIoeventfd *b)
177 {
178 if (int128_lt(a->addr.start, b->addr.start)) {
179 return true;
180 } else if (int128_gt(a->addr.start, b->addr.start)) {
181 return false;
182 } else if (int128_lt(a->addr.size, b->addr.size)) {
183 return true;
184 } else if (int128_gt(a->addr.size, b->addr.size)) {
185 return false;
186 } else if (a->match_data < b->match_data) {
187 return true;
188 } else if (a->match_data > b->match_data) {
189 return false;
190 } else if (a->match_data) {
191 if (a->data < b->data) {
192 return true;
193 } else if (a->data > b->data) {
194 return false;
195 }
196 }
197 if (a->e < b->e) {
198 return true;
199 } else if (a->e > b->e) {
200 return false;
201 }
202 return false;
203 }
204
205 static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd *a,
206 MemoryRegionIoeventfd *b)
207 {
208 if (int128_eq(a->addr.start, b->addr.start) &&
209 (!int128_nz(a->addr.size) || !int128_nz(b->addr.size) ||
210 (int128_eq(a->addr.size, b->addr.size) &&
211 (a->match_data == b->match_data) &&
212 ((a->match_data && (a->data == b->data)) || !a->match_data) &&
213 (a->e == b->e))))
214 return true;
215
216 return false;
217 }
218
219 /* Range of memory in the global map. Addresses are absolute. */
220 struct FlatRange {
221 MemoryRegion *mr;
222 hwaddr offset_in_region;
223 AddrRange addr;
224 uint8_t dirty_log_mask;
225 bool romd_mode;
226 bool readonly;
227 bool nonvolatile;
228 };
229
230 #define FOR_EACH_FLAT_RANGE(var, view) \
231 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
232
233 static inline MemoryRegionSection
234 section_from_flat_range(FlatRange *fr, FlatView *fv)
235 {
236 return (MemoryRegionSection) {
237 .mr = fr->mr,
238 .fv = fv,
239 .offset_within_region = fr->offset_in_region,
240 .size = fr->addr.size,
241 .offset_within_address_space = int128_get64(fr->addr.start),
242 .readonly = fr->readonly,
243 .nonvolatile = fr->nonvolatile,
244 };
245 }
246
247 static bool flatrange_equal(FlatRange *a, FlatRange *b)
248 {
249 return a->mr == b->mr
250 && addrrange_equal(a->addr, b->addr)
251 && a->offset_in_region == b->offset_in_region
252 && a->romd_mode == b->romd_mode
253 && a->readonly == b->readonly
254 && a->nonvolatile == b->nonvolatile;
255 }
256
257 static FlatView *flatview_new(MemoryRegion *mr_root)
258 {
259 FlatView *view;
260
261 view = g_new0(FlatView, 1);
262 view->ref = 1;
263 view->root = mr_root;
264 memory_region_ref(mr_root);
265 trace_flatview_new(view, mr_root);
266
267 return view;
268 }
269
270 /* Insert a range into a given position. Caller is responsible for maintaining
271 * sorting order.
272 */
273 static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
274 {
275 if (view->nr == view->nr_allocated) {
276 view->nr_allocated = MAX(2 * view->nr, 10);
277 view->ranges = g_realloc(view->ranges,
278 view->nr_allocated * sizeof(*view->ranges));
279 }
280 memmove(view->ranges + pos + 1, view->ranges + pos,
281 (view->nr - pos) * sizeof(FlatRange));
282 view->ranges[pos] = *range;
283 memory_region_ref(range->mr);
284 ++view->nr;
285 }
286
287 static void flatview_destroy(FlatView *view)
288 {
289 int i;
290
291 trace_flatview_destroy(view, view->root);
292 if (view->dispatch) {
293 address_space_dispatch_free(view->dispatch);
294 }
295 for (i = 0; i < view->nr; i++) {
296 memory_region_unref(view->ranges[i].mr);
297 }
298 g_free(view->ranges);
299 memory_region_unref(view->root);
300 g_free(view);
301 }
302
303 static bool flatview_ref(FlatView *view)
304 {
305 return qatomic_fetch_inc_nonzero(&view->ref) > 0;
306 }
307
308 void flatview_unref(FlatView *view)
309 {
310 if (qatomic_fetch_dec(&view->ref) == 1) {
311 trace_flatview_destroy_rcu(view, view->root);
312 assert(view->root);
313 call_rcu(view, flatview_destroy, rcu);
314 }
315 }
316
317 static bool can_merge(FlatRange *r1, FlatRange *r2)
318 {
319 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
320 && r1->mr == r2->mr
321 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
322 r1->addr.size),
323 int128_make64(r2->offset_in_region))
324 && r1->dirty_log_mask == r2->dirty_log_mask
325 && r1->romd_mode == r2->romd_mode
326 && r1->readonly == r2->readonly
327 && r1->nonvolatile == r2->nonvolatile;
328 }
329
330 /* Attempt to simplify a view by merging adjacent ranges */
331 static void flatview_simplify(FlatView *view)
332 {
333 unsigned i, j, k;
334
335 i = 0;
336 while (i < view->nr) {
337 j = i + 1;
338 while (j < view->nr
339 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
340 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
341 ++j;
342 }
343 ++i;
344 for (k = i; k < j; k++) {
345 memory_region_unref(view->ranges[k].mr);
346 }
347 memmove(&view->ranges[i], &view->ranges[j],
348 (view->nr - j) * sizeof(view->ranges[j]));
349 view->nr -= j - i;
350 }
351 }
352
353 static bool memory_region_big_endian(MemoryRegion *mr)
354 {
355 #ifdef TARGET_WORDS_BIGENDIAN
356 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
357 #else
358 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
359 #endif
360 }
361
362 static void adjust_endianness(MemoryRegion *mr, uint64_t *data, MemOp op)
363 {
364 if ((op & MO_BSWAP) != devend_memop(mr->ops->endianness)) {
365 switch (op & MO_SIZE) {
366 case MO_8:
367 break;
368 case MO_16:
369 *data = bswap16(*data);
370 break;
371 case MO_32:
372 *data = bswap32(*data);
373 break;
374 case MO_64:
375 *data = bswap64(*data);
376 break;
377 default:
378 g_assert_not_reached();
379 }
380 }
381 }
382
383 static inline void memory_region_shift_read_access(uint64_t *value,
384 signed shift,
385 uint64_t mask,
386 uint64_t tmp)
387 {
388 if (shift >= 0) {
389 *value |= (tmp & mask) << shift;
390 } else {
391 *value |= (tmp & mask) >> -shift;
392 }
393 }
394
395 static inline uint64_t memory_region_shift_write_access(uint64_t *value,
396 signed shift,
397 uint64_t mask)
398 {
399 uint64_t tmp;
400
401 if (shift >= 0) {
402 tmp = (*value >> shift) & mask;
403 } else {
404 tmp = (*value << -shift) & mask;
405 }
406
407 return tmp;
408 }
409
410 static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
411 {
412 MemoryRegion *root;
413 hwaddr abs_addr = offset;
414
415 abs_addr += mr->addr;
416 for (root = mr; root->container; ) {
417 root = root->container;
418 abs_addr += root->addr;
419 }
420
421 return abs_addr;
422 }
423
424 static int get_cpu_index(void)
425 {
426 if (current_cpu) {
427 return current_cpu->cpu_index;
428 }
429 return -1;
430 }
431
432 static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
433 hwaddr addr,
434 uint64_t *value,
435 unsigned size,
436 signed shift,
437 uint64_t mask,
438 MemTxAttrs attrs)
439 {
440 uint64_t tmp;
441
442 tmp = mr->ops->read(mr->opaque, addr, size);
443 if (mr->subpage) {
444 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
445 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_READ)) {
446 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
447 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
448 }
449 memory_region_shift_read_access(value, shift, mask, tmp);
450 return MEMTX_OK;
451 }
452
453 static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
454 hwaddr addr,
455 uint64_t *value,
456 unsigned size,
457 signed shift,
458 uint64_t mask,
459 MemTxAttrs attrs)
460 {
461 uint64_t tmp = 0;
462 MemTxResult r;
463
464 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
465 if (mr->subpage) {
466 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
467 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_READ)) {
468 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
469 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
470 }
471 memory_region_shift_read_access(value, shift, mask, tmp);
472 return r;
473 }
474
475 static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
476 hwaddr addr,
477 uint64_t *value,
478 unsigned size,
479 signed shift,
480 uint64_t mask,
481 MemTxAttrs attrs)
482 {
483 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
484
485 if (mr->subpage) {
486 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
487 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_WRITE)) {
488 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
489 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
490 }
491 mr->ops->write(mr->opaque, addr, tmp, size);
492 return MEMTX_OK;
493 }
494
495 static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
496 hwaddr addr,
497 uint64_t *value,
498 unsigned size,
499 signed shift,
500 uint64_t mask,
501 MemTxAttrs attrs)
502 {
503 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
504
505 if (mr->subpage) {
506 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
507 } else if (trace_event_get_state_backends(TRACE_MEMORY_REGION_OPS_WRITE)) {
508 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
509 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
510 }
511 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
512 }
513
514 static MemTxResult access_with_adjusted_size(hwaddr addr,
515 uint64_t *value,
516 unsigned size,
517 unsigned access_size_min,
518 unsigned access_size_max,
519 MemTxResult (*access_fn)
520 (MemoryRegion *mr,
521 hwaddr addr,
522 uint64_t *value,
523 unsigned size,
524 signed shift,
525 uint64_t mask,
526 MemTxAttrs attrs),
527 MemoryRegion *mr,
528 MemTxAttrs attrs)
529 {
530 uint64_t access_mask;
531 unsigned access_size;
532 unsigned i;
533 MemTxResult r = MEMTX_OK;
534
535 if (!access_size_min) {
536 access_size_min = 1;
537 }
538 if (!access_size_max) {
539 access_size_max = 4;
540 }
541
542 /* FIXME: support unaligned access? */
543 access_size = MAX(MIN(size, access_size_max), access_size_min);
544 access_mask = MAKE_64BIT_MASK(0, access_size * 8);
545 if (memory_region_big_endian(mr)) {
546 for (i = 0; i < size; i += access_size) {
547 r |= access_fn(mr, addr + i, value, access_size,
548 (size - access_size - i) * 8, access_mask, attrs);
549 }
550 } else {
551 for (i = 0; i < size; i += access_size) {
552 r |= access_fn(mr, addr + i, value, access_size, i * 8,
553 access_mask, attrs);
554 }
555 }
556 return r;
557 }
558
559 static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
560 {
561 AddressSpace *as;
562
563 while (mr->container) {
564 mr = mr->container;
565 }
566 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
567 if (mr == as->root) {
568 return as;
569 }
570 }
571 return NULL;
572 }
573
574 /* Render a memory region into the global view. Ranges in @view obscure
575 * ranges in @mr.
576 */
577 static void render_memory_region(FlatView *view,
578 MemoryRegion *mr,
579 Int128 base,
580 AddrRange clip,
581 bool readonly,
582 bool nonvolatile)
583 {
584 MemoryRegion *subregion;
585 unsigned i;
586 hwaddr offset_in_region;
587 Int128 remain;
588 Int128 now;
589 FlatRange fr;
590 AddrRange tmp;
591
592 if (!mr->enabled) {
593 return;
594 }
595
596 int128_addto(&base, int128_make64(mr->addr));
597 readonly |= mr->readonly;
598 nonvolatile |= mr->nonvolatile;
599
600 tmp = addrrange_make(base, mr->size);
601
602 if (!addrrange_intersects(tmp, clip)) {
603 return;
604 }
605
606 clip = addrrange_intersection(tmp, clip);
607
608 if (mr->alias) {
609 int128_subfrom(&base, int128_make64(mr->alias->addr));
610 int128_subfrom(&base, int128_make64(mr->alias_offset));
611 render_memory_region(view, mr->alias, base, clip,
612 readonly, nonvolatile);
613 return;
614 }
615
616 /* Render subregions in priority order. */
617 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
618 render_memory_region(view, subregion, base, clip,
619 readonly, nonvolatile);
620 }
621
622 if (!mr->terminates) {
623 return;
624 }
625
626 offset_in_region = int128_get64(int128_sub(clip.start, base));
627 base = clip.start;
628 remain = clip.size;
629
630 fr.mr = mr;
631 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
632 fr.romd_mode = mr->romd_mode;
633 fr.readonly = readonly;
634 fr.nonvolatile = nonvolatile;
635
636 /* Render the region itself into any gaps left by the current view. */
637 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
638 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
639 continue;
640 }
641 if (int128_lt(base, view->ranges[i].addr.start)) {
642 now = int128_min(remain,
643 int128_sub(view->ranges[i].addr.start, base));
644 fr.offset_in_region = offset_in_region;
645 fr.addr = addrrange_make(base, now);
646 flatview_insert(view, i, &fr);
647 ++i;
648 int128_addto(&base, now);
649 offset_in_region += int128_get64(now);
650 int128_subfrom(&remain, now);
651 }
652 now = int128_sub(int128_min(int128_add(base, remain),
653 addrrange_end(view->ranges[i].addr)),
654 base);
655 int128_addto(&base, now);
656 offset_in_region += int128_get64(now);
657 int128_subfrom(&remain, now);
658 }
659 if (int128_nz(remain)) {
660 fr.offset_in_region = offset_in_region;
661 fr.addr = addrrange_make(base, remain);
662 flatview_insert(view, i, &fr);
663 }
664 }
665
666 void flatview_for_each_range(FlatView *fv, flatview_cb cb , void *opaque)
667 {
668 FlatRange *fr;
669
670 assert(fv);
671 assert(cb);
672
673 FOR_EACH_FLAT_RANGE(fr, fv) {
674 if (cb(fr->addr.start, fr->addr.size, fr->mr, opaque))
675 break;
676 }
677 }
678
679 static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
680 {
681 while (mr->enabled) {
682 if (mr->alias) {
683 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
684 /* The alias is included in its entirety. Use it as
685 * the "real" root, so that we can share more FlatViews.
686 */
687 mr = mr->alias;
688 continue;
689 }
690 } else if (!mr->terminates) {
691 unsigned int found = 0;
692 MemoryRegion *child, *next = NULL;
693 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
694 if (child->enabled) {
695 if (++found > 1) {
696 next = NULL;
697 break;
698 }
699 if (!child->addr && int128_ge(mr->size, child->size)) {
700 /* A child is included in its entirety. If it's the only
701 * enabled one, use it in the hope of finding an alias down the
702 * way. This will also let us share FlatViews.
703 */
704 next = child;
705 }
706 }
707 }
708 if (found == 0) {
709 return NULL;
710 }
711 if (next) {
712 mr = next;
713 continue;
714 }
715 }
716
717 return mr;
718 }
719
720 return NULL;
721 }
722
723 /* Render a memory topology into a list of disjoint absolute ranges. */
724 static FlatView *generate_memory_topology(MemoryRegion *mr)
725 {
726 int i;
727 FlatView *view;
728
729 view = flatview_new(mr);
730
731 if (mr) {
732 render_memory_region(view, mr, int128_zero(),
733 addrrange_make(int128_zero(), int128_2_64()),
734 false, false);
735 }
736 flatview_simplify(view);
737
738 view->dispatch = address_space_dispatch_new(view);
739 for (i = 0; i < view->nr; i++) {
740 MemoryRegionSection mrs =
741 section_from_flat_range(&view->ranges[i], view);
742 flatview_add_to_dispatch(view, &mrs);
743 }
744 address_space_dispatch_compact(view->dispatch);
745 g_hash_table_replace(flat_views, mr, view);
746
747 return view;
748 }
749
750 static void address_space_add_del_ioeventfds(AddressSpace *as,
751 MemoryRegionIoeventfd *fds_new,
752 unsigned fds_new_nb,
753 MemoryRegionIoeventfd *fds_old,
754 unsigned fds_old_nb)
755 {
756 unsigned iold, inew;
757 MemoryRegionIoeventfd *fd;
758 MemoryRegionSection section;
759
760 /* Generate a symmetric difference of the old and new fd sets, adding
761 * and deleting as necessary.
762 */
763
764 iold = inew = 0;
765 while (iold < fds_old_nb || inew < fds_new_nb) {
766 if (iold < fds_old_nb
767 && (inew == fds_new_nb
768 || memory_region_ioeventfd_before(&fds_old[iold],
769 &fds_new[inew]))) {
770 fd = &fds_old[iold];
771 section = (MemoryRegionSection) {
772 .fv = address_space_to_flatview(as),
773 .offset_within_address_space = int128_get64(fd->addr.start),
774 .size = fd->addr.size,
775 };
776 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
777 fd->match_data, fd->data, fd->e);
778 ++iold;
779 } else if (inew < fds_new_nb
780 && (iold == fds_old_nb
781 || memory_region_ioeventfd_before(&fds_new[inew],
782 &fds_old[iold]))) {
783 fd = &fds_new[inew];
784 section = (MemoryRegionSection) {
785 .fv = address_space_to_flatview(as),
786 .offset_within_address_space = int128_get64(fd->addr.start),
787 .size = fd->addr.size,
788 };
789 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
790 fd->match_data, fd->data, fd->e);
791 ++inew;
792 } else {
793 ++iold;
794 ++inew;
795 }
796 }
797 }
798
799 FlatView *address_space_get_flatview(AddressSpace *as)
800 {
801 FlatView *view;
802
803 RCU_READ_LOCK_GUARD();
804 do {
805 view = address_space_to_flatview(as);
806 /* If somebody has replaced as->current_map concurrently,
807 * flatview_ref returns false.
808 */
809 } while (!flatview_ref(view));
810 return view;
811 }
812
813 static void address_space_update_ioeventfds(AddressSpace *as)
814 {
815 FlatView *view;
816 FlatRange *fr;
817 unsigned ioeventfd_nb = 0;
818 unsigned ioeventfd_max;
819 MemoryRegionIoeventfd *ioeventfds;
820 AddrRange tmp;
821 unsigned i;
822
823 /*
824 * It is likely that the number of ioeventfds hasn't changed much, so use
825 * the previous size as the starting value, with some headroom to avoid
826 * gratuitous reallocations.
827 */
828 ioeventfd_max = QEMU_ALIGN_UP(as->ioeventfd_nb, 4);
829 ioeventfds = g_new(MemoryRegionIoeventfd, ioeventfd_max);
830
831 view = address_space_get_flatview(as);
832 FOR_EACH_FLAT_RANGE(fr, view) {
833 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
834 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
835 int128_sub(fr->addr.start,
836 int128_make64(fr->offset_in_region)));
837 if (addrrange_intersects(fr->addr, tmp)) {
838 ++ioeventfd_nb;
839 if (ioeventfd_nb > ioeventfd_max) {
840 ioeventfd_max = MAX(ioeventfd_max * 2, 4);
841 ioeventfds = g_realloc(ioeventfds,
842 ioeventfd_max * sizeof(*ioeventfds));
843 }
844 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
845 ioeventfds[ioeventfd_nb-1].addr = tmp;
846 }
847 }
848 }
849
850 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
851 as->ioeventfds, as->ioeventfd_nb);
852
853 g_free(as->ioeventfds);
854 as->ioeventfds = ioeventfds;
855 as->ioeventfd_nb = ioeventfd_nb;
856 flatview_unref(view);
857 }
858
859 /*
860 * Notify the memory listeners about the coalesced IO change events of
861 * range `cmr'. Only the part that has intersection of the specified
862 * FlatRange will be sent.
863 */
864 static void flat_range_coalesced_io_notify(FlatRange *fr, AddressSpace *as,
865 CoalescedMemoryRange *cmr, bool add)
866 {
867 AddrRange tmp;
868
869 tmp = addrrange_shift(cmr->addr,
870 int128_sub(fr->addr.start,
871 int128_make64(fr->offset_in_region)));
872 if (!addrrange_intersects(tmp, fr->addr)) {
873 return;
874 }
875 tmp = addrrange_intersection(tmp, fr->addr);
876
877 if (add) {
878 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, coalesced_io_add,
879 int128_get64(tmp.start),
880 int128_get64(tmp.size));
881 } else {
882 MEMORY_LISTENER_UPDATE_REGION(fr, as, Reverse, coalesced_io_del,
883 int128_get64(tmp.start),
884 int128_get64(tmp.size));
885 }
886 }
887
888 static void flat_range_coalesced_io_del(FlatRange *fr, AddressSpace *as)
889 {
890 CoalescedMemoryRange *cmr;
891
892 QTAILQ_FOREACH(cmr, &fr->mr->coalesced, link) {
893 flat_range_coalesced_io_notify(fr, as, cmr, false);
894 }
895 }
896
897 static void flat_range_coalesced_io_add(FlatRange *fr, AddressSpace *as)
898 {
899 MemoryRegion *mr = fr->mr;
900 CoalescedMemoryRange *cmr;
901
902 if (QTAILQ_EMPTY(&mr->coalesced)) {
903 return;
904 }
905
906 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
907 flat_range_coalesced_io_notify(fr, as, cmr, true);
908 }
909 }
910
911 static void address_space_update_topology_pass(AddressSpace *as,
912 const FlatView *old_view,
913 const FlatView *new_view,
914 bool adding)
915 {
916 unsigned iold, inew;
917 FlatRange *frold, *frnew;
918
919 /* Generate a symmetric difference of the old and new memory maps.
920 * Kill ranges in the old map, and instantiate ranges in the new map.
921 */
922 iold = inew = 0;
923 while (iold < old_view->nr || inew < new_view->nr) {
924 if (iold < old_view->nr) {
925 frold = &old_view->ranges[iold];
926 } else {
927 frold = NULL;
928 }
929 if (inew < new_view->nr) {
930 frnew = &new_view->ranges[inew];
931 } else {
932 frnew = NULL;
933 }
934
935 if (frold
936 && (!frnew
937 || int128_lt(frold->addr.start, frnew->addr.start)
938 || (int128_eq(frold->addr.start, frnew->addr.start)
939 && !flatrange_equal(frold, frnew)))) {
940 /* In old but not in new, or in both but attributes changed. */
941
942 if (!adding) {
943 flat_range_coalesced_io_del(frold, as);
944 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
945 }
946
947 ++iold;
948 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
949 /* In both and unchanged (except logging may have changed) */
950
951 if (adding) {
952 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
953 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
954 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
955 frold->dirty_log_mask,
956 frnew->dirty_log_mask);
957 }
958 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
959 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
960 frold->dirty_log_mask,
961 frnew->dirty_log_mask);
962 }
963 }
964
965 ++iold;
966 ++inew;
967 } else {
968 /* In new */
969
970 if (adding) {
971 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
972 flat_range_coalesced_io_add(frnew, as);
973 }
974
975 ++inew;
976 }
977 }
978 }
979
980 static void flatviews_init(void)
981 {
982 static FlatView *empty_view;
983
984 if (flat_views) {
985 return;
986 }
987
988 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
989 (GDestroyNotify) flatview_unref);
990 if (!empty_view) {
991 empty_view = generate_memory_topology(NULL);
992 /* We keep it alive forever in the global variable. */
993 flatview_ref(empty_view);
994 } else {
995 g_hash_table_replace(flat_views, NULL, empty_view);
996 flatview_ref(empty_view);
997 }
998 }
999
1000 static void flatviews_reset(void)
1001 {
1002 AddressSpace *as;
1003
1004 if (flat_views) {
1005 g_hash_table_unref(flat_views);
1006 flat_views = NULL;
1007 }
1008 flatviews_init();
1009
1010 /* Render unique FVs */
1011 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1012 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1013
1014 if (g_hash_table_lookup(flat_views, physmr)) {
1015 continue;
1016 }
1017
1018 generate_memory_topology(physmr);
1019 }
1020 }
1021
1022 static void address_space_set_flatview(AddressSpace *as)
1023 {
1024 FlatView *old_view = address_space_to_flatview(as);
1025 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1026 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
1027
1028 assert(new_view);
1029
1030 if (old_view == new_view) {
1031 return;
1032 }
1033
1034 if (old_view) {
1035 flatview_ref(old_view);
1036 }
1037
1038 flatview_ref(new_view);
1039
1040 if (!QTAILQ_EMPTY(&as->listeners)) {
1041 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1042
1043 if (!old_view2) {
1044 old_view2 = &tmpview;
1045 }
1046 address_space_update_topology_pass(as, old_view2, new_view, false);
1047 address_space_update_topology_pass(as, old_view2, new_view, true);
1048 }
1049
1050 /* Writes are protected by the BQL. */
1051 qatomic_rcu_set(&as->current_map, new_view);
1052 if (old_view) {
1053 flatview_unref(old_view);
1054 }
1055
1056 /* Note that all the old MemoryRegions are still alive up to this
1057 * point. This relieves most MemoryListeners from the need to
1058 * ref/unref the MemoryRegions they get---unless they use them
1059 * outside the iothread mutex, in which case precise reference
1060 * counting is necessary.
1061 */
1062 if (old_view) {
1063 flatview_unref(old_view);
1064 }
1065 }
1066
1067 static void address_space_update_topology(AddressSpace *as)
1068 {
1069 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1070
1071 flatviews_init();
1072 if (!g_hash_table_lookup(flat_views, physmr)) {
1073 generate_memory_topology(physmr);
1074 }
1075 address_space_set_flatview(as);
1076 }
1077
1078 void memory_region_transaction_begin(void)
1079 {
1080 qemu_flush_coalesced_mmio_buffer();
1081 ++memory_region_transaction_depth;
1082 }
1083
1084 void memory_region_transaction_commit(void)
1085 {
1086 AddressSpace *as;
1087
1088 assert(memory_region_transaction_depth);
1089 assert(qemu_mutex_iothread_locked());
1090
1091 --memory_region_transaction_depth;
1092 if (!memory_region_transaction_depth) {
1093 if (memory_region_update_pending) {
1094 flatviews_reset();
1095
1096 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
1097
1098 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1099 address_space_set_flatview(as);
1100 address_space_update_ioeventfds(as);
1101 }
1102 memory_region_update_pending = false;
1103 ioeventfd_update_pending = false;
1104 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1105 } else if (ioeventfd_update_pending) {
1106 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1107 address_space_update_ioeventfds(as);
1108 }
1109 ioeventfd_update_pending = false;
1110 }
1111 }
1112 }
1113
1114 static void memory_region_destructor_none(MemoryRegion *mr)
1115 {
1116 }
1117
1118 static void memory_region_destructor_ram(MemoryRegion *mr)
1119 {
1120 qemu_ram_free(mr->ram_block);
1121 }
1122
1123 static bool memory_region_need_escape(char c)
1124 {
1125 return c == '/' || c == '[' || c == '\\' || c == ']';
1126 }
1127
1128 static char *memory_region_escape_name(const char *name)
1129 {
1130 const char *p;
1131 char *escaped, *q;
1132 uint8_t c;
1133 size_t bytes = 0;
1134
1135 for (p = name; *p; p++) {
1136 bytes += memory_region_need_escape(*p) ? 4 : 1;
1137 }
1138 if (bytes == p - name) {
1139 return g_memdup(name, bytes + 1);
1140 }
1141
1142 escaped = g_malloc(bytes + 1);
1143 for (p = name, q = escaped; *p; p++) {
1144 c = *p;
1145 if (unlikely(memory_region_need_escape(c))) {
1146 *q++ = '\\';
1147 *q++ = 'x';
1148 *q++ = "0123456789abcdef"[c >> 4];
1149 c = "0123456789abcdef"[c & 15];
1150 }
1151 *q++ = c;
1152 }
1153 *q = 0;
1154 return escaped;
1155 }
1156
1157 static void memory_region_do_init(MemoryRegion *mr,
1158 Object *owner,
1159 const char *name,
1160 uint64_t size)
1161 {
1162 mr->size = int128_make64(size);
1163 if (size == UINT64_MAX) {
1164 mr->size = int128_2_64();
1165 }
1166 mr->name = g_strdup(name);
1167 mr->owner = owner;
1168 mr->ram_block = NULL;
1169
1170 if (name) {
1171 char *escaped_name = memory_region_escape_name(name);
1172 char *name_array = g_strdup_printf("%s[*]", escaped_name);
1173
1174 if (!owner) {
1175 owner = container_get(qdev_get_machine(), "/unattached");
1176 }
1177
1178 object_property_add_child(owner, name_array, OBJECT(mr));
1179 object_unref(OBJECT(mr));
1180 g_free(name_array);
1181 g_free(escaped_name);
1182 }
1183 }
1184
1185 void memory_region_init(MemoryRegion *mr,
1186 Object *owner,
1187 const char *name,
1188 uint64_t size)
1189 {
1190 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1191 memory_region_do_init(mr, owner, name, size);
1192 }
1193
1194 static void memory_region_get_container(Object *obj, Visitor *v,
1195 const char *name, void *opaque,
1196 Error **errp)
1197 {
1198 MemoryRegion *mr = MEMORY_REGION(obj);
1199 char *path = (char *)"";
1200
1201 if (mr->container) {
1202 path = object_get_canonical_path(OBJECT(mr->container));
1203 }
1204 visit_type_str(v, name, &path, errp);
1205 if (mr->container) {
1206 g_free(path);
1207 }
1208 }
1209
1210 static Object *memory_region_resolve_container(Object *obj, void *opaque,
1211 const char *part)
1212 {
1213 MemoryRegion *mr = MEMORY_REGION(obj);
1214
1215 return OBJECT(mr->container);
1216 }
1217
1218 static void memory_region_get_priority(Object *obj, Visitor *v,
1219 const char *name, void *opaque,
1220 Error **errp)
1221 {
1222 MemoryRegion *mr = MEMORY_REGION(obj);
1223 int32_t value = mr->priority;
1224
1225 visit_type_int32(v, name, &value, errp);
1226 }
1227
1228 static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1229 void *opaque, Error **errp)
1230 {
1231 MemoryRegion *mr = MEMORY_REGION(obj);
1232 uint64_t value = memory_region_size(mr);
1233
1234 visit_type_uint64(v, name, &value, errp);
1235 }
1236
1237 static void memory_region_initfn(Object *obj)
1238 {
1239 MemoryRegion *mr = MEMORY_REGION(obj);
1240 ObjectProperty *op;
1241
1242 mr->ops = &unassigned_mem_ops;
1243 mr->enabled = true;
1244 mr->romd_mode = true;
1245 mr->destructor = memory_region_destructor_none;
1246 QTAILQ_INIT(&mr->subregions);
1247 QTAILQ_INIT(&mr->coalesced);
1248
1249 op = object_property_add(OBJECT(mr), "container",
1250 "link<" TYPE_MEMORY_REGION ">",
1251 memory_region_get_container,
1252 NULL, /* memory_region_set_container */
1253 NULL, NULL);
1254 op->resolve = memory_region_resolve_container;
1255
1256 object_property_add_uint64_ptr(OBJECT(mr), "addr",
1257 &mr->addr, OBJ_PROP_FLAG_READ);
1258 object_property_add(OBJECT(mr), "priority", "uint32",
1259 memory_region_get_priority,
1260 NULL, /* memory_region_set_priority */
1261 NULL, NULL);
1262 object_property_add(OBJECT(mr), "size", "uint64",
1263 memory_region_get_size,
1264 NULL, /* memory_region_set_size, */
1265 NULL, NULL);
1266 }
1267
1268 static void iommu_memory_region_initfn(Object *obj)
1269 {
1270 MemoryRegion *mr = MEMORY_REGION(obj);
1271
1272 mr->is_iommu = true;
1273 }
1274
1275 static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1276 unsigned size)
1277 {
1278 #ifdef DEBUG_UNASSIGNED
1279 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1280 #endif
1281 return 0;
1282 }
1283
1284 static void unassigned_mem_write(void *opaque, hwaddr addr,
1285 uint64_t val, unsigned size)
1286 {
1287 #ifdef DEBUG_UNASSIGNED
1288 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1289 #endif
1290 }
1291
1292 static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1293 unsigned size, bool is_write,
1294 MemTxAttrs attrs)
1295 {
1296 return false;
1297 }
1298
1299 const MemoryRegionOps unassigned_mem_ops = {
1300 .valid.accepts = unassigned_mem_accepts,
1301 .endianness = DEVICE_NATIVE_ENDIAN,
1302 };
1303
1304 static uint64_t memory_region_ram_device_read(void *opaque,
1305 hwaddr addr, unsigned size)
1306 {
1307 MemoryRegion *mr = opaque;
1308 uint64_t data = (uint64_t)~0;
1309
1310 switch (size) {
1311 case 1:
1312 data = *(uint8_t *)(mr->ram_block->host + addr);
1313 break;
1314 case 2:
1315 data = *(uint16_t *)(mr->ram_block->host + addr);
1316 break;
1317 case 4:
1318 data = *(uint32_t *)(mr->ram_block->host + addr);
1319 break;
1320 case 8:
1321 data = *(uint64_t *)(mr->ram_block->host + addr);
1322 break;
1323 }
1324
1325 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1326
1327 return data;
1328 }
1329
1330 static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1331 uint64_t data, unsigned size)
1332 {
1333 MemoryRegion *mr = opaque;
1334
1335 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1336
1337 switch (size) {
1338 case 1:
1339 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1340 break;
1341 case 2:
1342 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1343 break;
1344 case 4:
1345 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1346 break;
1347 case 8:
1348 *(uint64_t *)(mr->ram_block->host + addr) = data;
1349 break;
1350 }
1351 }
1352
1353 static const MemoryRegionOps ram_device_mem_ops = {
1354 .read = memory_region_ram_device_read,
1355 .write = memory_region_ram_device_write,
1356 .endianness = DEVICE_HOST_ENDIAN,
1357 .valid = {
1358 .min_access_size = 1,
1359 .max_access_size = 8,
1360 .unaligned = true,
1361 },
1362 .impl = {
1363 .min_access_size = 1,
1364 .max_access_size = 8,
1365 .unaligned = true,
1366 },
1367 };
1368
1369 bool memory_region_access_valid(MemoryRegion *mr,
1370 hwaddr addr,
1371 unsigned size,
1372 bool is_write,
1373 MemTxAttrs attrs)
1374 {
1375 if (mr->ops->valid.accepts
1376 && !mr->ops->valid.accepts(mr->opaque, addr, size, is_write, attrs)) {
1377 qemu_log_mask(LOG_GUEST_ERROR, "Invalid access at addr "
1378 "0x%" HWADDR_PRIX ", size %u, "
1379 "region '%s', reason: rejected\n",
1380 addr, size, memory_region_name(mr));
1381 return false;
1382 }
1383
1384 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1385 qemu_log_mask(LOG_GUEST_ERROR, "Invalid access at addr "
1386 "0x%" HWADDR_PRIX ", size %u, "
1387 "region '%s', reason: unaligned\n",
1388 addr, size, memory_region_name(mr));
1389 return false;
1390 }
1391
1392 /* Treat zero as compatibility all valid */
1393 if (!mr->ops->valid.max_access_size) {
1394 return true;
1395 }
1396
1397 if (size > mr->ops->valid.max_access_size
1398 || size < mr->ops->valid.min_access_size) {
1399 qemu_log_mask(LOG_GUEST_ERROR, "Invalid access at addr "
1400 "0x%" HWADDR_PRIX ", size %u, "
1401 "region '%s', reason: invalid size "
1402 "(min:%u max:%u)\n",
1403 addr, size, memory_region_name(mr),
1404 mr->ops->valid.min_access_size,
1405 mr->ops->valid.max_access_size);
1406 return false;
1407 }
1408 return true;
1409 }
1410
1411 static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1412 hwaddr addr,
1413 uint64_t *pval,
1414 unsigned size,
1415 MemTxAttrs attrs)
1416 {
1417 *pval = 0;
1418
1419 if (mr->ops->read) {
1420 return access_with_adjusted_size(addr, pval, size,
1421 mr->ops->impl.min_access_size,
1422 mr->ops->impl.max_access_size,
1423 memory_region_read_accessor,
1424 mr, attrs);
1425 } else {
1426 return access_with_adjusted_size(addr, pval, size,
1427 mr->ops->impl.min_access_size,
1428 mr->ops->impl.max_access_size,
1429 memory_region_read_with_attrs_accessor,
1430 mr, attrs);
1431 }
1432 }
1433
1434 MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1435 hwaddr addr,
1436 uint64_t *pval,
1437 MemOp op,
1438 MemTxAttrs attrs)
1439 {
1440 unsigned size = memop_size(op);
1441 MemTxResult r;
1442
1443 fuzz_dma_read_cb(addr, size, mr);
1444 if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
1445 *pval = unassigned_mem_read(mr, addr, size);
1446 return MEMTX_DECODE_ERROR;
1447 }
1448
1449 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
1450 adjust_endianness(mr, pval, op);
1451 return r;
1452 }
1453
1454 /* Return true if an eventfd was signalled */
1455 static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1456 hwaddr addr,
1457 uint64_t data,
1458 unsigned size,
1459 MemTxAttrs attrs)
1460 {
1461 MemoryRegionIoeventfd ioeventfd = {
1462 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1463 .data = data,
1464 };
1465 unsigned i;
1466
1467 for (i = 0; i < mr->ioeventfd_nb; i++) {
1468 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1469 ioeventfd.e = mr->ioeventfds[i].e;
1470
1471 if (memory_region_ioeventfd_equal(&ioeventfd, &mr->ioeventfds[i])) {
1472 event_notifier_set(ioeventfd.e);
1473 return true;
1474 }
1475 }
1476
1477 return false;
1478 }
1479
1480 MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1481 hwaddr addr,
1482 uint64_t data,
1483 MemOp op,
1484 MemTxAttrs attrs)
1485 {
1486 unsigned size = memop_size(op);
1487
1488 if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
1489 unassigned_mem_write(mr, addr, data, size);
1490 return MEMTX_DECODE_ERROR;
1491 }
1492
1493 adjust_endianness(mr, &data, op);
1494
1495 if ((!kvm_eventfds_enabled()) &&
1496 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1497 return MEMTX_OK;
1498 }
1499
1500 if (mr->ops->write) {
1501 return access_with_adjusted_size(addr, &data, size,
1502 mr->ops->impl.min_access_size,
1503 mr->ops->impl.max_access_size,
1504 memory_region_write_accessor, mr,
1505 attrs);
1506 } else {
1507 return
1508 access_with_adjusted_size(addr, &data, size,
1509 mr->ops->impl.min_access_size,
1510 mr->ops->impl.max_access_size,
1511 memory_region_write_with_attrs_accessor,
1512 mr, attrs);
1513 }
1514 }
1515
1516 void memory_region_init_io(MemoryRegion *mr,
1517 Object *owner,
1518 const MemoryRegionOps *ops,
1519 void *opaque,
1520 const char *name,
1521 uint64_t size)
1522 {
1523 memory_region_init(mr, owner, name, size);
1524 mr->ops = ops ? ops : &unassigned_mem_ops;
1525 mr->opaque = opaque;
1526 mr->terminates = true;
1527 }
1528
1529 void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1530 Object *owner,
1531 const char *name,
1532 uint64_t size,
1533 Error **errp)
1534 {
1535 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1536 }
1537
1538 void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr,
1539 Object *owner,
1540 const char *name,
1541 uint64_t size,
1542 bool share,
1543 Error **errp)
1544 {
1545 Error *err = NULL;
1546 memory_region_init(mr, owner, name, size);
1547 mr->ram = true;
1548 mr->terminates = true;
1549 mr->destructor = memory_region_destructor_ram;
1550 mr->ram_block = qemu_ram_alloc(size, share, mr, &err);
1551 if (err) {
1552 mr->size = int128_zero();
1553 object_unparent(OBJECT(mr));
1554 error_propagate(errp, err);
1555 }
1556 }
1557
1558 void memory_region_init_resizeable_ram(MemoryRegion *mr,
1559 Object *owner,
1560 const char *name,
1561 uint64_t size,
1562 uint64_t max_size,
1563 void (*resized)(const char*,
1564 uint64_t length,
1565 void *host),
1566 Error **errp)
1567 {
1568 Error *err = NULL;
1569 memory_region_init(mr, owner, name, size);
1570 mr->ram = true;
1571 mr->terminates = true;
1572 mr->destructor = memory_region_destructor_ram;
1573 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1574 mr, &err);
1575 if (err) {
1576 mr->size = int128_zero();
1577 object_unparent(OBJECT(mr));
1578 error_propagate(errp, err);
1579 }
1580 }
1581
1582 #ifdef CONFIG_POSIX
1583 void memory_region_init_ram_from_file(MemoryRegion *mr,
1584 Object *owner,
1585 const char *name,
1586 uint64_t size,
1587 uint64_t align,
1588 uint32_t ram_flags,
1589 const char *path,
1590 bool readonly,
1591 Error **errp)
1592 {
1593 Error *err = NULL;
1594 memory_region_init(mr, owner, name, size);
1595 mr->ram = true;
1596 mr->readonly = readonly;
1597 mr->terminates = true;
1598 mr->destructor = memory_region_destructor_ram;
1599 mr->align = align;
1600 mr->ram_block = qemu_ram_alloc_from_file(size, mr, ram_flags, path,
1601 readonly, &err);
1602 if (err) {
1603 mr->size = int128_zero();
1604 object_unparent(OBJECT(mr));
1605 error_propagate(errp, err);
1606 }
1607 }
1608
1609 void memory_region_init_ram_from_fd(MemoryRegion *mr,
1610 Object *owner,
1611 const char *name,
1612 uint64_t size,
1613 bool share,
1614 int fd,
1615 ram_addr_t offset,
1616 Error **errp)
1617 {
1618 Error *err = NULL;
1619 memory_region_init(mr, owner, name, size);
1620 mr->ram = true;
1621 mr->terminates = true;
1622 mr->destructor = memory_region_destructor_ram;
1623 mr->ram_block = qemu_ram_alloc_from_fd(size, mr,
1624 share ? RAM_SHARED : 0,
1625 fd, offset, false, &err);
1626 if (err) {
1627 mr->size = int128_zero();
1628 object_unparent(OBJECT(mr));
1629 error_propagate(errp, err);
1630 }
1631 }
1632 #endif
1633
1634 void memory_region_init_ram_ptr(MemoryRegion *mr,
1635 Object *owner,
1636 const char *name,
1637 uint64_t size,
1638 void *ptr)
1639 {
1640 memory_region_init(mr, owner, name, size);
1641 mr->ram = true;
1642 mr->terminates = true;
1643 mr->destructor = memory_region_destructor_ram;
1644
1645 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1646 assert(ptr != NULL);
1647 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
1648 }
1649
1650 void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1651 Object *owner,
1652 const char *name,
1653 uint64_t size,
1654 void *ptr)
1655 {
1656 memory_region_init(mr, owner, name, size);
1657 mr->ram = true;
1658 mr->terminates = true;
1659 mr->ram_device = true;
1660 mr->ops = &ram_device_mem_ops;
1661 mr->opaque = mr;
1662 mr->destructor = memory_region_destructor_ram;
1663
1664 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1665 assert(ptr != NULL);
1666 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
1667 }
1668
1669 void memory_region_init_alias(MemoryRegion *mr,
1670 Object *owner,
1671 const char *name,
1672 MemoryRegion *orig,
1673 hwaddr offset,
1674 uint64_t size)
1675 {
1676 memory_region_init(mr, owner, name, size);
1677 mr->alias = orig;
1678 mr->alias_offset = offset;
1679 }
1680
1681 void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1682 Object *owner,
1683 const char *name,
1684 uint64_t size,
1685 Error **errp)
1686 {
1687 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1688 mr->readonly = true;
1689 }
1690
1691 void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1692 Object *owner,
1693 const MemoryRegionOps *ops,
1694 void *opaque,
1695 const char *name,
1696 uint64_t size,
1697 Error **errp)
1698 {
1699 Error *err = NULL;
1700 assert(ops);
1701 memory_region_init(mr, owner, name, size);
1702 mr->ops = ops;
1703 mr->opaque = opaque;
1704 mr->terminates = true;
1705 mr->rom_device = true;
1706 mr->destructor = memory_region_destructor_ram;
1707 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
1708 if (err) {
1709 mr->size = int128_zero();
1710 object_unparent(OBJECT(mr));
1711 error_propagate(errp, err);
1712 }
1713 }
1714
1715 void memory_region_init_iommu(void *_iommu_mr,
1716 size_t instance_size,
1717 const char *mrtypename,
1718 Object *owner,
1719 const char *name,
1720 uint64_t size)
1721 {
1722 struct IOMMUMemoryRegion *iommu_mr;
1723 struct MemoryRegion *mr;
1724
1725 object_initialize(_iommu_mr, instance_size, mrtypename);
1726 mr = MEMORY_REGION(_iommu_mr);
1727 memory_region_do_init(mr, owner, name, size);
1728 iommu_mr = IOMMU_MEMORY_REGION(mr);
1729 mr->terminates = true; /* then re-forwards */
1730 QLIST_INIT(&iommu_mr->iommu_notify);
1731 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
1732 }
1733
1734 static void memory_region_finalize(Object *obj)
1735 {
1736 MemoryRegion *mr = MEMORY_REGION(obj);
1737
1738 assert(!mr->container);
1739
1740 /* We know the region is not visible in any address space (it
1741 * does not have a container and cannot be a root either because
1742 * it has no references, so we can blindly clear mr->enabled.
1743 * memory_region_set_enabled instead could trigger a transaction
1744 * and cause an infinite loop.
1745 */
1746 mr->enabled = false;
1747 memory_region_transaction_begin();
1748 while (!QTAILQ_EMPTY(&mr->subregions)) {
1749 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1750 memory_region_del_subregion(mr, subregion);
1751 }
1752 memory_region_transaction_commit();
1753
1754 mr->destructor(mr);
1755 memory_region_clear_coalescing(mr);
1756 g_free((char *)mr->name);
1757 g_free(mr->ioeventfds);
1758 }
1759
1760 Object *memory_region_owner(MemoryRegion *mr)
1761 {
1762 Object *obj = OBJECT(mr);
1763 return obj->parent;
1764 }
1765
1766 void memory_region_ref(MemoryRegion *mr)
1767 {
1768 /* MMIO callbacks most likely will access data that belongs
1769 * to the owner, hence the need to ref/unref the owner whenever
1770 * the memory region is in use.
1771 *
1772 * The memory region is a child of its owner. As long as the
1773 * owner doesn't call unparent itself on the memory region,
1774 * ref-ing the owner will also keep the memory region alive.
1775 * Memory regions without an owner are supposed to never go away;
1776 * we do not ref/unref them because it slows down DMA sensibly.
1777 */
1778 if (mr && mr->owner) {
1779 object_ref(mr->owner);
1780 }
1781 }
1782
1783 void memory_region_unref(MemoryRegion *mr)
1784 {
1785 if (mr && mr->owner) {
1786 object_unref(mr->owner);
1787 }
1788 }
1789
1790 uint64_t memory_region_size(MemoryRegion *mr)
1791 {
1792 if (int128_eq(mr->size, int128_2_64())) {
1793 return UINT64_MAX;
1794 }
1795 return int128_get64(mr->size);
1796 }
1797
1798 const char *memory_region_name(const MemoryRegion *mr)
1799 {
1800 if (!mr->name) {
1801 ((MemoryRegion *)mr)->name =
1802 g_strdup(object_get_canonical_path_component(OBJECT(mr)));
1803 }
1804 return mr->name;
1805 }
1806
1807 bool memory_region_is_ram_device(MemoryRegion *mr)
1808 {
1809 return mr->ram_device;
1810 }
1811
1812 uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
1813 {
1814 uint8_t mask = mr->dirty_log_mask;
1815 RAMBlock *rb = mr->ram_block;
1816
1817 if (global_dirty_log && ((rb && qemu_ram_is_migratable(rb)) ||
1818 memory_region_is_iommu(mr))) {
1819 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1820 }
1821
1822 if (tcg_enabled() && rb) {
1823 /* TCG only cares about dirty memory logging for RAM, not IOMMU. */
1824 mask |= (1 << DIRTY_MEMORY_CODE);
1825 }
1826 return mask;
1827 }
1828
1829 bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1830 {
1831 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1832 }
1833
1834 static int memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr,
1835 Error **errp)
1836 {
1837 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1838 IOMMUNotifier *iommu_notifier;
1839 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1840 int ret = 0;
1841
1842 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1843 flags |= iommu_notifier->notifier_flags;
1844 }
1845
1846 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1847 ret = imrc->notify_flag_changed(iommu_mr,
1848 iommu_mr->iommu_notify_flags,
1849 flags, errp);
1850 }
1851
1852 if (!ret) {
1853 iommu_mr->iommu_notify_flags = flags;
1854 }
1855 return ret;
1856 }
1857
1858 int memory_region_iommu_set_page_size_mask(IOMMUMemoryRegion *iommu_mr,
1859 uint64_t page_size_mask,
1860 Error **errp)
1861 {
1862 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1863 int ret = 0;
1864
1865 if (imrc->iommu_set_page_size_mask) {
1866 ret = imrc->iommu_set_page_size_mask(iommu_mr, page_size_mask, errp);
1867 }
1868 return ret;
1869 }
1870
1871 int memory_region_register_iommu_notifier(MemoryRegion *mr,
1872 IOMMUNotifier *n, Error **errp)
1873 {
1874 IOMMUMemoryRegion *iommu_mr;
1875 int ret;
1876
1877 if (mr->alias) {
1878 return memory_region_register_iommu_notifier(mr->alias, n, errp);
1879 }
1880
1881 /* We need to register for at least one bitfield */
1882 iommu_mr = IOMMU_MEMORY_REGION(mr);
1883 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
1884 assert(n->start <= n->end);
1885 assert(n->iommu_idx >= 0 &&
1886 n->iommu_idx < memory_region_iommu_num_indexes(iommu_mr));
1887
1888 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1889 ret = memory_region_update_iommu_notify_flags(iommu_mr, errp);
1890 if (ret) {
1891 QLIST_REMOVE(n, node);
1892 }
1893 return ret;
1894 }
1895
1896 uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
1897 {
1898 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1899
1900 if (imrc->get_min_page_size) {
1901 return imrc->get_min_page_size(iommu_mr);
1902 }
1903 return TARGET_PAGE_SIZE;
1904 }
1905
1906 void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
1907 {
1908 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1909 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1910 hwaddr addr, granularity;
1911 IOMMUTLBEntry iotlb;
1912
1913 /* If the IOMMU has its own replay callback, override */
1914 if (imrc->replay) {
1915 imrc->replay(iommu_mr, n);
1916 return;
1917 }
1918
1919 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
1920
1921 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1922 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx);
1923 if (iotlb.perm != IOMMU_NONE) {
1924 n->notify(n, &iotlb);
1925 }
1926
1927 /* if (2^64 - MR size) < granularity, it's possible to get an
1928 * infinite loop here. This should catch such a wraparound */
1929 if ((addr + granularity) < addr) {
1930 break;
1931 }
1932 }
1933 }
1934
1935 void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1936 IOMMUNotifier *n)
1937 {
1938 IOMMUMemoryRegion *iommu_mr;
1939
1940 if (mr->alias) {
1941 memory_region_unregister_iommu_notifier(mr->alias, n);
1942 return;
1943 }
1944 QLIST_REMOVE(n, node);
1945 iommu_mr = IOMMU_MEMORY_REGION(mr);
1946 memory_region_update_iommu_notify_flags(iommu_mr, NULL);
1947 }
1948
1949 void memory_region_notify_iommu_one(IOMMUNotifier *notifier,
1950 IOMMUTLBEvent *event)
1951 {
1952 IOMMUTLBEntry *entry = &event->entry;
1953 hwaddr entry_end = entry->iova + entry->addr_mask;
1954 IOMMUTLBEntry tmp = *entry;
1955
1956 if (event->type == IOMMU_NOTIFIER_UNMAP) {
1957 assert(entry->perm == IOMMU_NONE);
1958 }
1959
1960 /*
1961 * Skip the notification if the notification does not overlap
1962 * with registered range.
1963 */
1964 if (notifier->start > entry_end || notifier->end < entry->iova) {
1965 return;
1966 }
1967
1968 if (notifier->notifier_flags & IOMMU_NOTIFIER_DEVIOTLB_UNMAP) {
1969 /* Crop (iova, addr_mask) to range */
1970 tmp.iova = MAX(tmp.iova, notifier->start);
1971 tmp.addr_mask = MIN(entry_end, notifier->end) - tmp.iova;
1972 } else {
1973 assert(entry->iova >= notifier->start && entry_end <= notifier->end);
1974 }
1975
1976 if (event->type & notifier->notifier_flags) {
1977 notifier->notify(notifier, &tmp);
1978 }
1979 }
1980
1981 void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
1982 int iommu_idx,
1983 IOMMUTLBEvent event)
1984 {
1985 IOMMUNotifier *iommu_notifier;
1986
1987 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
1988
1989 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1990 if (iommu_notifier->iommu_idx == iommu_idx) {
1991 memory_region_notify_iommu_one(iommu_notifier, &event);
1992 }
1993 }
1994 }
1995
1996 int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr,
1997 enum IOMMUMemoryRegionAttr attr,
1998 void *data)
1999 {
2000 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2001
2002 if (!imrc->get_attr) {
2003 return -EINVAL;
2004 }
2005
2006 return imrc->get_attr(iommu_mr, attr, data);
2007 }
2008
2009 int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr,
2010 MemTxAttrs attrs)
2011 {
2012 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2013
2014 if (!imrc->attrs_to_index) {
2015 return 0;
2016 }
2017
2018 return imrc->attrs_to_index(iommu_mr, attrs);
2019 }
2020
2021 int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr)
2022 {
2023 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
2024
2025 if (!imrc->num_indexes) {
2026 return 1;
2027 }
2028
2029 return imrc->num_indexes(iommu_mr);
2030 }
2031
2032 void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
2033 {
2034 uint8_t mask = 1 << client;
2035 uint8_t old_logging;
2036
2037 assert(client == DIRTY_MEMORY_VGA);
2038 old_logging = mr->vga_logging_count;
2039 mr->vga_logging_count += log ? 1 : -1;
2040 if (!!old_logging == !!mr->vga_logging_count) {
2041 return;
2042 }
2043
2044 memory_region_transaction_begin();
2045 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
2046 memory_region_update_pending |= mr->enabled;
2047 memory_region_transaction_commit();
2048 }
2049
2050 void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
2051 hwaddr size)
2052 {
2053 assert(mr->ram_block);
2054 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
2055 size,
2056 memory_region_get_dirty_log_mask(mr));
2057 }
2058
2059 static void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
2060 {
2061 MemoryListener *listener;
2062 AddressSpace *as;
2063 FlatView *view;
2064 FlatRange *fr;
2065
2066 /* If the same address space has multiple log_sync listeners, we
2067 * visit that address space's FlatView multiple times. But because
2068 * log_sync listeners are rare, it's still cheaper than walking each
2069 * address space once.
2070 */
2071 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2072 if (!listener->log_sync) {
2073 continue;
2074 }
2075 as = listener->address_space;
2076 view = address_space_get_flatview(as);
2077 FOR_EACH_FLAT_RANGE(fr, view) {
2078 if (fr->dirty_log_mask && (!mr || fr->mr == mr)) {
2079 MemoryRegionSection mrs = section_from_flat_range(fr, view);
2080 listener->log_sync(listener, &mrs);
2081 }
2082 }
2083 flatview_unref(view);
2084 }
2085 }
2086
2087 void memory_region_clear_dirty_bitmap(MemoryRegion *mr, hwaddr start,
2088 hwaddr len)
2089 {
2090 MemoryRegionSection mrs;
2091 MemoryListener *listener;
2092 AddressSpace *as;
2093 FlatView *view;
2094 FlatRange *fr;
2095 hwaddr sec_start, sec_end, sec_size;
2096
2097 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2098 if (!listener->log_clear) {
2099 continue;
2100 }
2101 as = listener->address_space;
2102 view = address_space_get_flatview(as);
2103 FOR_EACH_FLAT_RANGE(fr, view) {
2104 if (!fr->dirty_log_mask || fr->mr != mr) {
2105 /*
2106 * Clear dirty bitmap operation only applies to those
2107 * regions whose dirty logging is at least enabled
2108 */
2109 continue;
2110 }
2111
2112 mrs = section_from_flat_range(fr, view);
2113
2114 sec_start = MAX(mrs.offset_within_region, start);
2115 sec_end = mrs.offset_within_region + int128_get64(mrs.size);
2116 sec_end = MIN(sec_end, start + len);
2117
2118 if (sec_start >= sec_end) {
2119 /*
2120 * If this memory region section has no intersection
2121 * with the requested range, skip.
2122 */
2123 continue;
2124 }
2125
2126 /* Valid case; shrink the section if needed */
2127 mrs.offset_within_address_space +=
2128 sec_start - mrs.offset_within_region;
2129 mrs.offset_within_region = sec_start;
2130 sec_size = sec_end - sec_start;
2131 mrs.size = int128_make64(sec_size);
2132 listener->log_clear(listener, &mrs);
2133 }
2134 flatview_unref(view);
2135 }
2136 }
2137
2138 DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
2139 hwaddr addr,
2140 hwaddr size,
2141 unsigned client)
2142 {
2143 DirtyBitmapSnapshot *snapshot;
2144 assert(mr->ram_block);
2145 memory_region_sync_dirty_bitmap(mr);
2146 snapshot = cpu_physical_memory_snapshot_and_clear_dirty(mr, addr, size, client);
2147 memory_global_after_dirty_log_sync();
2148 return snapshot;
2149 }
2150
2151 bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
2152 hwaddr addr, hwaddr size)
2153 {
2154 assert(mr->ram_block);
2155 return cpu_physical_memory_snapshot_get_dirty(snap,
2156 memory_region_get_ram_addr(mr) + addr, size);
2157 }
2158
2159 void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
2160 {
2161 if (mr->readonly != readonly) {
2162 memory_region_transaction_begin();
2163 mr->readonly = readonly;
2164 memory_region_update_pending |= mr->enabled;
2165 memory_region_transaction_commit();
2166 }
2167 }
2168
2169 void memory_region_set_nonvolatile(MemoryRegion *mr, bool nonvolatile)
2170 {
2171 if (mr->nonvolatile != nonvolatile) {
2172 memory_region_transaction_begin();
2173 mr->nonvolatile = nonvolatile;
2174 memory_region_update_pending |= mr->enabled;
2175 memory_region_transaction_commit();
2176 }
2177 }
2178
2179 void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
2180 {
2181 if (mr->romd_mode != romd_mode) {
2182 memory_region_transaction_begin();
2183 mr->romd_mode = romd_mode;
2184 memory_region_update_pending |= mr->enabled;
2185 memory_region_transaction_commit();
2186 }
2187 }
2188
2189 void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2190 hwaddr size, unsigned client)
2191 {
2192 assert(mr->ram_block);
2193 cpu_physical_memory_test_and_clear_dirty(
2194 memory_region_get_ram_addr(mr) + addr, size, client);
2195 }
2196
2197 int memory_region_get_fd(MemoryRegion *mr)
2198 {
2199 int fd;
2200
2201 RCU_READ_LOCK_GUARD();
2202 while (mr->alias) {
2203 mr = mr->alias;
2204 }
2205 fd = mr->ram_block->fd;
2206
2207 return fd;
2208 }
2209
2210 void *memory_region_get_ram_ptr(MemoryRegion *mr)
2211 {
2212 void *ptr;
2213 uint64_t offset = 0;
2214
2215 RCU_READ_LOCK_GUARD();
2216 while (mr->alias) {
2217 offset += mr->alias_offset;
2218 mr = mr->alias;
2219 }
2220 assert(mr->ram_block);
2221 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
2222
2223 return ptr;
2224 }
2225
2226 MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2227 {
2228 RAMBlock *block;
2229
2230 block = qemu_ram_block_from_host(ptr, false, offset);
2231 if (!block) {
2232 return NULL;
2233 }
2234
2235 return block->mr;
2236 }
2237
2238 ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2239 {
2240 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2241 }
2242
2243 void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2244 {
2245 assert(mr->ram_block);
2246
2247 qemu_ram_resize(mr->ram_block, newsize, errp);
2248 }
2249
2250 void memory_region_msync(MemoryRegion *mr, hwaddr addr, hwaddr size)
2251 {
2252 if (mr->ram_block) {
2253 qemu_ram_msync(mr->ram_block, addr, size);
2254 }
2255 }
2256
2257 void memory_region_writeback(MemoryRegion *mr, hwaddr addr, hwaddr size)
2258 {
2259 /*
2260 * Might be extended case needed to cover
2261 * different types of memory regions
2262 */
2263 if (mr->dirty_log_mask) {
2264 memory_region_msync(mr, addr, size);
2265 }
2266 }
2267
2268 /*
2269 * Call proper memory listeners about the change on the newly
2270 * added/removed CoalescedMemoryRange.
2271 */
2272 static void memory_region_update_coalesced_range(MemoryRegion *mr,
2273 CoalescedMemoryRange *cmr,
2274 bool add)
2275 {
2276 AddressSpace *as;
2277 FlatView *view;
2278 FlatRange *fr;
2279
2280 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2281 view = address_space_get_flatview(as);
2282 FOR_EACH_FLAT_RANGE(fr, view) {
2283 if (fr->mr == mr) {
2284 flat_range_coalesced_io_notify(fr, as, cmr, add);
2285 }
2286 }
2287 flatview_unref(view);
2288 }
2289 }
2290
2291 void memory_region_set_coalescing(MemoryRegion *mr)
2292 {
2293 memory_region_clear_coalescing(mr);
2294 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
2295 }
2296
2297 void memory_region_add_coalescing(MemoryRegion *mr,
2298 hwaddr offset,
2299 uint64_t size)
2300 {
2301 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
2302
2303 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
2304 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2305 memory_region_update_coalesced_range(mr, cmr, true);
2306 memory_region_set_flush_coalesced(mr);
2307 }
2308
2309 void memory_region_clear_coalescing(MemoryRegion *mr)
2310 {
2311 CoalescedMemoryRange *cmr;
2312
2313 if (QTAILQ_EMPTY(&mr->coalesced)) {
2314 return;
2315 }
2316
2317 qemu_flush_coalesced_mmio_buffer();
2318 mr->flush_coalesced_mmio = false;
2319
2320 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2321 cmr = QTAILQ_FIRST(&mr->coalesced);
2322 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
2323 memory_region_update_coalesced_range(mr, cmr, false);
2324 g_free(cmr);
2325 }
2326 }
2327
2328 void memory_region_set_flush_coalesced(MemoryRegion *mr)
2329 {
2330 mr->flush_coalesced_mmio = true;
2331 }
2332
2333 void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2334 {
2335 qemu_flush_coalesced_mmio_buffer();
2336 if (QTAILQ_EMPTY(&mr->coalesced)) {
2337 mr->flush_coalesced_mmio = false;
2338 }
2339 }
2340
2341 static bool userspace_eventfd_warning;
2342
2343 void memory_region_add_eventfd(MemoryRegion *mr,
2344 hwaddr addr,
2345 unsigned size,
2346 bool match_data,
2347 uint64_t data,
2348 EventNotifier *e)
2349 {
2350 MemoryRegionIoeventfd mrfd = {
2351 .addr.start = int128_make64(addr),
2352 .addr.size = int128_make64(size),
2353 .match_data = match_data,
2354 .data = data,
2355 .e = e,
2356 };
2357 unsigned i;
2358
2359 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2360 userspace_eventfd_warning))) {
2361 userspace_eventfd_warning = true;
2362 error_report("Using eventfd without MMIO binding in KVM. "
2363 "Suboptimal performance expected");
2364 }
2365
2366 if (size) {
2367 adjust_endianness(mr, &mrfd.data, size_memop(size) | MO_TE);
2368 }
2369 memory_region_transaction_begin();
2370 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2371 if (memory_region_ioeventfd_before(&mrfd, &mr->ioeventfds[i])) {
2372 break;
2373 }
2374 }
2375 ++mr->ioeventfd_nb;
2376 mr->ioeventfds = g_realloc(mr->ioeventfds,
2377 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2378 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2379 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2380 mr->ioeventfds[i] = mrfd;
2381 ioeventfd_update_pending |= mr->enabled;
2382 memory_region_transaction_commit();
2383 }
2384
2385 void memory_region_del_eventfd(MemoryRegion *mr,
2386 hwaddr addr,
2387 unsigned size,
2388 bool match_data,
2389 uint64_t data,
2390 EventNotifier *e)
2391 {
2392 MemoryRegionIoeventfd mrfd = {
2393 .addr.start = int128_make64(addr),
2394 .addr.size = int128_make64(size),
2395 .match_data = match_data,
2396 .data = data,
2397 .e = e,
2398 };
2399 unsigned i;
2400
2401 if (size) {
2402 adjust_endianness(mr, &mrfd.data, size_memop(size) | MO_TE);
2403 }
2404 memory_region_transaction_begin();
2405 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2406 if (memory_region_ioeventfd_equal(&mrfd, &mr->ioeventfds[i])) {
2407 break;
2408 }
2409 }
2410 assert(i != mr->ioeventfd_nb);
2411 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2412 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2413 --mr->ioeventfd_nb;
2414 mr->ioeventfds = g_realloc(mr->ioeventfds,
2415 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
2416 ioeventfd_update_pending |= mr->enabled;
2417 memory_region_transaction_commit();
2418 }
2419
2420 static void memory_region_update_container_subregions(MemoryRegion *subregion)
2421 {
2422 MemoryRegion *mr = subregion->container;
2423 MemoryRegion *other;
2424
2425 memory_region_transaction_begin();
2426
2427 memory_region_ref(subregion);
2428 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2429 if (subregion->priority >= other->priority) {
2430 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2431 goto done;
2432 }
2433 }
2434 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2435 done:
2436 memory_region_update_pending |= mr->enabled && subregion->enabled;
2437 memory_region_transaction_commit();
2438 }
2439
2440 static void memory_region_add_subregion_common(MemoryRegion *mr,
2441 hwaddr offset,
2442 MemoryRegion *subregion)
2443 {
2444 assert(!subregion->container);
2445 subregion->container = mr;
2446 subregion->addr = offset;
2447 memory_region_update_container_subregions(subregion);
2448 }
2449
2450 void memory_region_add_subregion(MemoryRegion *mr,
2451 hwaddr offset,
2452 MemoryRegion *subregion)
2453 {
2454 subregion->priority = 0;
2455 memory_region_add_subregion_common(mr, offset, subregion);
2456 }
2457
2458 void memory_region_add_subregion_overlap(MemoryRegion *mr,
2459 hwaddr offset,
2460 MemoryRegion *subregion,
2461 int priority)
2462 {
2463 subregion->priority = priority;
2464 memory_region_add_subregion_common(mr, offset, subregion);
2465 }
2466
2467 void memory_region_del_subregion(MemoryRegion *mr,
2468 MemoryRegion *subregion)
2469 {
2470 memory_region_transaction_begin();
2471 assert(subregion->container == mr);
2472 subregion->container = NULL;
2473 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
2474 memory_region_unref(subregion);
2475 memory_region_update_pending |= mr->enabled && subregion->enabled;
2476 memory_region_transaction_commit();
2477 }
2478
2479 void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2480 {
2481 if (enabled == mr->enabled) {
2482 return;
2483 }
2484 memory_region_transaction_begin();
2485 mr->enabled = enabled;
2486 memory_region_update_pending = true;
2487 memory_region_transaction_commit();
2488 }
2489
2490 void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2491 {
2492 Int128 s = int128_make64(size);
2493
2494 if (size == UINT64_MAX) {
2495 s = int128_2_64();
2496 }
2497 if (int128_eq(s, mr->size)) {
2498 return;
2499 }
2500 memory_region_transaction_begin();
2501 mr->size = s;
2502 memory_region_update_pending = true;
2503 memory_region_transaction_commit();
2504 }
2505
2506 static void memory_region_readd_subregion(MemoryRegion *mr)
2507 {
2508 MemoryRegion *container = mr->container;
2509
2510 if (container) {
2511 memory_region_transaction_begin();
2512 memory_region_ref(mr);
2513 memory_region_del_subregion(container, mr);
2514 mr->container = container;
2515 memory_region_update_container_subregions(mr);
2516 memory_region_unref(mr);
2517 memory_region_transaction_commit();
2518 }
2519 }
2520
2521 void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2522 {
2523 if (addr != mr->addr) {
2524 mr->addr = addr;
2525 memory_region_readd_subregion(mr);
2526 }
2527 }
2528
2529 void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
2530 {
2531 assert(mr->alias);
2532
2533 if (offset == mr->alias_offset) {
2534 return;
2535 }
2536
2537 memory_region_transaction_begin();
2538 mr->alias_offset = offset;
2539 memory_region_update_pending |= mr->enabled;
2540 memory_region_transaction_commit();
2541 }
2542
2543 uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2544 {
2545 return mr->align;
2546 }
2547
2548 static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2549 {
2550 const AddrRange *addr = addr_;
2551 const FlatRange *fr = fr_;
2552
2553 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2554 return -1;
2555 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2556 return 1;
2557 }
2558 return 0;
2559 }
2560
2561 static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
2562 {
2563 return bsearch(&addr, view->ranges, view->nr,
2564 sizeof(FlatRange), cmp_flatrange_addr);
2565 }
2566
2567 bool memory_region_is_mapped(MemoryRegion *mr)
2568 {
2569 return mr->container ? true : false;
2570 }
2571
2572 /* Same as memory_region_find, but it does not add a reference to the
2573 * returned region. It must be called from an RCU critical section.
2574 */
2575 static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2576 hwaddr addr, uint64_t size)
2577 {
2578 MemoryRegionSection ret = { .mr = NULL };
2579 MemoryRegion *root;
2580 AddressSpace *as;
2581 AddrRange range;
2582 FlatView *view;
2583 FlatRange *fr;
2584
2585 addr += mr->addr;
2586 for (root = mr; root->container; ) {
2587 root = root->container;
2588 addr += root->addr;
2589 }
2590
2591 as = memory_region_to_address_space(root);
2592 if (!as) {
2593 return ret;
2594 }
2595 range = addrrange_make(int128_make64(addr), int128_make64(size));
2596
2597 view = address_space_to_flatview(as);
2598 fr = flatview_lookup(view, range);
2599 if (!fr) {
2600 return ret;
2601 }
2602
2603 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
2604 --fr;
2605 }
2606
2607 ret.mr = fr->mr;
2608 ret.fv = view;
2609 range = addrrange_intersection(range, fr->addr);
2610 ret.offset_within_region = fr->offset_in_region;
2611 ret.offset_within_region += int128_get64(int128_sub(range.start,
2612 fr->addr.start));
2613 ret.size = range.size;
2614 ret.offset_within_address_space = int128_get64(range.start);
2615 ret.readonly = fr->readonly;
2616 ret.nonvolatile = fr->nonvolatile;
2617 return ret;
2618 }
2619
2620 MemoryRegionSection memory_region_find(MemoryRegion *mr,
2621 hwaddr addr, uint64_t size)
2622 {
2623 MemoryRegionSection ret;
2624 RCU_READ_LOCK_GUARD();
2625 ret = memory_region_find_rcu(mr, addr, size);
2626 if (ret.mr) {
2627 memory_region_ref(ret.mr);
2628 }
2629 return ret;
2630 }
2631
2632 bool memory_region_present(MemoryRegion *container, hwaddr addr)
2633 {
2634 MemoryRegion *mr;
2635
2636 RCU_READ_LOCK_GUARD();
2637 mr = memory_region_find_rcu(container, addr, 1).mr;
2638 return mr && mr != container;
2639 }
2640
2641 void memory_global_dirty_log_sync(void)
2642 {
2643 memory_region_sync_dirty_bitmap(NULL);
2644 }
2645
2646 void memory_global_after_dirty_log_sync(void)
2647 {
2648 MEMORY_LISTENER_CALL_GLOBAL(log_global_after_sync, Forward);
2649 }
2650
2651 static VMChangeStateEntry *vmstate_change;
2652
2653 void memory_global_dirty_log_start(void)
2654 {
2655 if (vmstate_change) {
2656 qemu_del_vm_change_state_handler(vmstate_change);
2657 vmstate_change = NULL;
2658 }
2659
2660 global_dirty_log = true;
2661
2662 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
2663
2664 /* Refresh DIRTY_MEMORY_MIGRATION bit. */
2665 memory_region_transaction_begin();
2666 memory_region_update_pending = true;
2667 memory_region_transaction_commit();
2668 }
2669
2670 static void memory_global_dirty_log_do_stop(void)
2671 {
2672 global_dirty_log = false;
2673
2674 /* Refresh DIRTY_MEMORY_MIGRATION bit. */
2675 memory_region_transaction_begin();
2676 memory_region_update_pending = true;
2677 memory_region_transaction_commit();
2678
2679 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
2680 }
2681
2682 static void memory_vm_change_state_handler(void *opaque, int running,
2683 RunState state)
2684 {
2685 if (running) {
2686 memory_global_dirty_log_do_stop();
2687
2688 if (vmstate_change) {
2689 qemu_del_vm_change_state_handler(vmstate_change);
2690 vmstate_change = NULL;
2691 }
2692 }
2693 }
2694
2695 void memory_global_dirty_log_stop(void)
2696 {
2697 if (!runstate_is_running()) {
2698 if (vmstate_change) {
2699 return;
2700 }
2701 vmstate_change = qemu_add_vm_change_state_handler(
2702 memory_vm_change_state_handler, NULL);
2703 return;
2704 }
2705
2706 memory_global_dirty_log_do_stop();
2707 }
2708
2709 static void listener_add_address_space(MemoryListener *listener,
2710 AddressSpace *as)
2711 {
2712 FlatView *view;
2713 FlatRange *fr;
2714
2715 if (listener->begin) {
2716 listener->begin(listener);
2717 }
2718 if (global_dirty_log) {
2719 if (listener->log_global_start) {
2720 listener->log_global_start(listener);
2721 }
2722 }
2723
2724 view = address_space_get_flatview(as);
2725 FOR_EACH_FLAT_RANGE(fr, view) {
2726 MemoryRegionSection section = section_from_flat_range(fr, view);
2727
2728 if (listener->region_add) {
2729 listener->region_add(listener, &section);
2730 }
2731 if (fr->dirty_log_mask && listener->log_start) {
2732 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2733 }
2734 }
2735 if (listener->commit) {
2736 listener->commit(listener);
2737 }
2738 flatview_unref(view);
2739 }
2740
2741 static void listener_del_address_space(MemoryListener *listener,
2742 AddressSpace *as)
2743 {
2744 FlatView *view;
2745 FlatRange *fr;
2746
2747 if (listener->begin) {
2748 listener->begin(listener);
2749 }
2750 view = address_space_get_flatview(as);
2751 FOR_EACH_FLAT_RANGE(fr, view) {
2752 MemoryRegionSection section = section_from_flat_range(fr, view);
2753
2754 if (fr->dirty_log_mask && listener->log_stop) {
2755 listener->log_stop(listener, &section, fr->dirty_log_mask, 0);
2756 }
2757 if (listener->region_del) {
2758 listener->region_del(listener, &section);
2759 }
2760 }
2761 if (listener->commit) {
2762 listener->commit(listener);
2763 }
2764 flatview_unref(view);
2765 }
2766
2767 void memory_listener_register(MemoryListener *listener, AddressSpace *as)
2768 {
2769 MemoryListener *other = NULL;
2770
2771 listener->address_space = as;
2772 if (QTAILQ_EMPTY(&memory_listeners)
2773 || listener->priority >= QTAILQ_LAST(&memory_listeners)->priority) {
2774 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2775 } else {
2776 QTAILQ_FOREACH(other, &memory_listeners, link) {
2777 if (listener->priority < other->priority) {
2778 break;
2779 }
2780 }
2781 QTAILQ_INSERT_BEFORE(other, listener, link);
2782 }
2783
2784 if (QTAILQ_EMPTY(&as->listeners)
2785 || listener->priority >= QTAILQ_LAST(&as->listeners)->priority) {
2786 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2787 } else {
2788 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2789 if (listener->priority < other->priority) {
2790 break;
2791 }
2792 }
2793 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2794 }
2795
2796 listener_add_address_space(listener, as);
2797 }
2798
2799 void memory_listener_unregister(MemoryListener *listener)
2800 {
2801 if (!listener->address_space) {
2802 return;
2803 }
2804
2805 listener_del_address_space(listener, listener->address_space);
2806 QTAILQ_REMOVE(&memory_listeners, listener, link);
2807 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
2808 listener->address_space = NULL;
2809 }
2810
2811 void address_space_remove_listeners(AddressSpace *as)
2812 {
2813 while (!QTAILQ_EMPTY(&as->listeners)) {
2814 memory_listener_unregister(QTAILQ_FIRST(&as->listeners));
2815 }
2816 }
2817
2818 void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
2819 {
2820 memory_region_ref(root);
2821 as->root = root;
2822 as->current_map = NULL;
2823 as->ioeventfd_nb = 0;
2824 as->ioeventfds = NULL;
2825 QTAILQ_INIT(&as->listeners);
2826 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
2827 as->name = g_strdup(name ? name : "anonymous");
2828 address_space_update_topology(as);
2829 address_space_update_ioeventfds(as);
2830 }
2831
2832 static void do_address_space_destroy(AddressSpace *as)
2833 {
2834 assert(QTAILQ_EMPTY(&as->listeners));
2835
2836 flatview_unref(as->current_map);
2837 g_free(as->name);
2838 g_free(as->ioeventfds);
2839 memory_region_unref(as->root);
2840 }
2841
2842 void address_space_destroy(AddressSpace *as)
2843 {
2844 MemoryRegion *root = as->root;
2845
2846 /* Flush out anything from MemoryListeners listening in on this */
2847 memory_region_transaction_begin();
2848 as->root = NULL;
2849 memory_region_transaction_commit();
2850 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2851
2852 /* At this point, as->dispatch and as->current_map are dummy
2853 * entries that the guest should never use. Wait for the old
2854 * values to expire before freeing the data.
2855 */
2856 as->root = root;
2857 call_rcu(as, do_address_space_destroy, rcu);
2858 }
2859
2860 static const char *memory_region_type(MemoryRegion *mr)
2861 {
2862 if (mr->alias) {
2863 return memory_region_type(mr->alias);
2864 }
2865 if (memory_region_is_ram_device(mr)) {
2866 return "ramd";
2867 } else if (memory_region_is_romd(mr)) {
2868 return "romd";
2869 } else if (memory_region_is_rom(mr)) {
2870 return "rom";
2871 } else if (memory_region_is_ram(mr)) {
2872 return "ram";
2873 } else {
2874 return "i/o";
2875 }
2876 }
2877
2878 typedef struct MemoryRegionList MemoryRegionList;
2879
2880 struct MemoryRegionList {
2881 const MemoryRegion *mr;
2882 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
2883 };
2884
2885 typedef QTAILQ_HEAD(, MemoryRegionList) MemoryRegionListHead;
2886
2887 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2888 int128_sub((size), int128_one())) : 0)
2889 #define MTREE_INDENT " "
2890
2891 static void mtree_expand_owner(const char *label, Object *obj)
2892 {
2893 DeviceState *dev = (DeviceState *) object_dynamic_cast(obj, TYPE_DEVICE);
2894
2895 qemu_printf(" %s:{%s", label, dev ? "dev" : "obj");
2896 if (dev && dev->id) {
2897 qemu_printf(" id=%s", dev->id);
2898 } else {
2899 char *canonical_path = object_get_canonical_path(obj);
2900 if (canonical_path) {
2901 qemu_printf(" path=%s", canonical_path);
2902 g_free(canonical_path);
2903 } else {
2904 qemu_printf(" type=%s", object_get_typename(obj));
2905 }
2906 }
2907 qemu_printf("}");
2908 }
2909
2910 static void mtree_print_mr_owner(const MemoryRegion *mr)
2911 {
2912 Object *owner = mr->owner;
2913 Object *parent = memory_region_owner((MemoryRegion *)mr);
2914
2915 if (!owner && !parent) {
2916 qemu_printf(" orphan");
2917 return;
2918 }
2919 if (owner) {
2920 mtree_expand_owner("owner", owner);
2921 }
2922 if (parent && parent != owner) {
2923 mtree_expand_owner("parent", parent);
2924 }
2925 }
2926
2927 static void mtree_print_mr(const MemoryRegion *mr, unsigned int level,
2928 hwaddr base,
2929 MemoryRegionListHead *alias_print_queue,
2930 bool owner, bool display_disabled)
2931 {
2932 MemoryRegionList *new_ml, *ml, *next_ml;
2933 MemoryRegionListHead submr_print_queue;
2934 const MemoryRegion *submr;
2935 unsigned int i;
2936 hwaddr cur_start, cur_end;
2937
2938 if (!mr) {
2939 return;
2940 }
2941
2942 cur_start = base + mr->addr;
2943 cur_end = cur_start + MR_SIZE(mr->size);
2944
2945 /*
2946 * Try to detect overflow of memory region. This should never
2947 * happen normally. When it happens, we dump something to warn the
2948 * user who is observing this.
2949 */
2950 if (cur_start < base || cur_end < cur_start) {
2951 qemu_printf("[DETECTED OVERFLOW!] ");
2952 }
2953
2954 if (mr->alias) {
2955 MemoryRegionList *ml;
2956 bool found = false;
2957
2958 /* check if the alias is already in the queue */
2959 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
2960 if (ml->mr == mr->alias) {
2961 found = true;
2962 }
2963 }
2964
2965 if (!found) {
2966 ml = g_new(MemoryRegionList, 1);
2967 ml->mr = mr->alias;
2968 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
2969 }
2970 if (mr->enabled || display_disabled) {
2971 for (i = 0; i < level; i++) {
2972 qemu_printf(MTREE_INDENT);
2973 }
2974 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
2975 " (prio %d, %s%s): alias %s @%s " TARGET_FMT_plx
2976 "-" TARGET_FMT_plx "%s",
2977 cur_start, cur_end,
2978 mr->priority,
2979 mr->nonvolatile ? "nv-" : "",
2980 memory_region_type((MemoryRegion *)mr),
2981 memory_region_name(mr),
2982 memory_region_name(mr->alias),
2983 mr->alias_offset,
2984 mr->alias_offset + MR_SIZE(mr->size),
2985 mr->enabled ? "" : " [disabled]");
2986 if (owner) {
2987 mtree_print_mr_owner(mr);
2988 }
2989 qemu_printf("\n");
2990 }
2991 } else {
2992 if (mr->enabled || display_disabled) {
2993 for (i = 0; i < level; i++) {
2994 qemu_printf(MTREE_INDENT);
2995 }
2996 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
2997 " (prio %d, %s%s): %s%s",
2998 cur_start, cur_end,
2999 mr->priority,
3000 mr->nonvolatile ? "nv-" : "",
3001 memory_region_type((MemoryRegion *)mr),
3002 memory_region_name(mr),
3003 mr->enabled ? "" : " [disabled]");
3004 if (owner) {
3005 mtree_print_mr_owner(mr);
3006 }
3007 qemu_printf("\n");
3008 }
3009 }
3010
3011 QTAILQ_INIT(&submr_print_queue);
3012
3013 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
3014 new_ml = g_new(MemoryRegionList, 1);
3015 new_ml->mr = submr;
3016 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
3017 if (new_ml->mr->addr < ml->mr->addr ||
3018 (new_ml->mr->addr == ml->mr->addr &&
3019 new_ml->mr->priority > ml->mr->priority)) {
3020 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
3021 new_ml = NULL;
3022 break;
3023 }
3024 }
3025 if (new_ml) {
3026 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
3027 }
3028 }
3029
3030 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
3031 mtree_print_mr(ml->mr, level + 1, cur_start,
3032 alias_print_queue, owner, display_disabled);
3033 }
3034
3035 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
3036 g_free(ml);
3037 }
3038 }
3039
3040 struct FlatViewInfo {
3041 int counter;
3042 bool dispatch_tree;
3043 bool owner;
3044 AccelClass *ac;
3045 };
3046
3047 static void mtree_print_flatview(gpointer key, gpointer value,
3048 gpointer user_data)
3049 {
3050 FlatView *view = key;
3051 GArray *fv_address_spaces = value;
3052 struct FlatViewInfo *fvi = user_data;
3053 FlatRange *range = &view->ranges[0];
3054 MemoryRegion *mr;
3055 int n = view->nr;
3056 int i;
3057 AddressSpace *as;
3058
3059 qemu_printf("FlatView #%d\n", fvi->counter);
3060 ++fvi->counter;
3061
3062 for (i = 0; i < fv_address_spaces->len; ++i) {
3063 as = g_array_index(fv_address_spaces, AddressSpace*, i);
3064 qemu_printf(" AS \"%s\", root: %s",
3065 as->name, memory_region_name(as->root));
3066 if (as->root->alias) {
3067 qemu_printf(", alias %s", memory_region_name(as->root->alias));
3068 }
3069 qemu_printf("\n");
3070 }
3071
3072 qemu_printf(" Root memory region: %s\n",
3073 view->root ? memory_region_name(view->root) : "(none)");
3074
3075 if (n <= 0) {
3076 qemu_printf(MTREE_INDENT "No rendered FlatView\n\n");
3077 return;
3078 }
3079
3080 while (n--) {
3081 mr = range->mr;
3082 if (range->offset_in_region) {
3083 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
3084 " (prio %d, %s%s): %s @" TARGET_FMT_plx,
3085 int128_get64(range->addr.start),
3086 int128_get64(range->addr.start)
3087 + MR_SIZE(range->addr.size),
3088 mr->priority,
3089 range->nonvolatile ? "nv-" : "",
3090 range->readonly ? "rom" : memory_region_type(mr),
3091 memory_region_name(mr),
3092 range->offset_in_region);
3093 } else {
3094 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
3095 " (prio %d, %s%s): %s",
3096 int128_get64(range->addr.start),
3097 int128_get64(range->addr.start)
3098 + MR_SIZE(range->addr.size),
3099 mr->priority,
3100 range->nonvolatile ? "nv-" : "",
3101 range->readonly ? "rom" : memory_region_type(mr),
3102 memory_region_name(mr));
3103 }
3104 if (fvi->owner) {
3105 mtree_print_mr_owner(mr);
3106 }
3107
3108 if (fvi->ac) {
3109 for (i = 0; i < fv_address_spaces->len; ++i) {
3110 as = g_array_index(fv_address_spaces, AddressSpace*, i);
3111 if (fvi->ac->has_memory(current_machine, as,
3112 int128_get64(range->addr.start),
3113 MR_SIZE(range->addr.size) + 1)) {
3114 qemu_printf(" %s", fvi->ac->name);
3115 }
3116 }
3117 }
3118 qemu_printf("\n");
3119 range++;
3120 }
3121
3122 #if !defined(CONFIG_USER_ONLY)
3123 if (fvi->dispatch_tree && view->root) {
3124 mtree_print_dispatch(view->dispatch, view->root);
3125 }
3126 #endif
3127
3128 qemu_printf("\n");
3129 }
3130
3131 static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3132 gpointer user_data)
3133 {
3134 FlatView *view = key;
3135 GArray *fv_address_spaces = value;
3136
3137 g_array_unref(fv_address_spaces);
3138 flatview_unref(view);
3139
3140 return true;
3141 }
3142
3143 void mtree_info(bool flatview, bool dispatch_tree, bool owner, bool disabled)
3144 {
3145 MemoryRegionListHead ml_head;
3146 MemoryRegionList *ml, *ml2;
3147 AddressSpace *as;
3148
3149 if (flatview) {
3150 FlatView *view;
3151 struct FlatViewInfo fvi = {
3152 .counter = 0,
3153 .dispatch_tree = dispatch_tree,
3154 .owner = owner,
3155 };
3156 GArray *fv_address_spaces;
3157 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
3158 AccelClass *ac = ACCEL_GET_CLASS(current_accel());
3159
3160 if (ac->has_memory) {
3161 fvi.ac = ac;
3162 }
3163
3164 /* Gather all FVs in one table */
3165 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3166 view = address_space_get_flatview(as);
3167
3168 fv_address_spaces = g_hash_table_lookup(views, view);
3169 if (!fv_address_spaces) {
3170 fv_address_spaces = g_array_new(false, false, sizeof(as));
3171 g_hash_table_insert(views, view, fv_address_spaces);
3172 }
3173
3174 g_array_append_val(fv_address_spaces, as);
3175 }
3176
3177 /* Print */
3178 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3179
3180 /* Free */
3181 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3182 g_hash_table_unref(views);
3183
3184 return;
3185 }
3186
3187 QTAILQ_INIT(&ml_head);
3188
3189 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3190 qemu_printf("address-space: %s\n", as->name);
3191 mtree_print_mr(as->root, 1, 0, &ml_head, owner, disabled);
3192 qemu_printf("\n");
3193 }
3194
3195 /* print aliased regions */
3196 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
3197 qemu_printf("memory-region: %s\n", memory_region_name(ml->mr));
3198 mtree_print_mr(ml->mr, 1, 0, &ml_head, owner, disabled);
3199 qemu_printf("\n");
3200 }
3201
3202 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
3203 g_free(ml);
3204 }
3205 }
3206
3207 void memory_region_init_ram(MemoryRegion *mr,
3208 Object *owner,
3209 const char *name,
3210 uint64_t size,
3211 Error **errp)
3212 {
3213 DeviceState *owner_dev;
3214 Error *err = NULL;
3215
3216 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3217 if (err) {
3218 error_propagate(errp, err);
3219 return;
3220 }
3221 /* This will assert if owner is neither NULL nor a DeviceState.
3222 * We only want the owner here for the purposes of defining a
3223 * unique name for migration. TODO: Ideally we should implement
3224 * a naming scheme for Objects which are not DeviceStates, in
3225 * which case we can relax this restriction.
3226 */
3227 owner_dev = DEVICE(owner);
3228 vmstate_register_ram(mr, owner_dev);
3229 }
3230
3231 void memory_region_init_rom(MemoryRegion *mr,
3232 Object *owner,
3233 const char *name,
3234 uint64_t size,
3235 Error **errp)
3236 {
3237 DeviceState *owner_dev;
3238 Error *err = NULL;
3239
3240 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3241 if (err) {
3242 error_propagate(errp, err);
3243 return;
3244 }
3245 /* This will assert if owner is neither NULL nor a DeviceState.
3246 * We only want the owner here for the purposes of defining a
3247 * unique name for migration. TODO: Ideally we should implement
3248 * a naming scheme for Objects which are not DeviceStates, in
3249 * which case we can relax this restriction.
3250 */
3251 owner_dev = DEVICE(owner);
3252 vmstate_register_ram(mr, owner_dev);
3253 }
3254
3255 void memory_region_init_rom_device(MemoryRegion *mr,
3256 Object *owner,
3257 const MemoryRegionOps *ops,
3258 void *opaque,
3259 const char *name,
3260 uint64_t size,
3261 Error **errp)
3262 {
3263 DeviceState *owner_dev;
3264 Error *err = NULL;
3265
3266 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3267 name, size, &err);
3268 if (err) {
3269 error_propagate(errp, err);
3270 return;
3271 }
3272 /* This will assert if owner is neither NULL nor a DeviceState.
3273 * We only want the owner here for the purposes of defining a
3274 * unique name for migration. TODO: Ideally we should implement
3275 * a naming scheme for Objects which are not DeviceStates, in
3276 * which case we can relax this restriction.
3277 */
3278 owner_dev = DEVICE(owner);
3279 vmstate_register_ram(mr, owner_dev);
3280 }
3281
3282 /*
3283 * Support softmmu builds with CONFIG_FUZZ using a weak symbol and a stub for
3284 * the fuzz_dma_read_cb callback
3285 */
3286 #ifdef CONFIG_FUZZ
3287 void __attribute__((weak)) fuzz_dma_read_cb(size_t addr,
3288 size_t len,
3289 MemoryRegion *mr)
3290 {
3291 }
3292 #endif
3293
3294 static const TypeInfo memory_region_info = {
3295 .parent = TYPE_OBJECT,
3296 .name = TYPE_MEMORY_REGION,
3297 .class_size = sizeof(MemoryRegionClass),
3298 .instance_size = sizeof(MemoryRegion),
3299 .instance_init = memory_region_initfn,
3300 .instance_finalize = memory_region_finalize,
3301 };
3302
3303 static const TypeInfo iommu_memory_region_info = {
3304 .parent = TYPE_MEMORY_REGION,
3305 .name = TYPE_IOMMU_MEMORY_REGION,
3306 .class_size = sizeof(IOMMUMemoryRegionClass),
3307 .instance_size = sizeof(IOMMUMemoryRegion),
3308 .instance_init = iommu_memory_region_initfn,
3309 .abstract = true,
3310 };
3311
3312 static void memory_register_types(void)
3313 {
3314 type_register_static(&memory_region_info);
3315 type_register_static(&iommu_memory_region_info);
3316 }
3317
3318 type_init(memory_register_types)
AR7 emulation for QEMU