exec/memory: Use struct Object typedef
[qemu/ar7.git] / hw / ppc / virtex_ml507.c
blobb26ff177676a7401eea2c9fc37975dea98b2c42e
1 /*
2 * Model of Xilinx Virtex5 ML507 PPC-440 refdesign.
4 * Copyright (c) 2010 Edgar E. Iglesias.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #include "qemu/osdep.h"
26 #include "qemu-common.h"
27 #include "qemu/datadir.h"
28 #include "qemu/units.h"
29 #include "cpu.h"
30 #include "hw/sysbus.h"
31 #include "hw/char/serial.h"
32 #include "hw/block/flash.h"
33 #include "sysemu/sysemu.h"
34 #include "sysemu/qtest.h"
35 #include "sysemu/reset.h"
36 #include "hw/boards.h"
37 #include "sysemu/device_tree.h"
38 #include "hw/loader.h"
39 #include "elf.h"
40 #include "qapi/error.h"
41 #include "qemu/error-report.h"
42 #include "qemu/log.h"
43 #include "qemu/option.h"
44 #include "exec/address-spaces.h"
46 #include "hw/intc/ppc-uic.h"
47 #include "hw/ppc/ppc.h"
48 #include "hw/ppc/ppc4xx.h"
49 #include "hw/qdev-properties.h"
50 #include "ppc405.h"
52 #define EPAPR_MAGIC (0x45504150)
53 #define FLASH_SIZE (16 * MiB)
55 #define INTC_BASEADDR 0x81800000
56 #define UART16550_BASEADDR 0x83e01003
57 #define TIMER_BASEADDR 0x83c00000
58 #define PFLASH_BASEADDR 0xfc000000
60 #define TIMER_IRQ 3
61 #define UART16550_IRQ 9
63 static struct boot_info
65 uint32_t bootstrap_pc;
66 uint32_t cmdline;
67 uint32_t fdt;
68 uint32_t ima_size;
69 void *vfdt;
70 } boot_info;
72 /* Create reset TLB entries for BookE, spanning the 32bit addr space. */
73 static void mmubooke_create_initial_mapping(CPUPPCState *env,
74 target_ulong va,
75 hwaddr pa)
77 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
79 tlb->attr = 0;
80 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
81 tlb->size = 1U << 31; /* up to 0x80000000 */
82 tlb->EPN = va & TARGET_PAGE_MASK;
83 tlb->RPN = pa & TARGET_PAGE_MASK;
84 tlb->PID = 0;
86 tlb = &env->tlb.tlbe[1];
87 tlb->attr = 0;
88 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
89 tlb->size = 1U << 31; /* up to 0xffffffff */
90 tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
91 tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
92 tlb->PID = 0;
95 static PowerPCCPU *ppc440_init_xilinx(const char *cpu_type, uint32_t sysclk)
97 PowerPCCPU *cpu;
98 CPUPPCState *env;
99 DeviceState *uicdev;
100 SysBusDevice *uicsbd;
102 cpu = POWERPC_CPU(cpu_create(cpu_type));
103 env = &cpu->env;
105 ppc_booke_timers_init(cpu, sysclk, 0/* no flags */);
107 ppc_dcr_init(env, NULL, NULL);
109 /* interrupt controller */
110 uicdev = qdev_new(TYPE_PPC_UIC);
111 uicsbd = SYS_BUS_DEVICE(uicdev);
113 object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu),
114 &error_fatal);
115 sysbus_realize_and_unref(uicsbd, &error_fatal);
117 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
118 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]);
119 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT,
120 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]);
122 /* This board doesn't wire anything up to the inputs of the UIC. */
123 return cpu;
126 static void main_cpu_reset(void *opaque)
128 PowerPCCPU *cpu = opaque;
129 CPUPPCState *env = &cpu->env;
130 struct boot_info *bi = env->load_info;
132 cpu_reset(CPU(cpu));
133 /* Linux Kernel Parameters (passing device tree):
134 * r3: pointer to the fdt
135 * r4: 0
136 * r5: 0
137 * r6: epapr magic
138 * r7: size of IMA in bytes
139 * r8: 0
140 * r9: 0
142 env->gpr[1] = (16 * MiB) - 8;
143 /* Provide a device-tree. */
144 env->gpr[3] = bi->fdt;
145 env->nip = bi->bootstrap_pc;
147 /* Create a mapping for the kernel. */
148 mmubooke_create_initial_mapping(env, 0, 0);
149 env->gpr[6] = tswap32(EPAPR_MAGIC);
150 env->gpr[7] = bi->ima_size;
153 #define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb"
154 static int xilinx_load_device_tree(hwaddr addr,
155 uint32_t ramsize,
156 hwaddr initrd_base,
157 hwaddr initrd_size,
158 const char *kernel_cmdline)
160 char *path;
161 int fdt_size;
162 void *fdt = NULL;
163 int r;
164 const char *dtb_filename;
166 dtb_filename = current_machine->dtb;
167 if (dtb_filename) {
168 fdt = load_device_tree(dtb_filename, &fdt_size);
169 if (!fdt) {
170 error_report("Error while loading device tree file '%s'",
171 dtb_filename);
173 } else {
174 /* Try the local "ppc.dtb" override. */
175 fdt = load_device_tree("ppc.dtb", &fdt_size);
176 if (!fdt) {
177 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
178 if (path) {
179 fdt = load_device_tree(path, &fdt_size);
180 g_free(path);
184 if (!fdt) {
185 return 0;
188 r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
189 initrd_base);
190 if (r < 0) {
191 error_report("couldn't set /chosen/linux,initrd-start");
194 r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
195 (initrd_base + initrd_size));
196 if (r < 0) {
197 error_report("couldn't set /chosen/linux,initrd-end");
200 r = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
201 if (r < 0)
202 fprintf(stderr, "couldn't set /chosen/bootargs\n");
203 cpu_physical_memory_write(addr, fdt, fdt_size);
204 g_free(fdt);
205 return fdt_size;
208 static void virtex_init(MachineState *machine)
210 const char *kernel_filename = machine->kernel_filename;
211 const char *kernel_cmdline = machine->kernel_cmdline;
212 hwaddr initrd_base = 0;
213 int initrd_size = 0;
214 MemoryRegion *address_space_mem = get_system_memory();
215 DeviceState *dev;
216 PowerPCCPU *cpu;
217 CPUPPCState *env;
218 hwaddr ram_base = 0;
219 DriveInfo *dinfo;
220 qemu_irq irq[32], *cpu_irq;
221 int kernel_size;
222 int i;
224 /* init CPUs */
225 cpu = ppc440_init_xilinx(machine->cpu_type, 400000000);
226 env = &cpu->env;
228 if (env->mmu_model != POWERPC_MMU_BOOKE) {
229 error_report("MMU model %i not supported by this machine",
230 env->mmu_model);
231 exit(1);
234 qemu_register_reset(main_cpu_reset, cpu);
236 memory_region_add_subregion(address_space_mem, ram_base, machine->ram);
238 dinfo = drive_get(IF_PFLASH, 0, 0);
239 pflash_cfi01_register(PFLASH_BASEADDR, "virtex.flash", FLASH_SIZE,
240 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
241 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1);
243 cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT];
244 dev = qdev_new("xlnx.xps-intc");
245 qdev_prop_set_uint32(dev, "kind-of-intr", 0);
246 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
247 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
248 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]);
249 for (i = 0; i < 32; i++) {
250 irq[i] = qdev_get_gpio_in(dev, i);
253 serial_mm_init(address_space_mem, UART16550_BASEADDR, 2, irq[UART16550_IRQ],
254 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
256 /* 2 timers at irq 2 @ 62 Mhz. */
257 dev = qdev_new("xlnx.xps-timer");
258 qdev_prop_set_uint32(dev, "one-timer-only", 0);
259 qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
260 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
261 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
262 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
264 if (kernel_filename) {
265 uint64_t entry, high;
266 hwaddr boot_offset;
268 /* Boots a kernel elf binary. */
269 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
270 &entry, NULL, &high, NULL, 1, PPC_ELF_MACHINE,
271 0, 0);
272 boot_info.bootstrap_pc = entry & 0x00ffffff;
274 if (kernel_size < 0) {
275 boot_offset = 0x1200000;
276 /* If we failed loading ELF's try a raw image. */
277 kernel_size = load_image_targphys(kernel_filename,
278 boot_offset,
279 machine->ram_size);
280 boot_info.bootstrap_pc = boot_offset;
281 high = boot_info.bootstrap_pc + kernel_size + 8192;
284 boot_info.ima_size = kernel_size;
286 /* Load initrd. */
287 if (machine->initrd_filename) {
288 initrd_base = high = ROUND_UP(high, 4);
289 initrd_size = load_image_targphys(machine->initrd_filename,
290 high, machine->ram_size - high);
292 if (initrd_size < 0) {
293 error_report("couldn't load ram disk '%s'",
294 machine->initrd_filename);
295 exit(1);
297 high = ROUND_UP(high + initrd_size, 4);
300 /* Provide a device-tree. */
301 boot_info.fdt = high + (8192 * 2);
302 boot_info.fdt &= ~8191;
304 xilinx_load_device_tree(boot_info.fdt, machine->ram_size,
305 initrd_base, initrd_size,
306 kernel_cmdline);
308 env->load_info = &boot_info;
311 static void virtex_machine_init(MachineClass *mc)
313 mc->desc = "Xilinx Virtex ML507 reference design";
314 mc->init = virtex_init;
315 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440-xilinx");
316 mc->default_ram_id = "ram";
319 DEFINE_MACHINE("virtex-ml507", virtex_machine_init)