exec/memory: Use struct Object typedef
[qemu/ar7.git] / hw / ppc / spapr.c
blob85fe65f89476a3fece549c8037be29ebd763d6fd
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
27 #include "qemu/osdep.h"
28 #include "qemu-common.h"
29 #include "qemu/datadir.h"
30 #include "qapi/error.h"
31 #include "qapi/visitor.h"
32 #include "sysemu/sysemu.h"
33 #include "sysemu/hostmem.h"
34 #include "sysemu/numa.h"
35 #include "sysemu/qtest.h"
36 #include "sysemu/reset.h"
37 #include "sysemu/runstate.h"
38 #include "qemu/log.h"
39 #include "hw/fw-path-provider.h"
40 #include "elf.h"
41 #include "net/net.h"
42 #include "sysemu/device_tree.h"
43 #include "sysemu/cpus.h"
44 #include "sysemu/hw_accel.h"
45 #include "kvm_ppc.h"
46 #include "migration/misc.h"
47 #include "migration/qemu-file-types.h"
48 #include "migration/global_state.h"
49 #include "migration/register.h"
50 #include "migration/blocker.h"
51 #include "mmu-hash64.h"
52 #include "mmu-book3s-v3.h"
53 #include "cpu-models.h"
54 #include "hw/core/cpu.h"
56 #include "hw/boards.h"
57 #include "hw/ppc/ppc.h"
58 #include "hw/loader.h"
60 #include "hw/ppc/fdt.h"
61 #include "hw/ppc/spapr.h"
62 #include "hw/ppc/spapr_vio.h"
63 #include "hw/qdev-properties.h"
64 #include "hw/pci-host/spapr.h"
65 #include "hw/pci/msi.h"
67 #include "hw/pci/pci.h"
68 #include "hw/scsi/scsi.h"
69 #include "hw/virtio/virtio-scsi.h"
70 #include "hw/virtio/vhost-scsi-common.h"
72 #include "exec/address-spaces.h"
73 #include "exec/ram_addr.h"
74 #include "hw/usb.h"
75 #include "qemu/config-file.h"
76 #include "qemu/error-report.h"
77 #include "trace.h"
78 #include "hw/nmi.h"
79 #include "hw/intc/intc.h"
81 #include "hw/ppc/spapr_cpu_core.h"
82 #include "hw/mem/memory-device.h"
83 #include "hw/ppc/spapr_tpm_proxy.h"
84 #include "hw/ppc/spapr_nvdimm.h"
85 #include "hw/ppc/spapr_numa.h"
86 #include "hw/ppc/pef.h"
88 #include "monitor/monitor.h"
90 #include <libfdt.h>
92 /* SLOF memory layout:
94 * SLOF raw image loaded at 0, copies its romfs right below the flat
95 * device-tree, then position SLOF itself 31M below that
97 * So we set FW_OVERHEAD to 40MB which should account for all of that
98 * and more
100 * We load our kernel at 4M, leaving space for SLOF initial image
102 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
103 #define FW_MAX_SIZE 0x400000
104 #define FW_FILE_NAME "slof.bin"
105 #define FW_OVERHEAD 0x2800000
106 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
108 #define MIN_RMA_SLOF (128 * MiB)
110 #define PHANDLE_INTC 0x00001111
112 /* These two functions implement the VCPU id numbering: one to compute them
113 * all and one to identify thread 0 of a VCORE. Any change to the first one
114 * is likely to have an impact on the second one, so let's keep them close.
116 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index)
118 MachineState *ms = MACHINE(spapr);
119 unsigned int smp_threads = ms->smp.threads;
121 assert(spapr->vsmt);
122 return
123 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads;
125 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr,
126 PowerPCCPU *cpu)
128 assert(spapr->vsmt);
129 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0;
132 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque)
134 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
135 * and newer QEMUs don't even have them. In both cases, we don't want
136 * to send anything on the wire.
138 return false;
141 static const VMStateDescription pre_2_10_vmstate_dummy_icp = {
142 .name = "icp/server",
143 .version_id = 1,
144 .minimum_version_id = 1,
145 .needed = pre_2_10_vmstate_dummy_icp_needed,
146 .fields = (VMStateField[]) {
147 VMSTATE_UNUSED(4), /* uint32_t xirr */
148 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
149 VMSTATE_UNUSED(1), /* uint8_t mfrr */
150 VMSTATE_END_OF_LIST()
154 static void pre_2_10_vmstate_register_dummy_icp(int i)
156 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp,
157 (void *)(uintptr_t) i);
160 static void pre_2_10_vmstate_unregister_dummy_icp(int i)
162 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp,
163 (void *)(uintptr_t) i);
166 int spapr_max_server_number(SpaprMachineState *spapr)
168 MachineState *ms = MACHINE(spapr);
170 assert(spapr->vsmt);
171 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads);
174 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
175 int smt_threads)
177 int i, ret = 0;
178 uint32_t servers_prop[smt_threads];
179 uint32_t gservers_prop[smt_threads * 2];
180 int index = spapr_get_vcpu_id(cpu);
182 if (cpu->compat_pvr) {
183 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
184 if (ret < 0) {
185 return ret;
189 /* Build interrupt servers and gservers properties */
190 for (i = 0; i < smt_threads; i++) {
191 servers_prop[i] = cpu_to_be32(index + i);
192 /* Hack, direct the group queues back to cpu 0 */
193 gservers_prop[i*2] = cpu_to_be32(index + i);
194 gservers_prop[i*2 + 1] = 0;
196 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
197 servers_prop, sizeof(servers_prop));
198 if (ret < 0) {
199 return ret;
201 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
202 gservers_prop, sizeof(gservers_prop));
204 return ret;
207 static void spapr_dt_pa_features(SpaprMachineState *spapr,
208 PowerPCCPU *cpu,
209 void *fdt, int offset)
211 uint8_t pa_features_206[] = { 6, 0,
212 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
213 uint8_t pa_features_207[] = { 24, 0,
214 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
215 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
216 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
217 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
218 uint8_t pa_features_300[] = { 66, 0,
219 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
220 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
221 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
222 /* 6: DS207 */
223 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
224 /* 16: Vector */
225 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
226 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
227 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
228 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
229 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
230 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
231 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
232 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
233 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
234 /* 42: PM, 44: PC RA, 46: SC vec'd */
235 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
236 /* 48: SIMD, 50: QP BFP, 52: String */
237 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
238 /* 54: DecFP, 56: DecI, 58: SHA */
239 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
240 /* 60: NM atomic, 62: RNG */
241 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
243 uint8_t *pa_features = NULL;
244 size_t pa_size;
246 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) {
247 pa_features = pa_features_206;
248 pa_size = sizeof(pa_features_206);
250 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) {
251 pa_features = pa_features_207;
252 pa_size = sizeof(pa_features_207);
254 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) {
255 pa_features = pa_features_300;
256 pa_size = sizeof(pa_features_300);
258 if (!pa_features) {
259 return;
262 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
264 * Note: we keep CI large pages off by default because a 64K capable
265 * guest provisioned with large pages might otherwise try to map a qemu
266 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
267 * even if that qemu runs on a 4k host.
268 * We dd this bit back here if we are confident this is not an issue
270 pa_features[3] |= 0x20;
272 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) {
273 pa_features[24] |= 0x80; /* Transactional memory support */
275 if (spapr->cas_pre_isa3_guest && pa_size > 40) {
276 /* Workaround for broken kernels that attempt (guest) radix
277 * mode when they can't handle it, if they see the radix bit set
278 * in pa-features. So hide it from them. */
279 pa_features[40 + 2] &= ~0x80; /* Radix MMU */
282 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
285 static hwaddr spapr_node0_size(MachineState *machine)
287 if (machine->numa_state->num_nodes) {
288 int i;
289 for (i = 0; i < machine->numa_state->num_nodes; ++i) {
290 if (machine->numa_state->nodes[i].node_mem) {
291 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem),
292 machine->ram_size);
296 return machine->ram_size;
299 static void add_str(GString *s, const gchar *s1)
301 g_string_append_len(s, s1, strlen(s1) + 1);
304 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid,
305 hwaddr start, hwaddr size)
307 char mem_name[32];
308 uint64_t mem_reg_property[2];
309 int off;
311 mem_reg_property[0] = cpu_to_be64(start);
312 mem_reg_property[1] = cpu_to_be64(size);
314 sprintf(mem_name, "memory@%" HWADDR_PRIx, start);
315 off = fdt_add_subnode(fdt, 0, mem_name);
316 _FDT(off);
317 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
318 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
319 sizeof(mem_reg_property))));
320 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid);
321 return off;
324 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr)
326 MemoryDeviceInfoList *info;
328 for (info = list; info; info = info->next) {
329 MemoryDeviceInfo *value = info->value;
331 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) {
332 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data;
334 if (addr >= pcdimm_info->addr &&
335 addr < (pcdimm_info->addr + pcdimm_info->size)) {
336 return pcdimm_info->node;
341 return -1;
344 struct sPAPRDrconfCellV2 {
345 uint32_t seq_lmbs;
346 uint64_t base_addr;
347 uint32_t drc_index;
348 uint32_t aa_index;
349 uint32_t flags;
350 } QEMU_PACKED;
352 typedef struct DrconfCellQueue {
353 struct sPAPRDrconfCellV2 cell;
354 QSIMPLEQ_ENTRY(DrconfCellQueue) entry;
355 } DrconfCellQueue;
357 static DrconfCellQueue *
358 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr,
359 uint32_t drc_index, uint32_t aa_index,
360 uint32_t flags)
362 DrconfCellQueue *elem;
364 elem = g_malloc0(sizeof(*elem));
365 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs);
366 elem->cell.base_addr = cpu_to_be64(base_addr);
367 elem->cell.drc_index = cpu_to_be32(drc_index);
368 elem->cell.aa_index = cpu_to_be32(aa_index);
369 elem->cell.flags = cpu_to_be32(flags);
371 return elem;
374 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt,
375 int offset, MemoryDeviceInfoList *dimms)
377 MachineState *machine = MACHINE(spapr);
378 uint8_t *int_buf, *cur_index;
379 int ret;
380 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
381 uint64_t addr, cur_addr, size;
382 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size);
383 uint64_t mem_end = machine->device_memory->base +
384 memory_region_size(&machine->device_memory->mr);
385 uint32_t node, buf_len, nr_entries = 0;
386 SpaprDrc *drc;
387 DrconfCellQueue *elem, *next;
388 MemoryDeviceInfoList *info;
389 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue
390 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue);
392 /* Entry to cover RAM and the gap area */
393 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1,
394 SPAPR_LMB_FLAGS_RESERVED |
395 SPAPR_LMB_FLAGS_DRC_INVALID);
396 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
397 nr_entries++;
399 cur_addr = machine->device_memory->base;
400 for (info = dimms; info; info = info->next) {
401 PCDIMMDeviceInfo *di = info->value->u.dimm.data;
403 addr = di->addr;
404 size = di->size;
405 node = di->node;
408 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The
409 * area is marked hotpluggable in the next iteration for the bigger
410 * chunk including the NVDIMM occupied area.
412 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM)
413 continue;
415 /* Entry for hot-pluggable area */
416 if (cur_addr < addr) {
417 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
418 g_assert(drc);
419 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size,
420 cur_addr, spapr_drc_index(drc), -1, 0);
421 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
422 nr_entries++;
425 /* Entry for DIMM */
426 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size);
427 g_assert(drc);
428 elem = spapr_get_drconf_cell(size / lmb_size, addr,
429 spapr_drc_index(drc), node,
430 (SPAPR_LMB_FLAGS_ASSIGNED |
431 SPAPR_LMB_FLAGS_HOTREMOVABLE));
432 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
433 nr_entries++;
434 cur_addr = addr + size;
437 /* Entry for remaining hotpluggable area */
438 if (cur_addr < mem_end) {
439 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size);
440 g_assert(drc);
441 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size,
442 cur_addr, spapr_drc_index(drc), -1, 0);
443 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry);
444 nr_entries++;
447 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t);
448 int_buf = cur_index = g_malloc0(buf_len);
449 *(uint32_t *)int_buf = cpu_to_be32(nr_entries);
450 cur_index += sizeof(nr_entries);
452 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) {
453 memcpy(cur_index, &elem->cell, sizeof(elem->cell));
454 cur_index += sizeof(elem->cell);
455 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry);
456 g_free(elem);
459 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len);
460 g_free(int_buf);
461 if (ret < 0) {
462 return -1;
464 return 0;
467 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt,
468 int offset, MemoryDeviceInfoList *dimms)
470 MachineState *machine = MACHINE(spapr);
471 int i, ret;
472 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
473 uint32_t device_lmb_start = machine->device_memory->base / lmb_size;
474 uint32_t nr_lmbs = (machine->device_memory->base +
475 memory_region_size(&machine->device_memory->mr)) /
476 lmb_size;
477 uint32_t *int_buf, *cur_index, buf_len;
480 * Allocate enough buffer size to fit in ibm,dynamic-memory
482 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t);
483 cur_index = int_buf = g_malloc0(buf_len);
484 int_buf[0] = cpu_to_be32(nr_lmbs);
485 cur_index++;
486 for (i = 0; i < nr_lmbs; i++) {
487 uint64_t addr = i * lmb_size;
488 uint32_t *dynamic_memory = cur_index;
490 if (i >= device_lmb_start) {
491 SpaprDrc *drc;
493 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i);
494 g_assert(drc);
496 dynamic_memory[0] = cpu_to_be32(addr >> 32);
497 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
498 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc));
499 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
500 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr));
501 if (memory_region_present(get_system_memory(), addr)) {
502 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
503 } else {
504 dynamic_memory[5] = cpu_to_be32(0);
506 } else {
508 * LMB information for RMA, boot time RAM and gap b/n RAM and
509 * device memory region -- all these are marked as reserved
510 * and as having no valid DRC.
512 dynamic_memory[0] = cpu_to_be32(addr >> 32);
513 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
514 dynamic_memory[2] = cpu_to_be32(0);
515 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
516 dynamic_memory[4] = cpu_to_be32(-1);
517 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
518 SPAPR_LMB_FLAGS_DRC_INVALID);
521 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
523 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
524 g_free(int_buf);
525 if (ret < 0) {
526 return -1;
528 return 0;
532 * Adds ibm,dynamic-reconfiguration-memory node.
533 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
534 * of this device tree node.
536 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr,
537 void *fdt)
539 MachineState *machine = MACHINE(spapr);
540 int ret, offset;
541 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
542 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32),
543 cpu_to_be32(lmb_size & 0xffffffff)};
544 MemoryDeviceInfoList *dimms = NULL;
547 * Don't create the node if there is no device memory
549 if (machine->ram_size == machine->maxram_size) {
550 return 0;
553 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
555 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
556 sizeof(prop_lmb_size));
557 if (ret < 0) {
558 return ret;
561 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
562 if (ret < 0) {
563 return ret;
566 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
567 if (ret < 0) {
568 return ret;
571 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
572 dimms = qmp_memory_device_list();
573 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) {
574 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms);
575 } else {
576 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms);
578 qapi_free_MemoryDeviceInfoList(dimms);
580 if (ret < 0) {
581 return ret;
584 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset);
586 return ret;
589 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt)
591 MachineState *machine = MACHINE(spapr);
592 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
593 hwaddr mem_start, node_size;
594 int i, nb_nodes = machine->numa_state->num_nodes;
595 NodeInfo *nodes = machine->numa_state->nodes;
597 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
598 if (!nodes[i].node_mem) {
599 continue;
601 if (mem_start >= machine->ram_size) {
602 node_size = 0;
603 } else {
604 node_size = nodes[i].node_mem;
605 if (node_size > machine->ram_size - mem_start) {
606 node_size = machine->ram_size - mem_start;
609 if (!mem_start) {
610 /* spapr_machine_init() checks for rma_size <= node0_size
611 * already */
612 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size);
613 mem_start += spapr->rma_size;
614 node_size -= spapr->rma_size;
616 for ( ; node_size; ) {
617 hwaddr sizetmp = pow2floor(node_size);
619 /* mem_start != 0 here */
620 if (ctzl(mem_start) < ctzl(sizetmp)) {
621 sizetmp = 1ULL << ctzl(mem_start);
624 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp);
625 node_size -= sizetmp;
626 mem_start += sizetmp;
630 /* Generate ibm,dynamic-reconfiguration-memory node if required */
631 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) {
632 int ret;
634 g_assert(smc->dr_lmb_enabled);
635 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt);
636 if (ret) {
637 return ret;
641 return 0;
644 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset,
645 SpaprMachineState *spapr)
647 MachineState *ms = MACHINE(spapr);
648 PowerPCCPU *cpu = POWERPC_CPU(cs);
649 CPUPPCState *env = &cpu->env;
650 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
651 int index = spapr_get_vcpu_id(cpu);
652 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
653 0xffffffff, 0xffffffff};
654 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
655 : SPAPR_TIMEBASE_FREQ;
656 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
657 uint32_t page_sizes_prop[64];
658 size_t page_sizes_prop_size;
659 unsigned int smp_threads = ms->smp.threads;
660 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores;
661 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
662 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
663 SpaprDrc *drc;
664 int drc_index;
665 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
666 int i;
668 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index);
669 if (drc) {
670 drc_index = spapr_drc_index(drc);
671 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
674 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
675 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
677 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
678 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
679 env->dcache_line_size)));
680 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
681 env->dcache_line_size)));
682 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
683 env->icache_line_size)));
684 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
685 env->icache_line_size)));
687 if (pcc->l1_dcache_size) {
688 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
689 pcc->l1_dcache_size)));
690 } else {
691 warn_report("Unknown L1 dcache size for cpu");
693 if (pcc->l1_icache_size) {
694 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
695 pcc->l1_icache_size)));
696 } else {
697 warn_report("Unknown L1 icache size for cpu");
700 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
701 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
702 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size)));
703 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size)));
704 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
705 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
707 if (env->spr_cb[SPR_PURR].oea_read) {
708 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1)));
710 if (env->spr_cb[SPR_SPURR].oea_read) {
711 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1)));
714 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
715 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
716 segs, sizeof(segs))));
719 /* Advertise VSX (vector extensions) if available
720 * 1 == VMX / Altivec available
721 * 2 == VSX available
723 * Only CPUs for which we create core types in spapr_cpu_core.c
724 * are possible, and all of those have VMX */
725 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) {
726 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2)));
727 } else {
728 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1)));
731 /* Advertise DFP (Decimal Floating Point) if available
732 * 0 / no property == no DFP
733 * 1 == DFP available */
734 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) {
735 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
738 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
739 sizeof(page_sizes_prop));
740 if (page_sizes_prop_size) {
741 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
742 page_sizes_prop, page_sizes_prop_size)));
745 spapr_dt_pa_features(spapr, cpu, fdt, offset);
747 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
748 cs->cpu_index / vcpus_per_socket)));
750 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
751 pft_size_prop, sizeof(pft_size_prop))));
753 if (ms->numa_state->num_nodes > 1) {
754 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu));
757 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
759 if (pcc->radix_page_info) {
760 for (i = 0; i < pcc->radix_page_info->count; i++) {
761 radix_AP_encodings[i] =
762 cpu_to_be32(pcc->radix_page_info->entries[i]);
764 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings",
765 radix_AP_encodings,
766 pcc->radix_page_info->count *
767 sizeof(radix_AP_encodings[0]))));
771 * We set this property to let the guest know that it can use the large
772 * decrementer and its width in bits.
774 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF)
775 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits",
776 pcc->lrg_decr_bits)));
779 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr)
781 CPUState **rev;
782 CPUState *cs;
783 int n_cpus;
784 int cpus_offset;
785 int i;
787 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
788 _FDT(cpus_offset);
789 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
790 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
793 * We walk the CPUs in reverse order to ensure that CPU DT nodes
794 * created by fdt_add_subnode() end up in the right order in FDT
795 * for the guest kernel the enumerate the CPUs correctly.
797 * The CPU list cannot be traversed in reverse order, so we need
798 * to do extra work.
800 n_cpus = 0;
801 rev = NULL;
802 CPU_FOREACH(cs) {
803 rev = g_renew(CPUState *, rev, n_cpus + 1);
804 rev[n_cpus++] = cs;
807 for (i = n_cpus - 1; i >= 0; i--) {
808 CPUState *cs = rev[i];
809 PowerPCCPU *cpu = POWERPC_CPU(cs);
810 int index = spapr_get_vcpu_id(cpu);
811 DeviceClass *dc = DEVICE_GET_CLASS(cs);
812 g_autofree char *nodename = NULL;
813 int offset;
815 if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
816 continue;
819 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
820 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
821 _FDT(offset);
822 spapr_dt_cpu(cs, fdt, offset, spapr);
825 g_free(rev);
828 static int spapr_dt_rng(void *fdt)
830 int node;
831 int ret;
833 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities");
834 if (node <= 0) {
835 return -1;
837 ret = fdt_setprop_string(fdt, node, "device_type",
838 "ibm,platform-facilities");
839 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1);
840 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0);
842 node = fdt_add_subnode(fdt, node, "ibm,random-v1");
843 if (node <= 0) {
844 return -1;
846 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random");
848 return ret ? -1 : 0;
851 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt)
853 MachineState *ms = MACHINE(spapr);
854 int rtas;
855 GString *hypertas = g_string_sized_new(256);
856 GString *qemu_hypertas = g_string_sized_new(256);
857 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base +
858 memory_region_size(&MACHINE(spapr)->device_memory->mr);
859 uint32_t lrdr_capacity[] = {
860 cpu_to_be32(max_device_addr >> 32),
861 cpu_to_be32(max_device_addr & 0xffffffff),
862 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32),
863 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff),
864 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads),
867 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
869 /* hypertas */
870 add_str(hypertas, "hcall-pft");
871 add_str(hypertas, "hcall-term");
872 add_str(hypertas, "hcall-dabr");
873 add_str(hypertas, "hcall-interrupt");
874 add_str(hypertas, "hcall-tce");
875 add_str(hypertas, "hcall-vio");
876 add_str(hypertas, "hcall-splpar");
877 add_str(hypertas, "hcall-join");
878 add_str(hypertas, "hcall-bulk");
879 add_str(hypertas, "hcall-set-mode");
880 add_str(hypertas, "hcall-sprg0");
881 add_str(hypertas, "hcall-copy");
882 add_str(hypertas, "hcall-debug");
883 add_str(hypertas, "hcall-vphn");
884 add_str(qemu_hypertas, "hcall-memop1");
886 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
887 add_str(hypertas, "hcall-multi-tce");
890 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
891 add_str(hypertas, "hcall-hpt-resize");
894 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
895 hypertas->str, hypertas->len));
896 g_string_free(hypertas, TRUE);
897 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
898 qemu_hypertas->str, qemu_hypertas->len));
899 g_string_free(qemu_hypertas, TRUE);
901 spapr_numa_write_rtas_dt(spapr, fdt, rtas);
904 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log,
905 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes.
907 * The system reset requirements are driven by existing Linux and PowerVM
908 * implementation which (contrary to PAPR) saves r3 in the error log
909 * structure like machine check, so Linux expects to find the saved r3
910 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and
911 * does not look at the error value).
913 * System reset interrupts are not subject to interlock like machine
914 * check, so this memory area could be corrupted if the sreset is
915 * interrupted by a machine check (or vice versa) if it was shared. To
916 * prevent this, system reset uses per-CPU areas for the sreset save
917 * area. A system reset that interrupts a system reset handler could
918 * still overwrite this area, but Linux doesn't try to recover in that
919 * case anyway.
921 * The extra 8 bytes is required because Linux's FWNMI error log check
922 * is off-by-one.
924 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_ERROR_LOG_MAX +
925 ms->smp.max_cpus * sizeof(uint64_t)*2 + sizeof(uint64_t)));
926 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
927 RTAS_ERROR_LOG_MAX));
928 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
929 RTAS_EVENT_SCAN_RATE));
931 g_assert(msi_nonbroken);
932 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
935 * According to PAPR, rtas ibm,os-term does not guarantee a return
936 * back to the guest cpu.
938 * While an additional ibm,extended-os-term property indicates
939 * that rtas call return will always occur. Set this property.
941 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
943 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
944 lrdr_capacity, sizeof(lrdr_capacity)));
946 spapr_dt_rtas_tokens(fdt, rtas);
950 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU
951 * and the XIVE features that the guest may request and thus the valid
952 * values for bytes 23..26 of option vector 5:
954 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt,
955 int chosen)
957 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
959 char val[2 * 4] = {
960 23, 0x00, /* XICS / XIVE mode */
961 24, 0x00, /* Hash/Radix, filled in below. */
962 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
963 26, 0x40, /* Radix options: GTSE == yes. */
966 if (spapr->irq->xics && spapr->irq->xive) {
967 val[1] = SPAPR_OV5_XIVE_BOTH;
968 } else if (spapr->irq->xive) {
969 val[1] = SPAPR_OV5_XIVE_EXPLOIT;
970 } else {
971 assert(spapr->irq->xics);
972 val[1] = SPAPR_OV5_XIVE_LEGACY;
975 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
976 first_ppc_cpu->compat_pvr)) {
978 * If we're in a pre POWER9 compat mode then the guest should
979 * do hash and use the legacy interrupt mode
981 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */
982 val[3] = 0x00; /* Hash */
983 } else if (kvm_enabled()) {
984 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
985 val[3] = 0x80; /* OV5_MMU_BOTH */
986 } else if (kvmppc_has_cap_mmu_radix()) {
987 val[3] = 0x40; /* OV5_MMU_RADIX_300 */
988 } else {
989 val[3] = 0x00; /* Hash */
991 } else {
992 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
993 val[3] = 0xC0;
995 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
996 val, sizeof(val)));
999 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset)
1001 MachineState *machine = MACHINE(spapr);
1002 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1003 int chosen;
1005 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
1007 if (reset) {
1008 const char *boot_device = machine->boot_order;
1009 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
1010 size_t cb = 0;
1011 char *bootlist = get_boot_devices_list(&cb);
1013 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) {
1014 _FDT(fdt_setprop_string(fdt, chosen, "bootargs",
1015 machine->kernel_cmdline));
1018 if (spapr->initrd_size) {
1019 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
1020 spapr->initrd_base));
1021 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
1022 spapr->initrd_base + spapr->initrd_size));
1025 if (spapr->kernel_size) {
1026 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr),
1027 cpu_to_be64(spapr->kernel_size) };
1029 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
1030 &kprop, sizeof(kprop)));
1031 if (spapr->kernel_le) {
1032 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
1035 if (boot_menu) {
1036 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
1038 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
1039 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
1040 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
1042 if (cb && bootlist) {
1043 int i;
1045 for (i = 0; i < cb; i++) {
1046 if (bootlist[i] == '\n') {
1047 bootlist[i] = ' ';
1050 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
1053 if (boot_device && strlen(boot_device)) {
1054 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
1057 if (!spapr->has_graphics && stdout_path) {
1059 * "linux,stdout-path" and "stdout" properties are
1060 * deprecated by linux kernel. New platforms should only
1061 * use the "stdout-path" property. Set the new property
1062 * and continue using older property to remain compatible
1063 * with the existing firmware.
1065 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
1066 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path));
1070 * We can deal with BAR reallocation just fine, advertise it
1071 * to the guest
1073 if (smc->linux_pci_probe) {
1074 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0));
1077 spapr_dt_ov5_platform_support(spapr, fdt, chosen);
1079 g_free(stdout_path);
1080 g_free(bootlist);
1083 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5"));
1086 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt)
1088 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1089 * KVM to work under pHyp with some guest co-operation */
1090 int hypervisor;
1091 uint8_t hypercall[16];
1093 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
1094 /* indicate KVM hypercall interface */
1095 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
1096 if (kvmppc_has_cap_fixup_hcalls()) {
1098 * Older KVM versions with older guest kernels were broken
1099 * with the magic page, don't allow the guest to map it.
1101 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
1102 sizeof(hypercall))) {
1103 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
1104 hypercall, sizeof(hypercall)));
1109 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space)
1111 MachineState *machine = MACHINE(spapr);
1112 MachineClass *mc = MACHINE_GET_CLASS(machine);
1113 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1114 uint32_t root_drc_type_mask = 0;
1115 int ret;
1116 void *fdt;
1117 SpaprPhbState *phb;
1118 char *buf;
1120 fdt = g_malloc0(space);
1121 _FDT((fdt_create_empty_tree(fdt, space)));
1123 /* Root node */
1124 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
1125 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
1126 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
1128 /* Guest UUID & Name*/
1129 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
1130 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
1131 if (qemu_uuid_set) {
1132 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
1134 g_free(buf);
1136 if (qemu_get_vm_name()) {
1137 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
1138 qemu_get_vm_name()));
1141 /* Host Model & Serial Number */
1142 if (spapr->host_model) {
1143 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model));
1144 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) {
1145 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
1146 g_free(buf);
1149 if (spapr->host_serial) {
1150 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial));
1151 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) {
1152 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
1153 g_free(buf);
1156 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
1157 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
1159 /* /interrupt controller */
1160 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC);
1162 ret = spapr_dt_memory(spapr, fdt);
1163 if (ret < 0) {
1164 error_report("couldn't setup memory nodes in fdt");
1165 exit(1);
1168 /* /vdevice */
1169 spapr_dt_vdevice(spapr->vio_bus, fdt);
1171 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
1172 ret = spapr_dt_rng(fdt);
1173 if (ret < 0) {
1174 error_report("could not set up rng device in the fdt");
1175 exit(1);
1179 QLIST_FOREACH(phb, &spapr->phbs, list) {
1180 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL);
1181 if (ret < 0) {
1182 error_report("couldn't setup PCI devices in fdt");
1183 exit(1);
1187 spapr_dt_cpus(fdt, spapr);
1189 /* ibm,drc-indexes and friends */
1190 if (smc->dr_lmb_enabled) {
1191 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB;
1193 if (smc->dr_phb_enabled) {
1194 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB;
1196 if (mc->nvdimm_supported) {
1197 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM;
1199 if (root_drc_type_mask) {
1200 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask));
1203 if (mc->has_hotpluggable_cpus) {
1204 int offset = fdt_path_offset(fdt, "/cpus");
1205 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU);
1206 if (ret < 0) {
1207 error_report("Couldn't set up CPU DR device tree properties");
1208 exit(1);
1212 /* /event-sources */
1213 spapr_dt_events(spapr, fdt);
1215 /* /rtas */
1216 spapr_dt_rtas(spapr, fdt);
1218 /* /chosen */
1219 spapr_dt_chosen(spapr, fdt, reset);
1221 /* /hypervisor */
1222 if (kvm_enabled()) {
1223 spapr_dt_hypervisor(spapr, fdt);
1226 /* Build memory reserve map */
1227 if (reset) {
1228 if (spapr->kernel_size) {
1229 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr,
1230 spapr->kernel_size)));
1232 if (spapr->initrd_size) {
1233 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base,
1234 spapr->initrd_size)));
1238 /* NVDIMM devices */
1239 if (mc->nvdimm_supported) {
1240 spapr_dt_persistent_memory(spapr, fdt);
1243 return fdt;
1246 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1248 SpaprMachineState *spapr = opaque;
1250 return (addr & 0x0fffffff) + spapr->kernel_addr;
1253 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1254 PowerPCCPU *cpu)
1256 CPUPPCState *env = &cpu->env;
1258 /* The TCG path should also be holding the BQL at this point */
1259 g_assert(qemu_mutex_iothread_locked());
1261 if (msr_pr) {
1262 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1263 env->gpr[3] = H_PRIVILEGE;
1264 } else {
1265 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1269 struct LPCRSyncState {
1270 target_ulong value;
1271 target_ulong mask;
1274 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg)
1276 struct LPCRSyncState *s = arg.host_ptr;
1277 PowerPCCPU *cpu = POWERPC_CPU(cs);
1278 CPUPPCState *env = &cpu->env;
1279 target_ulong lpcr;
1281 cpu_synchronize_state(cs);
1282 lpcr = env->spr[SPR_LPCR];
1283 lpcr &= ~s->mask;
1284 lpcr |= s->value;
1285 ppc_store_lpcr(cpu, lpcr);
1288 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask)
1290 CPUState *cs;
1291 struct LPCRSyncState s = {
1292 .value = value,
1293 .mask = mask
1295 CPU_FOREACH(cs) {
1296 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s));
1300 static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry)
1302 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1304 /* Copy PATE1:GR into PATE0:HR */
1305 entry->dw0 = spapr->patb_entry & PATE0_HR;
1306 entry->dw1 = spapr->patb_entry;
1309 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1310 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1311 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1312 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1313 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1316 * Get the fd to access the kernel htab, re-opening it if necessary
1318 static int get_htab_fd(SpaprMachineState *spapr)
1320 Error *local_err = NULL;
1322 if (spapr->htab_fd >= 0) {
1323 return spapr->htab_fd;
1326 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err);
1327 if (spapr->htab_fd < 0) {
1328 error_report_err(local_err);
1331 return spapr->htab_fd;
1334 void close_htab_fd(SpaprMachineState *spapr)
1336 if (spapr->htab_fd >= 0) {
1337 close(spapr->htab_fd);
1339 spapr->htab_fd = -1;
1342 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1344 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1346 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1349 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
1351 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1353 assert(kvm_enabled());
1355 if (!spapr->htab) {
1356 return 0;
1359 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18);
1362 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1363 hwaddr ptex, int n)
1365 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1366 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1368 if (!spapr->htab) {
1370 * HTAB is controlled by KVM. Fetch into temporary buffer
1372 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1373 kvmppc_read_hptes(hptes, ptex, n);
1374 return hptes;
1378 * HTAB is controlled by QEMU. Just point to the internally
1379 * accessible PTEG.
1381 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1384 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1385 const ppc_hash_pte64_t *hptes,
1386 hwaddr ptex, int n)
1388 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1390 if (!spapr->htab) {
1391 g_free((void *)hptes);
1394 /* Nothing to do for qemu managed HPT */
1397 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
1398 uint64_t pte0, uint64_t pte1)
1400 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp);
1401 hwaddr offset = ptex * HASH_PTE_SIZE_64;
1403 if (!spapr->htab) {
1404 kvmppc_write_hpte(ptex, pte0, pte1);
1405 } else {
1406 if (pte0 & HPTE64_V_VALID) {
1407 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1409 * When setting valid, we write PTE1 first. This ensures
1410 * proper synchronization with the reading code in
1411 * ppc_hash64_pteg_search()
1413 smp_wmb();
1414 stq_p(spapr->htab + offset, pte0);
1415 } else {
1416 stq_p(spapr->htab + offset, pte0);
1418 * When clearing it we set PTE0 first. This ensures proper
1419 * synchronization with the reading code in
1420 * ppc_hash64_pteg_search()
1422 smp_wmb();
1423 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1428 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1429 uint64_t pte1)
1431 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 15;
1432 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1434 if (!spapr->htab) {
1435 /* There should always be a hash table when this is called */
1436 error_report("spapr_hpte_set_c called with no hash table !");
1437 return;
1440 /* The HW performs a non-atomic byte update */
1441 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80);
1444 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1445 uint64_t pte1)
1447 hwaddr offset = ptex * HASH_PTE_SIZE_64 + 14;
1448 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
1450 if (!spapr->htab) {
1451 /* There should always be a hash table when this is called */
1452 error_report("spapr_hpte_set_r called with no hash table !");
1453 return;
1456 /* The HW performs a non-atomic byte update */
1457 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01);
1460 int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1462 int shift;
1464 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1465 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1466 * that's much more than is needed for Linux guests */
1467 shift = ctz64(pow2ceil(ramsize)) - 7;
1468 shift = MAX(shift, 18); /* Minimum architected size */
1469 shift = MIN(shift, 46); /* Maximum architected size */
1470 return shift;
1473 void spapr_free_hpt(SpaprMachineState *spapr)
1475 g_free(spapr->htab);
1476 spapr->htab = NULL;
1477 spapr->htab_shift = 0;
1478 close_htab_fd(spapr);
1481 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp)
1483 ERRP_GUARD();
1484 long rc;
1486 /* Clean up any HPT info from a previous boot */
1487 spapr_free_hpt(spapr);
1489 rc = kvmppc_reset_htab(shift);
1491 if (rc == -EOPNOTSUPP) {
1492 error_setg(errp, "HPT not supported in nested guests");
1493 return -EOPNOTSUPP;
1496 if (rc < 0) {
1497 /* kernel-side HPT needed, but couldn't allocate one */
1498 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d",
1499 shift);
1500 error_append_hint(errp, "Try smaller maxmem?\n");
1501 return -errno;
1502 } else if (rc > 0) {
1503 /* kernel-side HPT allocated */
1504 if (rc != shift) {
1505 error_setg(errp,
1506 "Requested order %d HPT, but kernel allocated order %ld",
1507 shift, rc);
1508 error_append_hint(errp, "Try smaller maxmem?\n");
1509 return -ENOSPC;
1512 spapr->htab_shift = shift;
1513 spapr->htab = NULL;
1514 } else {
1515 /* kernel-side HPT not needed, allocate in userspace instead */
1516 size_t size = 1ULL << shift;
1517 int i;
1519 spapr->htab = qemu_memalign(size, size);
1520 memset(spapr->htab, 0, size);
1521 spapr->htab_shift = shift;
1523 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1524 DIRTY_HPTE(HPTE(spapr->htab, i));
1527 /* We're setting up a hash table, so that means we're not radix */
1528 spapr->patb_entry = 0;
1529 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT);
1530 return 0;
1533 void spapr_setup_hpt(SpaprMachineState *spapr)
1535 int hpt_shift;
1537 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) {
1538 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1539 } else {
1540 uint64_t current_ram_size;
1542 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size();
1543 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size);
1545 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal);
1547 if (kvm_enabled()) {
1548 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift);
1550 /* Check our RMA fits in the possible VRMA */
1551 if (vrma_limit < spapr->rma_size) {
1552 error_report("Unable to create %" HWADDR_PRIu
1553 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB",
1554 spapr->rma_size / MiB, vrma_limit / MiB);
1555 exit(EXIT_FAILURE);
1560 static void spapr_machine_reset(MachineState *machine)
1562 SpaprMachineState *spapr = SPAPR_MACHINE(machine);
1563 PowerPCCPU *first_ppc_cpu;
1564 hwaddr fdt_addr;
1565 void *fdt;
1566 int rc;
1568 pef_kvm_reset(machine->cgs, &error_fatal);
1569 spapr_caps_apply(spapr);
1571 first_ppc_cpu = POWERPC_CPU(first_cpu);
1572 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1573 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
1574 spapr->max_compat_pvr)) {
1576 * If using KVM with radix mode available, VCPUs can be started
1577 * without a HPT because KVM will start them in radix mode.
1578 * Set the GR bit in PATE so that we know there is no HPT.
1580 spapr->patb_entry = PATE1_GR;
1581 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT);
1582 } else {
1583 spapr_setup_hpt(spapr);
1586 qemu_devices_reset();
1588 spapr_ovec_cleanup(spapr->ov5_cas);
1589 spapr->ov5_cas = spapr_ovec_new();
1591 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal);
1594 * This is fixing some of the default configuration of the XIVE
1595 * devices. To be called after the reset of the machine devices.
1597 spapr_irq_reset(spapr, &error_fatal);
1600 * There is no CAS under qtest. Simulate one to please the code that
1601 * depends on spapr->ov5_cas. This is especially needed to test device
1602 * unplug, so we do that before resetting the DRCs.
1604 if (qtest_enabled()) {
1605 spapr_ovec_cleanup(spapr->ov5_cas);
1606 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5);
1609 /* DRC reset may cause a device to be unplugged. This will cause troubles
1610 * if this device is used by another device (eg, a running vhost backend
1611 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1612 * situations, we reset DRCs after all devices have been reset.
1614 spapr_drc_reset_all(spapr);
1616 spapr_clear_pending_events(spapr);
1619 * We place the device tree and RTAS just below either the top of the RMA,
1620 * or just below 2GB, whichever is lower, so that it can be
1621 * processed with 32-bit real mode code if necessary
1623 fdt_addr = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FDT_MAX_SIZE;
1625 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE);
1627 rc = fdt_pack(fdt);
1629 /* Should only fail if we've built a corrupted tree */
1630 assert(rc == 0);
1632 /* Load the fdt */
1633 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1634 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1635 g_free(spapr->fdt_blob);
1636 spapr->fdt_size = fdt_totalsize(fdt);
1637 spapr->fdt_initial_size = spapr->fdt_size;
1638 spapr->fdt_blob = fdt;
1640 /* Set up the entry state */
1641 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 0, fdt_addr, 0);
1642 first_ppc_cpu->env.gpr[5] = 0;
1644 spapr->fwnmi_system_reset_addr = -1;
1645 spapr->fwnmi_machine_check_addr = -1;
1646 spapr->fwnmi_machine_check_interlock = -1;
1648 /* Signal all vCPUs waiting on this condition */
1649 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond);
1651 migrate_del_blocker(spapr->fwnmi_migration_blocker);
1654 static void spapr_create_nvram(SpaprMachineState *spapr)
1656 DeviceState *dev = qdev_new("spapr-nvram");
1657 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1659 if (dinfo) {
1660 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo),
1661 &error_fatal);
1664 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal);
1666 spapr->nvram = (struct SpaprNvram *)dev;
1669 static void spapr_rtc_create(SpaprMachineState *spapr)
1671 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc,
1672 sizeof(spapr->rtc), TYPE_SPAPR_RTC,
1673 &error_fatal, NULL);
1674 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal);
1675 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
1676 "date");
1679 /* Returns whether we want to use VGA or not */
1680 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1682 switch (vga_interface_type) {
1683 case VGA_NONE:
1684 return false;
1685 case VGA_DEVICE:
1686 return true;
1687 case VGA_STD:
1688 case VGA_VIRTIO:
1689 case VGA_CIRRUS:
1690 return pci_vga_init(pci_bus) != NULL;
1691 default:
1692 error_setg(errp,
1693 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1694 return false;
1698 static int spapr_pre_load(void *opaque)
1700 int rc;
1702 rc = spapr_caps_pre_load(opaque);
1703 if (rc) {
1704 return rc;
1707 return 0;
1710 static int spapr_post_load(void *opaque, int version_id)
1712 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1713 int err = 0;
1715 err = spapr_caps_post_migration(spapr);
1716 if (err) {
1717 return err;
1721 * In earlier versions, there was no separate qdev for the PAPR
1722 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1723 * So when migrating from those versions, poke the incoming offset
1724 * value into the RTC device
1726 if (version_id < 3) {
1727 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset);
1728 if (err) {
1729 return err;
1733 if (kvm_enabled() && spapr->patb_entry) {
1734 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
1735 bool radix = !!(spapr->patb_entry & PATE1_GR);
1736 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE);
1739 * Update LPCR:HR and UPRT as they may not be set properly in
1740 * the stream
1742 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0,
1743 LPCR_HR | LPCR_UPRT);
1745 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry);
1746 if (err) {
1747 error_report("Process table config unsupported by the host");
1748 return -EINVAL;
1752 err = spapr_irq_post_load(spapr, version_id);
1753 if (err) {
1754 return err;
1757 return err;
1760 static int spapr_pre_save(void *opaque)
1762 int rc;
1764 rc = spapr_caps_pre_save(opaque);
1765 if (rc) {
1766 return rc;
1769 return 0;
1772 static bool version_before_3(void *opaque, int version_id)
1774 return version_id < 3;
1777 static bool spapr_pending_events_needed(void *opaque)
1779 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1780 return !QTAILQ_EMPTY(&spapr->pending_events);
1783 static const VMStateDescription vmstate_spapr_event_entry = {
1784 .name = "spapr_event_log_entry",
1785 .version_id = 1,
1786 .minimum_version_id = 1,
1787 .fields = (VMStateField[]) {
1788 VMSTATE_UINT32(summary, SpaprEventLogEntry),
1789 VMSTATE_UINT32(extended_length, SpaprEventLogEntry),
1790 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0,
1791 NULL, extended_length),
1792 VMSTATE_END_OF_LIST()
1796 static const VMStateDescription vmstate_spapr_pending_events = {
1797 .name = "spapr_pending_events",
1798 .version_id = 1,
1799 .minimum_version_id = 1,
1800 .needed = spapr_pending_events_needed,
1801 .fields = (VMStateField[]) {
1802 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1,
1803 vmstate_spapr_event_entry, SpaprEventLogEntry, next),
1804 VMSTATE_END_OF_LIST()
1808 static bool spapr_ov5_cas_needed(void *opaque)
1810 SpaprMachineState *spapr = opaque;
1811 SpaprOptionVector *ov5_mask = spapr_ovec_new();
1812 bool cas_needed;
1814 /* Prior to the introduction of SpaprOptionVector, we had two option
1815 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1816 * Both of these options encode machine topology into the device-tree
1817 * in such a way that the now-booted OS should still be able to interact
1818 * appropriately with QEMU regardless of what options were actually
1819 * negotiatied on the source side.
1821 * As such, we can avoid migrating the CAS-negotiated options if these
1822 * are the only options available on the current machine/platform.
1823 * Since these are the only options available for pseries-2.7 and
1824 * earlier, this allows us to maintain old->new/new->old migration
1825 * compatibility.
1827 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1828 * via default pseries-2.8 machines and explicit command-line parameters.
1829 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1830 * of the actual CAS-negotiated values to continue working properly. For
1831 * example, availability of memory unplug depends on knowing whether
1832 * OV5_HP_EVT was negotiated via CAS.
1834 * Thus, for any cases where the set of available CAS-negotiatable
1835 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1836 * include the CAS-negotiated options in the migration stream, unless
1837 * if they affect boot time behaviour only.
1839 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1840 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1841 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2);
1843 /* We need extra information if we have any bits outside the mask
1844 * defined above */
1845 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask);
1847 spapr_ovec_cleanup(ov5_mask);
1849 return cas_needed;
1852 static const VMStateDescription vmstate_spapr_ov5_cas = {
1853 .name = "spapr_option_vector_ov5_cas",
1854 .version_id = 1,
1855 .minimum_version_id = 1,
1856 .needed = spapr_ov5_cas_needed,
1857 .fields = (VMStateField[]) {
1858 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1,
1859 vmstate_spapr_ovec, SpaprOptionVector),
1860 VMSTATE_END_OF_LIST()
1864 static bool spapr_patb_entry_needed(void *opaque)
1866 SpaprMachineState *spapr = opaque;
1868 return !!spapr->patb_entry;
1871 static const VMStateDescription vmstate_spapr_patb_entry = {
1872 .name = "spapr_patb_entry",
1873 .version_id = 1,
1874 .minimum_version_id = 1,
1875 .needed = spapr_patb_entry_needed,
1876 .fields = (VMStateField[]) {
1877 VMSTATE_UINT64(patb_entry, SpaprMachineState),
1878 VMSTATE_END_OF_LIST()
1882 static bool spapr_irq_map_needed(void *opaque)
1884 SpaprMachineState *spapr = opaque;
1886 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr);
1889 static const VMStateDescription vmstate_spapr_irq_map = {
1890 .name = "spapr_irq_map",
1891 .version_id = 1,
1892 .minimum_version_id = 1,
1893 .needed = spapr_irq_map_needed,
1894 .fields = (VMStateField[]) {
1895 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr),
1896 VMSTATE_END_OF_LIST()
1900 static bool spapr_dtb_needed(void *opaque)
1902 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque);
1904 return smc->update_dt_enabled;
1907 static int spapr_dtb_pre_load(void *opaque)
1909 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1911 g_free(spapr->fdt_blob);
1912 spapr->fdt_blob = NULL;
1913 spapr->fdt_size = 0;
1915 return 0;
1918 static const VMStateDescription vmstate_spapr_dtb = {
1919 .name = "spapr_dtb",
1920 .version_id = 1,
1921 .minimum_version_id = 1,
1922 .needed = spapr_dtb_needed,
1923 .pre_load = spapr_dtb_pre_load,
1924 .fields = (VMStateField[]) {
1925 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState),
1926 VMSTATE_UINT32(fdt_size, SpaprMachineState),
1927 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL,
1928 fdt_size),
1929 VMSTATE_END_OF_LIST()
1933 static bool spapr_fwnmi_needed(void *opaque)
1935 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1937 return spapr->fwnmi_machine_check_addr != -1;
1940 static int spapr_fwnmi_pre_save(void *opaque)
1942 SpaprMachineState *spapr = (SpaprMachineState *)opaque;
1945 * Check if machine check handling is in progress and print a
1946 * warning message.
1948 if (spapr->fwnmi_machine_check_interlock != -1) {
1949 warn_report("A machine check is being handled during migration. The"
1950 "handler may run and log hardware error on the destination");
1953 return 0;
1956 static const VMStateDescription vmstate_spapr_fwnmi = {
1957 .name = "spapr_fwnmi",
1958 .version_id = 1,
1959 .minimum_version_id = 1,
1960 .needed = spapr_fwnmi_needed,
1961 .pre_save = spapr_fwnmi_pre_save,
1962 .fields = (VMStateField[]) {
1963 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState),
1964 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState),
1965 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState),
1966 VMSTATE_END_OF_LIST()
1970 static const VMStateDescription vmstate_spapr = {
1971 .name = "spapr",
1972 .version_id = 3,
1973 .minimum_version_id = 1,
1974 .pre_load = spapr_pre_load,
1975 .post_load = spapr_post_load,
1976 .pre_save = spapr_pre_save,
1977 .fields = (VMStateField[]) {
1978 /* used to be @next_irq */
1979 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1981 /* RTC offset */
1982 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3),
1984 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2),
1985 VMSTATE_END_OF_LIST()
1987 .subsections = (const VMStateDescription*[]) {
1988 &vmstate_spapr_ov5_cas,
1989 &vmstate_spapr_patb_entry,
1990 &vmstate_spapr_pending_events,
1991 &vmstate_spapr_cap_htm,
1992 &vmstate_spapr_cap_vsx,
1993 &vmstate_spapr_cap_dfp,
1994 &vmstate_spapr_cap_cfpc,
1995 &vmstate_spapr_cap_sbbc,
1996 &vmstate_spapr_cap_ibs,
1997 &vmstate_spapr_cap_hpt_maxpagesize,
1998 &vmstate_spapr_irq_map,
1999 &vmstate_spapr_cap_nested_kvm_hv,
2000 &vmstate_spapr_dtb,
2001 &vmstate_spapr_cap_large_decr,
2002 &vmstate_spapr_cap_ccf_assist,
2003 &vmstate_spapr_cap_fwnmi,
2004 &vmstate_spapr_fwnmi,
2005 NULL
2009 static int htab_save_setup(QEMUFile *f, void *opaque)
2011 SpaprMachineState *spapr = opaque;
2013 /* "Iteration" header */
2014 if (!spapr->htab_shift) {
2015 qemu_put_be32(f, -1);
2016 } else {
2017 qemu_put_be32(f, spapr->htab_shift);
2020 if (spapr->htab) {
2021 spapr->htab_save_index = 0;
2022 spapr->htab_first_pass = true;
2023 } else {
2024 if (spapr->htab_shift) {
2025 assert(kvm_enabled());
2030 return 0;
2033 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr,
2034 int chunkstart, int n_valid, int n_invalid)
2036 qemu_put_be32(f, chunkstart);
2037 qemu_put_be16(f, n_valid);
2038 qemu_put_be16(f, n_invalid);
2039 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
2040 HASH_PTE_SIZE_64 * n_valid);
2043 static void htab_save_end_marker(QEMUFile *f)
2045 qemu_put_be32(f, 0);
2046 qemu_put_be16(f, 0);
2047 qemu_put_be16(f, 0);
2050 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr,
2051 int64_t max_ns)
2053 bool has_timeout = max_ns != -1;
2054 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2055 int index = spapr->htab_save_index;
2056 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2058 assert(spapr->htab_first_pass);
2060 do {
2061 int chunkstart;
2063 /* Consume invalid HPTEs */
2064 while ((index < htabslots)
2065 && !HPTE_VALID(HPTE(spapr->htab, index))) {
2066 CLEAN_HPTE(HPTE(spapr->htab, index));
2067 index++;
2070 /* Consume valid HPTEs */
2071 chunkstart = index;
2072 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2073 && HPTE_VALID(HPTE(spapr->htab, index))) {
2074 CLEAN_HPTE(HPTE(spapr->htab, index));
2075 index++;
2078 if (index > chunkstart) {
2079 int n_valid = index - chunkstart;
2081 htab_save_chunk(f, spapr, chunkstart, n_valid, 0);
2083 if (has_timeout &&
2084 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2085 break;
2088 } while ((index < htabslots) && !qemu_file_rate_limit(f));
2090 if (index >= htabslots) {
2091 assert(index == htabslots);
2092 index = 0;
2093 spapr->htab_first_pass = false;
2095 spapr->htab_save_index = index;
2098 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr,
2099 int64_t max_ns)
2101 bool final = max_ns < 0;
2102 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
2103 int examined = 0, sent = 0;
2104 int index = spapr->htab_save_index;
2105 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2107 assert(!spapr->htab_first_pass);
2109 do {
2110 int chunkstart, invalidstart;
2112 /* Consume non-dirty HPTEs */
2113 while ((index < htabslots)
2114 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
2115 index++;
2116 examined++;
2119 chunkstart = index;
2120 /* Consume valid dirty HPTEs */
2121 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
2122 && HPTE_DIRTY(HPTE(spapr->htab, index))
2123 && HPTE_VALID(HPTE(spapr->htab, index))) {
2124 CLEAN_HPTE(HPTE(spapr->htab, index));
2125 index++;
2126 examined++;
2129 invalidstart = index;
2130 /* Consume invalid dirty HPTEs */
2131 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
2132 && HPTE_DIRTY(HPTE(spapr->htab, index))
2133 && !HPTE_VALID(HPTE(spapr->htab, index))) {
2134 CLEAN_HPTE(HPTE(spapr->htab, index));
2135 index++;
2136 examined++;
2139 if (index > chunkstart) {
2140 int n_valid = invalidstart - chunkstart;
2141 int n_invalid = index - invalidstart;
2143 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid);
2144 sent += index - chunkstart;
2146 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
2147 break;
2151 if (examined >= htabslots) {
2152 break;
2155 if (index >= htabslots) {
2156 assert(index == htabslots);
2157 index = 0;
2159 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
2161 if (index >= htabslots) {
2162 assert(index == htabslots);
2163 index = 0;
2166 spapr->htab_save_index = index;
2168 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
2171 #define MAX_ITERATION_NS 5000000 /* 5 ms */
2172 #define MAX_KVM_BUF_SIZE 2048
2174 static int htab_save_iterate(QEMUFile *f, void *opaque)
2176 SpaprMachineState *spapr = opaque;
2177 int fd;
2178 int rc = 0;
2180 /* Iteration header */
2181 if (!spapr->htab_shift) {
2182 qemu_put_be32(f, -1);
2183 return 1;
2184 } else {
2185 qemu_put_be32(f, 0);
2188 if (!spapr->htab) {
2189 assert(kvm_enabled());
2191 fd = get_htab_fd(spapr);
2192 if (fd < 0) {
2193 return fd;
2196 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
2197 if (rc < 0) {
2198 return rc;
2200 } else if (spapr->htab_first_pass) {
2201 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
2202 } else {
2203 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
2206 htab_save_end_marker(f);
2208 return rc;
2211 static int htab_save_complete(QEMUFile *f, void *opaque)
2213 SpaprMachineState *spapr = opaque;
2214 int fd;
2216 /* Iteration header */
2217 if (!spapr->htab_shift) {
2218 qemu_put_be32(f, -1);
2219 return 0;
2220 } else {
2221 qemu_put_be32(f, 0);
2224 if (!spapr->htab) {
2225 int rc;
2227 assert(kvm_enabled());
2229 fd = get_htab_fd(spapr);
2230 if (fd < 0) {
2231 return fd;
2234 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
2235 if (rc < 0) {
2236 return rc;
2238 } else {
2239 if (spapr->htab_first_pass) {
2240 htab_save_first_pass(f, spapr, -1);
2242 htab_save_later_pass(f, spapr, -1);
2245 /* End marker */
2246 htab_save_end_marker(f);
2248 return 0;
2251 static int htab_load(QEMUFile *f, void *opaque, int version_id)
2253 SpaprMachineState *spapr = opaque;
2254 uint32_t section_hdr;
2255 int fd = -1;
2256 Error *local_err = NULL;
2258 if (version_id < 1 || version_id > 1) {
2259 error_report("htab_load() bad version");
2260 return -EINVAL;
2263 section_hdr = qemu_get_be32(f);
2265 if (section_hdr == -1) {
2266 spapr_free_hpt(spapr);
2267 return 0;
2270 if (section_hdr) {
2271 int ret;
2273 /* First section gives the htab size */
2274 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err);
2275 if (ret < 0) {
2276 error_report_err(local_err);
2277 return ret;
2279 return 0;
2282 if (!spapr->htab) {
2283 assert(kvm_enabled());
2285 fd = kvmppc_get_htab_fd(true, 0, &local_err);
2286 if (fd < 0) {
2287 error_report_err(local_err);
2288 return fd;
2292 while (true) {
2293 uint32_t index;
2294 uint16_t n_valid, n_invalid;
2296 index = qemu_get_be32(f);
2297 n_valid = qemu_get_be16(f);
2298 n_invalid = qemu_get_be16(f);
2300 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
2301 /* End of Stream */
2302 break;
2305 if ((index + n_valid + n_invalid) >
2306 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
2307 /* Bad index in stream */
2308 error_report(
2309 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2310 index, n_valid, n_invalid, spapr->htab_shift);
2311 return -EINVAL;
2314 if (spapr->htab) {
2315 if (n_valid) {
2316 qemu_get_buffer(f, HPTE(spapr->htab, index),
2317 HASH_PTE_SIZE_64 * n_valid);
2319 if (n_invalid) {
2320 memset(HPTE(spapr->htab, index + n_valid), 0,
2321 HASH_PTE_SIZE_64 * n_invalid);
2323 } else {
2324 int rc;
2326 assert(fd >= 0);
2328 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid,
2329 &local_err);
2330 if (rc < 0) {
2331 error_report_err(local_err);
2332 return rc;
2337 if (!spapr->htab) {
2338 assert(fd >= 0);
2339 close(fd);
2342 return 0;
2345 static void htab_save_cleanup(void *opaque)
2347 SpaprMachineState *spapr = opaque;
2349 close_htab_fd(spapr);
2352 static SaveVMHandlers savevm_htab_handlers = {
2353 .save_setup = htab_save_setup,
2354 .save_live_iterate = htab_save_iterate,
2355 .save_live_complete_precopy = htab_save_complete,
2356 .save_cleanup = htab_save_cleanup,
2357 .load_state = htab_load,
2360 static void spapr_boot_set(void *opaque, const char *boot_device,
2361 Error **errp)
2363 MachineState *machine = MACHINE(opaque);
2364 machine->boot_order = g_strdup(boot_device);
2367 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr)
2369 MachineState *machine = MACHINE(spapr);
2370 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
2371 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
2372 int i;
2374 for (i = 0; i < nr_lmbs; i++) {
2375 uint64_t addr;
2377 addr = i * lmb_size + machine->device_memory->base;
2378 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB,
2379 addr / lmb_size);
2384 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2385 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2386 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2388 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
2390 int i;
2392 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2393 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
2394 " is not aligned to %" PRIu64 " MiB",
2395 machine->ram_size,
2396 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2397 return;
2400 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2401 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
2402 " is not aligned to %" PRIu64 " MiB",
2403 machine->ram_size,
2404 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2405 return;
2408 for (i = 0; i < machine->numa_state->num_nodes; i++) {
2409 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
2410 error_setg(errp,
2411 "Node %d memory size 0x%" PRIx64
2412 " is not aligned to %" PRIu64 " MiB",
2413 i, machine->numa_state->nodes[i].node_mem,
2414 SPAPR_MEMORY_BLOCK_SIZE / MiB);
2415 return;
2420 /* find cpu slot in machine->possible_cpus by core_id */
2421 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2423 int index = id / ms->smp.threads;
2425 if (index >= ms->possible_cpus->len) {
2426 return NULL;
2428 if (idx) {
2429 *idx = index;
2431 return &ms->possible_cpus->cpus[index];
2434 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp)
2436 MachineState *ms = MACHINE(spapr);
2437 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
2438 Error *local_err = NULL;
2439 bool vsmt_user = !!spapr->vsmt;
2440 int kvm_smt = kvmppc_smt_threads();
2441 int ret;
2442 unsigned int smp_threads = ms->smp.threads;
2444 if (!kvm_enabled() && (smp_threads > 1)) {
2445 error_setg(errp, "TCG cannot support more than 1 thread/core "
2446 "on a pseries machine");
2447 return;
2449 if (!is_power_of_2(smp_threads)) {
2450 error_setg(errp, "Cannot support %d threads/core on a pseries "
2451 "machine because it must be a power of 2", smp_threads);
2452 return;
2455 /* Detemine the VSMT mode to use: */
2456 if (vsmt_user) {
2457 if (spapr->vsmt < smp_threads) {
2458 error_setg(errp, "Cannot support VSMT mode %d"
2459 " because it must be >= threads/core (%d)",
2460 spapr->vsmt, smp_threads);
2461 return;
2463 /* In this case, spapr->vsmt has been set by the command line */
2464 } else if (!smc->smp_threads_vsmt) {
2466 * Default VSMT value is tricky, because we need it to be as
2467 * consistent as possible (for migration), but this requires
2468 * changing it for at least some existing cases. We pick 8 as
2469 * the value that we'd get with KVM on POWER8, the
2470 * overwhelmingly common case in production systems.
2472 spapr->vsmt = MAX(8, smp_threads);
2473 } else {
2474 spapr->vsmt = smp_threads;
2477 /* KVM: If necessary, set the SMT mode: */
2478 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) {
2479 ret = kvmppc_set_smt_threads(spapr->vsmt);
2480 if (ret) {
2481 /* Looks like KVM isn't able to change VSMT mode */
2482 error_setg(&local_err,
2483 "Failed to set KVM's VSMT mode to %d (errno %d)",
2484 spapr->vsmt, ret);
2485 /* We can live with that if the default one is big enough
2486 * for the number of threads, and a submultiple of the one
2487 * we want. In this case we'll waste some vcpu ids, but
2488 * behaviour will be correct */
2489 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) {
2490 warn_report_err(local_err);
2491 } else {
2492 if (!vsmt_user) {
2493 error_append_hint(&local_err,
2494 "On PPC, a VM with %d threads/core"
2495 " on a host with %d threads/core"
2496 " requires the use of VSMT mode %d.\n",
2497 smp_threads, kvm_smt, spapr->vsmt);
2499 kvmppc_error_append_smt_possible_hint(&local_err);
2500 error_propagate(errp, local_err);
2504 /* else TCG: nothing to do currently */
2507 static void spapr_init_cpus(SpaprMachineState *spapr)
2509 MachineState *machine = MACHINE(spapr);
2510 MachineClass *mc = MACHINE_GET_CLASS(machine);
2511 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2512 const char *type = spapr_get_cpu_core_type(machine->cpu_type);
2513 const CPUArchIdList *possible_cpus;
2514 unsigned int smp_cpus = machine->smp.cpus;
2515 unsigned int smp_threads = machine->smp.threads;
2516 unsigned int max_cpus = machine->smp.max_cpus;
2517 int boot_cores_nr = smp_cpus / smp_threads;
2518 int i;
2520 possible_cpus = mc->possible_cpu_arch_ids(machine);
2521 if (mc->has_hotpluggable_cpus) {
2522 if (smp_cpus % smp_threads) {
2523 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2524 smp_cpus, smp_threads);
2525 exit(1);
2527 if (max_cpus % smp_threads) {
2528 error_report("max_cpus (%u) must be multiple of threads (%u)",
2529 max_cpus, smp_threads);
2530 exit(1);
2532 } else {
2533 if (max_cpus != smp_cpus) {
2534 error_report("This machine version does not support CPU hotplug");
2535 exit(1);
2537 boot_cores_nr = possible_cpus->len;
2540 if (smc->pre_2_10_has_unused_icps) {
2541 int i;
2543 for (i = 0; i < spapr_max_server_number(spapr); i++) {
2544 /* Dummy entries get deregistered when real ICPState objects
2545 * are registered during CPU core hotplug.
2547 pre_2_10_vmstate_register_dummy_icp(i);
2551 for (i = 0; i < possible_cpus->len; i++) {
2552 int core_id = i * smp_threads;
2554 if (mc->has_hotpluggable_cpus) {
2555 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU,
2556 spapr_vcpu_id(spapr, core_id));
2559 if (i < boot_cores_nr) {
2560 Object *core = object_new(type);
2561 int nr_threads = smp_threads;
2563 /* Handle the partially filled core for older machine types */
2564 if ((i + 1) * smp_threads >= smp_cpus) {
2565 nr_threads = smp_cpus - i * smp_threads;
2568 object_property_set_int(core, "nr-threads", nr_threads,
2569 &error_fatal);
2570 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id,
2571 &error_fatal);
2572 qdev_realize(DEVICE(core), NULL, &error_fatal);
2574 object_unref(core);
2579 static PCIHostState *spapr_create_default_phb(void)
2581 DeviceState *dev;
2583 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE);
2584 qdev_prop_set_uint32(dev, "index", 0);
2585 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
2587 return PCI_HOST_BRIDGE(dev);
2590 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp)
2592 MachineState *machine = MACHINE(spapr);
2593 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
2594 hwaddr rma_size = machine->ram_size;
2595 hwaddr node0_size = spapr_node0_size(machine);
2597 /* RMA has to fit in the first NUMA node */
2598 rma_size = MIN(rma_size, node0_size);
2601 * VRMA access is via a special 1TiB SLB mapping, so the RMA can
2602 * never exceed that
2604 rma_size = MIN(rma_size, 1 * TiB);
2607 * Clamp the RMA size based on machine type. This is for
2608 * migration compatibility with older qemu versions, which limited
2609 * the RMA size for complicated and mostly bad reasons.
2611 if (smc->rma_limit) {
2612 rma_size = MIN(rma_size, smc->rma_limit);
2615 if (rma_size < MIN_RMA_SLOF) {
2616 error_setg(errp,
2617 "pSeries SLOF firmware requires >= %" HWADDR_PRIx
2618 "ldMiB guest RMA (Real Mode Area memory)",
2619 MIN_RMA_SLOF / MiB);
2620 return 0;
2623 return rma_size;
2626 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr)
2628 MachineState *machine = MACHINE(spapr);
2629 int i;
2631 for (i = 0; i < machine->ram_slots; i++) {
2632 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i);
2636 /* pSeries LPAR / sPAPR hardware init */
2637 static void spapr_machine_init(MachineState *machine)
2639 SpaprMachineState *spapr = SPAPR_MACHINE(machine);
2640 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2641 MachineClass *mc = MACHINE_GET_CLASS(machine);
2642 const char *bios_name = machine->firmware ?: FW_FILE_NAME;
2643 const char *kernel_filename = machine->kernel_filename;
2644 const char *initrd_filename = machine->initrd_filename;
2645 PCIHostState *phb;
2646 int i;
2647 MemoryRegion *sysmem = get_system_memory();
2648 long load_limit, fw_size;
2649 char *filename;
2650 Error *resize_hpt_err = NULL;
2653 * if Secure VM (PEF) support is configured, then initialize it
2655 pef_kvm_init(machine->cgs, &error_fatal);
2657 msi_nonbroken = true;
2659 QLIST_INIT(&spapr->phbs);
2660 QTAILQ_INIT(&spapr->pending_dimm_unplugs);
2662 /* Determine capabilities to run with */
2663 spapr_caps_init(spapr);
2665 kvmppc_check_papr_resize_hpt(&resize_hpt_err);
2666 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) {
2668 * If the user explicitly requested a mode we should either
2669 * supply it, or fail completely (which we do below). But if
2670 * it's not set explicitly, we reset our mode to something
2671 * that works
2673 if (resize_hpt_err) {
2674 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2675 error_free(resize_hpt_err);
2676 resize_hpt_err = NULL;
2677 } else {
2678 spapr->resize_hpt = smc->resize_hpt_default;
2682 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT);
2684 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) {
2686 * User requested HPT resize, but this host can't supply it. Bail out
2688 error_report_err(resize_hpt_err);
2689 exit(1);
2691 error_free(resize_hpt_err);
2693 spapr->rma_size = spapr_rma_size(spapr, &error_fatal);
2695 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2696 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2699 * VSMT must be set in order to be able to compute VCPU ids, ie to
2700 * call spapr_max_server_number() or spapr_vcpu_id().
2702 spapr_set_vsmt_mode(spapr, &error_fatal);
2704 /* Set up Interrupt Controller before we create the VCPUs */
2705 spapr_irq_init(spapr, &error_fatal);
2707 /* Set up containers for ibm,client-architecture-support negotiated options
2709 spapr->ov5 = spapr_ovec_new();
2710 spapr->ov5_cas = spapr_ovec_new();
2712 if (smc->dr_lmb_enabled) {
2713 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2714 spapr_validate_node_memory(machine, &error_fatal);
2717 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2719 /* advertise support for dedicated HP event source to guests */
2720 if (spapr->use_hotplug_event_source) {
2721 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2724 /* advertise support for HPT resizing */
2725 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
2726 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE);
2729 /* advertise support for ibm,dyamic-memory-v2 */
2730 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2);
2732 /* advertise XIVE on POWER9 machines */
2733 if (spapr->irq->xive) {
2734 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT);
2737 /* init CPUs */
2738 spapr_init_cpus(spapr);
2741 * check we don't have a memory-less/cpu-less NUMA node
2742 * Firmware relies on the existing memory/cpu topology to provide the
2743 * NUMA topology to the kernel.
2744 * And the linux kernel needs to know the NUMA topology at start
2745 * to be able to hotplug CPUs later.
2747 if (machine->numa_state->num_nodes) {
2748 for (i = 0; i < machine->numa_state->num_nodes; ++i) {
2749 /* check for memory-less node */
2750 if (machine->numa_state->nodes[i].node_mem == 0) {
2751 CPUState *cs;
2752 int found = 0;
2753 /* check for cpu-less node */
2754 CPU_FOREACH(cs) {
2755 PowerPCCPU *cpu = POWERPC_CPU(cs);
2756 if (cpu->node_id == i) {
2757 found = 1;
2758 break;
2761 /* memory-less and cpu-less node */
2762 if (!found) {
2763 error_report(
2764 "Memory-less/cpu-less nodes are not supported (node %d)",
2766 exit(1);
2773 spapr->gpu_numa_id = spapr_numa_initial_nvgpu_numa_id(machine);
2775 /* Init numa_assoc_array */
2776 spapr_numa_associativity_init(spapr, machine);
2778 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2779 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0,
2780 spapr->max_compat_pvr)) {
2781 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300);
2782 /* KVM and TCG always allow GTSE with radix... */
2783 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
2785 /* ... but not with hash (currently). */
2787 if (kvm_enabled()) {
2788 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2789 kvmppc_enable_logical_ci_hcalls();
2790 kvmppc_enable_set_mode_hcall();
2792 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2793 kvmppc_enable_clear_ref_mod_hcalls();
2795 /* Enable H_PAGE_INIT */
2796 kvmppc_enable_h_page_init();
2799 /* map RAM */
2800 memory_region_add_subregion(sysmem, 0, machine->ram);
2802 /* always allocate the device memory information */
2803 machine->device_memory = g_malloc0(sizeof(*machine->device_memory));
2805 /* initialize hotplug memory address space */
2806 if (machine->ram_size < machine->maxram_size) {
2807 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size;
2809 * Limit the number of hotpluggable memory slots to half the number
2810 * slots that KVM supports, leaving the other half for PCI and other
2811 * devices. However ensure that number of slots doesn't drop below 32.
2813 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2814 SPAPR_MAX_RAM_SLOTS;
2816 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2817 max_memslots = SPAPR_MAX_RAM_SLOTS;
2819 if (machine->ram_slots > max_memslots) {
2820 error_report("Specified number of memory slots %"
2821 PRIu64" exceeds max supported %d",
2822 machine->ram_slots, max_memslots);
2823 exit(1);
2826 machine->device_memory->base = ROUND_UP(machine->ram_size,
2827 SPAPR_DEVICE_MEM_ALIGN);
2828 memory_region_init(&machine->device_memory->mr, OBJECT(spapr),
2829 "device-memory", device_mem_size);
2830 memory_region_add_subregion(sysmem, machine->device_memory->base,
2831 &machine->device_memory->mr);
2834 if (smc->dr_lmb_enabled) {
2835 spapr_create_lmb_dr_connectors(spapr);
2838 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) {
2839 /* Create the error string for live migration blocker */
2840 error_setg(&spapr->fwnmi_migration_blocker,
2841 "A machine check is being handled during migration. The handler"
2842 "may run and log hardware error on the destination");
2845 if (mc->nvdimm_supported) {
2846 spapr_create_nvdimm_dr_connectors(spapr);
2849 /* Set up RTAS event infrastructure */
2850 spapr_events_init(spapr);
2852 /* Set up the RTC RTAS interfaces */
2853 spapr_rtc_create(spapr);
2855 /* Set up VIO bus */
2856 spapr->vio_bus = spapr_vio_bus_init();
2858 for (i = 0; serial_hd(i); i++) {
2859 spapr_vty_create(spapr->vio_bus, serial_hd(i));
2862 /* We always have at least the nvram device on VIO */
2863 spapr_create_nvram(spapr);
2866 * Setup hotplug / dynamic-reconfiguration connectors. top-level
2867 * connectors (described in root DT node's "ibm,drc-types" property)
2868 * are pre-initialized here. additional child connectors (such as
2869 * connectors for a PHBs PCI slots) are added as needed during their
2870 * parent's realization.
2872 if (smc->dr_phb_enabled) {
2873 for (i = 0; i < SPAPR_MAX_PHBS; i++) {
2874 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i);
2878 /* Set up PCI */
2879 spapr_pci_rtas_init();
2881 phb = spapr_create_default_phb();
2883 for (i = 0; i < nb_nics; i++) {
2884 NICInfo *nd = &nd_table[i];
2886 if (!nd->model) {
2887 nd->model = g_strdup("spapr-vlan");
2890 if (g_str_equal(nd->model, "spapr-vlan") ||
2891 g_str_equal(nd->model, "ibmveth")) {
2892 spapr_vlan_create(spapr->vio_bus, nd);
2893 } else {
2894 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2898 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2899 spapr_vscsi_create(spapr->vio_bus);
2902 /* Graphics */
2903 if (spapr_vga_init(phb->bus, &error_fatal)) {
2904 spapr->has_graphics = true;
2905 machine->usb |= defaults_enabled() && !machine->usb_disabled;
2908 if (machine->usb) {
2909 if (smc->use_ohci_by_default) {
2910 pci_create_simple(phb->bus, -1, "pci-ohci");
2911 } else {
2912 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2915 if (spapr->has_graphics) {
2916 USBBus *usb_bus = usb_bus_find(-1);
2918 usb_create_simple(usb_bus, "usb-kbd");
2919 usb_create_simple(usb_bus, "usb-mouse");
2923 if (kernel_filename) {
2924 spapr->kernel_size = load_elf(kernel_filename, NULL,
2925 translate_kernel_address, spapr,
2926 NULL, NULL, NULL, NULL, 1,
2927 PPC_ELF_MACHINE, 0, 0);
2928 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2929 spapr->kernel_size = load_elf(kernel_filename, NULL,
2930 translate_kernel_address, spapr,
2931 NULL, NULL, NULL, NULL, 0,
2932 PPC_ELF_MACHINE, 0, 0);
2933 spapr->kernel_le = spapr->kernel_size > 0;
2935 if (spapr->kernel_size < 0) {
2936 error_report("error loading %s: %s", kernel_filename,
2937 load_elf_strerror(spapr->kernel_size));
2938 exit(1);
2941 /* load initrd */
2942 if (initrd_filename) {
2943 /* Try to locate the initrd in the gap between the kernel
2944 * and the firmware. Add a bit of space just in case
2946 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size
2947 + 0x1ffff) & ~0xffff;
2948 spapr->initrd_size = load_image_targphys(initrd_filename,
2949 spapr->initrd_base,
2950 load_limit
2951 - spapr->initrd_base);
2952 if (spapr->initrd_size < 0) {
2953 error_report("could not load initial ram disk '%s'",
2954 initrd_filename);
2955 exit(1);
2960 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2961 if (!filename) {
2962 error_report("Could not find LPAR firmware '%s'", bios_name);
2963 exit(1);
2965 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2966 if (fw_size <= 0) {
2967 error_report("Could not load LPAR firmware '%s'", filename);
2968 exit(1);
2970 g_free(filename);
2972 /* FIXME: Should register things through the MachineState's qdev
2973 * interface, this is a legacy from the sPAPREnvironment structure
2974 * which predated MachineState but had a similar function */
2975 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2976 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1,
2977 &savevm_htab_handlers, spapr);
2979 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine));
2981 qemu_register_boot_set(spapr_boot_set, spapr);
2984 * Nothing needs to be done to resume a suspended guest because
2985 * suspending does not change the machine state, so no need for
2986 * a ->wakeup method.
2988 qemu_register_wakeup_support();
2990 if (kvm_enabled()) {
2991 /* to stop and start vmclock */
2992 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
2993 &spapr->tb);
2995 kvmppc_spapr_enable_inkernel_multitce();
2998 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond);
3001 #define DEFAULT_KVM_TYPE "auto"
3002 static int spapr_kvm_type(MachineState *machine, const char *vm_type)
3005 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to
3006 * accomodate the 'HV' and 'PV' formats that exists in the
3007 * wild. The 'auto' mode is being introduced already as
3008 * lower-case, thus we don't need to bother checking for
3009 * "AUTO".
3011 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) {
3012 return 0;
3015 if (!g_ascii_strcasecmp(vm_type, "hv")) {
3016 return 1;
3019 if (!g_ascii_strcasecmp(vm_type, "pr")) {
3020 return 2;
3023 error_report("Unknown kvm-type specified '%s'", vm_type);
3024 exit(1);
3028 * Implementation of an interface to adjust firmware path
3029 * for the bootindex property handling.
3031 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
3032 DeviceState *dev)
3034 #define CAST(type, obj, name) \
3035 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
3036 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
3037 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
3038 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON);
3039 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE);
3041 if (d) {
3042 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
3043 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
3044 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
3046 if (spapr) {
3048 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
3049 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form
3050 * 0x8000 | (target << 8) | (bus << 5) | lun
3051 * (see the "Logical unit addressing format" table in SAM5)
3053 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun;
3054 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3055 (uint64_t)id << 48);
3056 } else if (virtio) {
3058 * We use SRP luns of the form 01000000 | (target << 8) | lun
3059 * in the top 32 bits of the 64-bit LUN
3060 * Note: the quote above is from SLOF and it is wrong,
3061 * the actual binding is:
3062 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
3064 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
3065 if (d->lun >= 256) {
3066 /* Use the LUN "flat space addressing method" */
3067 id |= 0x4000;
3069 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3070 (uint64_t)id << 32);
3071 } else if (usb) {
3073 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
3074 * in the top 32 bits of the 64-bit LUN
3076 unsigned usb_port = atoi(usb->port->path);
3077 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
3078 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
3079 (uint64_t)id << 32);
3084 * SLOF probes the USB devices, and if it recognizes that the device is a
3085 * storage device, it changes its name to "storage" instead of "usb-host",
3086 * and additionally adds a child node for the SCSI LUN, so the correct
3087 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
3089 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
3090 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
3091 if (usb_host_dev_is_scsi_storage(usbdev)) {
3092 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
3096 if (phb) {
3097 /* Replace "pci" with "pci@800000020000000" */
3098 return g_strdup_printf("pci@%"PRIX64, phb->buid);
3101 if (vsc) {
3102 /* Same logic as virtio above */
3103 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun;
3104 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32);
3107 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) {
3108 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
3109 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE);
3110 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn));
3113 if (pcidev) {
3114 return spapr_pci_fw_dev_name(pcidev);
3117 return NULL;
3120 static char *spapr_get_kvm_type(Object *obj, Error **errp)
3122 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3124 return g_strdup(spapr->kvm_type);
3127 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
3129 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3131 g_free(spapr->kvm_type);
3132 spapr->kvm_type = g_strdup(value);
3135 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
3137 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3139 return spapr->use_hotplug_event_source;
3142 static void spapr_set_modern_hotplug_events(Object *obj, bool value,
3143 Error **errp)
3145 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3147 spapr->use_hotplug_event_source = value;
3150 static bool spapr_get_msix_emulation(Object *obj, Error **errp)
3152 return true;
3155 static char *spapr_get_resize_hpt(Object *obj, Error **errp)
3157 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3159 switch (spapr->resize_hpt) {
3160 case SPAPR_RESIZE_HPT_DEFAULT:
3161 return g_strdup("default");
3162 case SPAPR_RESIZE_HPT_DISABLED:
3163 return g_strdup("disabled");
3164 case SPAPR_RESIZE_HPT_ENABLED:
3165 return g_strdup("enabled");
3166 case SPAPR_RESIZE_HPT_REQUIRED:
3167 return g_strdup("required");
3169 g_assert_not_reached();
3172 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp)
3174 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3176 if (strcmp(value, "default") == 0) {
3177 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT;
3178 } else if (strcmp(value, "disabled") == 0) {
3179 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
3180 } else if (strcmp(value, "enabled") == 0) {
3181 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED;
3182 } else if (strcmp(value, "required") == 0) {
3183 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED;
3184 } else {
3185 error_setg(errp, "Bad value for \"resize-hpt\" property");
3189 static char *spapr_get_ic_mode(Object *obj, Error **errp)
3191 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3193 if (spapr->irq == &spapr_irq_xics_legacy) {
3194 return g_strdup("legacy");
3195 } else if (spapr->irq == &spapr_irq_xics) {
3196 return g_strdup("xics");
3197 } else if (spapr->irq == &spapr_irq_xive) {
3198 return g_strdup("xive");
3199 } else if (spapr->irq == &spapr_irq_dual) {
3200 return g_strdup("dual");
3202 g_assert_not_reached();
3205 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp)
3207 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3209 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
3210 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode");
3211 return;
3214 /* The legacy IRQ backend can not be set */
3215 if (strcmp(value, "xics") == 0) {
3216 spapr->irq = &spapr_irq_xics;
3217 } else if (strcmp(value, "xive") == 0) {
3218 spapr->irq = &spapr_irq_xive;
3219 } else if (strcmp(value, "dual") == 0) {
3220 spapr->irq = &spapr_irq_dual;
3221 } else {
3222 error_setg(errp, "Bad value for \"ic-mode\" property");
3226 static char *spapr_get_host_model(Object *obj, Error **errp)
3228 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3230 return g_strdup(spapr->host_model);
3233 static void spapr_set_host_model(Object *obj, const char *value, Error **errp)
3235 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3237 g_free(spapr->host_model);
3238 spapr->host_model = g_strdup(value);
3241 static char *spapr_get_host_serial(Object *obj, Error **errp)
3243 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3245 return g_strdup(spapr->host_serial);
3248 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp)
3250 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3252 g_free(spapr->host_serial);
3253 spapr->host_serial = g_strdup(value);
3256 static void spapr_instance_init(Object *obj)
3258 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3259 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
3260 MachineState *ms = MACHINE(spapr);
3261 MachineClass *mc = MACHINE_GET_CLASS(ms);
3264 * NVDIMM support went live in 5.1 without considering that, in
3265 * other archs, the user needs to enable NVDIMM support with the
3266 * 'nvdimm' machine option and the default behavior is NVDIMM
3267 * support disabled. It is too late to roll back to the standard
3268 * behavior without breaking 5.1 guests.
3270 if (mc->nvdimm_supported) {
3271 ms->nvdimms_state->is_enabled = true;
3274 spapr->htab_fd = -1;
3275 spapr->use_hotplug_event_source = true;
3276 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE);
3277 object_property_add_str(obj, "kvm-type",
3278 spapr_get_kvm_type, spapr_set_kvm_type);
3279 object_property_set_description(obj, "kvm-type",
3280 "Specifies the KVM virtualization mode (auto,"
3281 " hv, pr). Defaults to 'auto'. This mode will use"
3282 " any available KVM module loaded in the host,"
3283 " where kvm_hv takes precedence if both kvm_hv and"
3284 " kvm_pr are loaded.");
3285 object_property_add_bool(obj, "modern-hotplug-events",
3286 spapr_get_modern_hotplug_events,
3287 spapr_set_modern_hotplug_events);
3288 object_property_set_description(obj, "modern-hotplug-events",
3289 "Use dedicated hotplug event mechanism in"
3290 " place of standard EPOW events when possible"
3291 " (required for memory hot-unplug support)");
3292 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr,
3293 "Maximum permitted CPU compatibility mode");
3295 object_property_add_str(obj, "resize-hpt",
3296 spapr_get_resize_hpt, spapr_set_resize_hpt);
3297 object_property_set_description(obj, "resize-hpt",
3298 "Resizing of the Hash Page Table (enabled, disabled, required)");
3299 object_property_add_uint32_ptr(obj, "vsmt",
3300 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE);
3301 object_property_set_description(obj, "vsmt",
3302 "Virtual SMT: KVM behaves as if this were"
3303 " the host's SMT mode");
3305 object_property_add_bool(obj, "vfio-no-msix-emulation",
3306 spapr_get_msix_emulation, NULL);
3308 object_property_add_uint64_ptr(obj, "kernel-addr",
3309 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE);
3310 object_property_set_description(obj, "kernel-addr",
3311 stringify(KERNEL_LOAD_ADDR)
3312 " for -kernel is the default");
3313 spapr->kernel_addr = KERNEL_LOAD_ADDR;
3314 /* The machine class defines the default interrupt controller mode */
3315 spapr->irq = smc->irq;
3316 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode,
3317 spapr_set_ic_mode);
3318 object_property_set_description(obj, "ic-mode",
3319 "Specifies the interrupt controller mode (xics, xive, dual)");
3321 object_property_add_str(obj, "host-model",
3322 spapr_get_host_model, spapr_set_host_model);
3323 object_property_set_description(obj, "host-model",
3324 "Host model to advertise in guest device tree");
3325 object_property_add_str(obj, "host-serial",
3326 spapr_get_host_serial, spapr_set_host_serial);
3327 object_property_set_description(obj, "host-serial",
3328 "Host serial number to advertise in guest device tree");
3331 static void spapr_machine_finalizefn(Object *obj)
3333 SpaprMachineState *spapr = SPAPR_MACHINE(obj);
3335 g_free(spapr->kvm_type);
3338 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
3340 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
3341 PowerPCCPU *cpu = POWERPC_CPU(cs);
3342 CPUPPCState *env = &cpu->env;
3344 cpu_synchronize_state(cs);
3345 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */
3346 if (spapr->fwnmi_system_reset_addr != -1) {
3347 uint64_t rtas_addr, addr;
3349 /* get rtas addr from fdt */
3350 rtas_addr = spapr_get_rtas_addr();
3351 if (!rtas_addr) {
3352 qemu_system_guest_panicked(NULL);
3353 return;
3356 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2;
3357 stq_be_phys(&address_space_memory, addr, env->gpr[3]);
3358 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0);
3359 env->gpr[3] = addr;
3361 ppc_cpu_do_system_reset(cs);
3362 if (spapr->fwnmi_system_reset_addr != -1) {
3363 env->nip = spapr->fwnmi_system_reset_addr;
3367 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
3369 CPUState *cs;
3371 CPU_FOREACH(cs) {
3372 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
3376 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
3377 void *fdt, int *fdt_start_offset, Error **errp)
3379 uint64_t addr;
3380 uint32_t node;
3382 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE;
3383 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP,
3384 &error_abort);
3385 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr,
3386 SPAPR_MEMORY_BLOCK_SIZE);
3387 return 0;
3390 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
3391 bool dedicated_hp_event_source)
3393 SpaprDrc *drc;
3394 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
3395 int i;
3396 uint64_t addr = addr_start;
3397 bool hotplugged = spapr_drc_hotplugged(dev);
3399 for (i = 0; i < nr_lmbs; i++) {
3400 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3401 addr / SPAPR_MEMORY_BLOCK_SIZE);
3402 g_assert(drc);
3405 * memory_device_get_free_addr() provided a range of free addresses
3406 * that doesn't overlap with any existing mapping at pre-plug. The
3407 * corresponding LMB DRCs are thus assumed to be all attachable.
3409 spapr_drc_attach(drc, dev);
3410 if (!hotplugged) {
3411 spapr_drc_reset(drc);
3413 addr += SPAPR_MEMORY_BLOCK_SIZE;
3415 /* send hotplug notification to the
3416 * guest only in case of hotplugged memory
3418 if (hotplugged) {
3419 if (dedicated_hp_event_source) {
3420 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3421 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3422 g_assert(drc);
3423 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3424 nr_lmbs,
3425 spapr_drc_index(drc));
3426 } else {
3427 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
3428 nr_lmbs);
3433 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev)
3435 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev);
3436 PCDIMMDevice *dimm = PC_DIMM(dev);
3437 uint64_t size, addr;
3438 int64_t slot;
3439 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
3441 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort);
3443 pc_dimm_plug(dimm, MACHINE(ms));
3445 if (!is_nvdimm) {
3446 addr = object_property_get_uint(OBJECT(dimm),
3447 PC_DIMM_ADDR_PROP, &error_abort);
3448 spapr_add_lmbs(dev, addr, size,
3449 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT));
3450 } else {
3451 slot = object_property_get_int(OBJECT(dimm),
3452 PC_DIMM_SLOT_PROP, &error_abort);
3453 /* We should have valid slot number at this point */
3454 g_assert(slot >= 0);
3455 spapr_add_nvdimm(dev, slot);
3459 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3460 Error **errp)
3462 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev);
3463 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3464 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
3465 PCDIMMDevice *dimm = PC_DIMM(dev);
3466 Error *local_err = NULL;
3467 uint64_t size;
3468 Object *memdev;
3469 hwaddr pagesize;
3471 if (!smc->dr_lmb_enabled) {
3472 error_setg(errp, "Memory hotplug not supported for this machine");
3473 return;
3476 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err);
3477 if (local_err) {
3478 error_propagate(errp, local_err);
3479 return;
3482 if (is_nvdimm) {
3483 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) {
3484 return;
3486 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) {
3487 error_setg(errp, "Hotplugged memory size must be a multiple of "
3488 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB);
3489 return;
3492 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP,
3493 &error_abort);
3494 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev));
3495 if (!spapr_check_pagesize(spapr, pagesize, errp)) {
3496 return;
3499 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp);
3502 struct SpaprDimmState {
3503 PCDIMMDevice *dimm;
3504 uint32_t nr_lmbs;
3505 QTAILQ_ENTRY(SpaprDimmState) next;
3508 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s,
3509 PCDIMMDevice *dimm)
3511 SpaprDimmState *dimm_state = NULL;
3513 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) {
3514 if (dimm_state->dimm == dimm) {
3515 break;
3518 return dimm_state;
3521 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr,
3522 uint32_t nr_lmbs,
3523 PCDIMMDevice *dimm)
3525 SpaprDimmState *ds = NULL;
3528 * If this request is for a DIMM whose removal had failed earlier
3529 * (due to guest's refusal to remove the LMBs), we would have this
3530 * dimm already in the pending_dimm_unplugs list. In that
3531 * case don't add again.
3533 ds = spapr_pending_dimm_unplugs_find(spapr, dimm);
3534 if (!ds) {
3535 ds = g_malloc0(sizeof(SpaprDimmState));
3536 ds->nr_lmbs = nr_lmbs;
3537 ds->dimm = dimm;
3538 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next);
3540 return ds;
3543 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr,
3544 SpaprDimmState *dimm_state)
3546 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next);
3547 g_free(dimm_state);
3550 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms,
3551 PCDIMMDevice *dimm)
3553 SpaprDrc *drc;
3554 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm),
3555 &error_abort);
3556 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3557 uint32_t avail_lmbs = 0;
3558 uint64_t addr_start, addr;
3559 int i;
3561 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3562 &error_abort);
3564 addr = addr_start;
3565 for (i = 0; i < nr_lmbs; i++) {
3566 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3567 addr / SPAPR_MEMORY_BLOCK_SIZE);
3568 g_assert(drc);
3569 if (drc->dev) {
3570 avail_lmbs++;
3572 addr += SPAPR_MEMORY_BLOCK_SIZE;
3575 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm);
3578 /* Callback to be called during DRC release. */
3579 void spapr_lmb_release(DeviceState *dev)
3581 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
3582 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl);
3583 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3585 /* This information will get lost if a migration occurs
3586 * during the unplug process. In this case recover it. */
3587 if (ds == NULL) {
3588 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev));
3589 g_assert(ds);
3590 /* The DRC being examined by the caller at least must be counted */
3591 g_assert(ds->nr_lmbs);
3594 if (--ds->nr_lmbs) {
3595 return;
3599 * Now that all the LMBs have been removed by the guest, call the
3600 * unplug handler chain. This can never fail.
3602 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
3603 object_unparent(OBJECT(dev));
3606 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
3608 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3609 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3611 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev));
3612 qdev_unrealize(dev);
3613 spapr_pending_dimm_unplugs_remove(spapr, ds);
3616 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
3617 DeviceState *dev, Error **errp)
3619 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3620 PCDIMMDevice *dimm = PC_DIMM(dev);
3621 uint32_t nr_lmbs;
3622 uint64_t size, addr_start, addr;
3623 int i;
3624 SpaprDrc *drc;
3626 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
3627 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
3628 return;
3631 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort);
3632 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3634 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3635 &error_abort);
3638 * An existing pending dimm state for this DIMM means that there is an
3639 * unplug operation in progress, waiting for the spapr_lmb_release
3640 * callback to complete the job (BQL can't cover that far). In this case,
3641 * bail out to avoid detaching DRCs that were already released.
3643 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) {
3644 error_setg(errp, "Memory unplug already in progress for device %s",
3645 dev->id);
3646 return;
3649 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm);
3651 addr = addr_start;
3652 for (i = 0; i < nr_lmbs; i++) {
3653 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3654 addr / SPAPR_MEMORY_BLOCK_SIZE);
3655 g_assert(drc);
3657 spapr_drc_detach(drc);
3658 addr += SPAPR_MEMORY_BLOCK_SIZE;
3661 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3662 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3663 g_assert(drc);
3664 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3665 nr_lmbs, spapr_drc_index(drc));
3668 /* Callback to be called during DRC release. */
3669 void spapr_core_release(DeviceState *dev)
3671 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev);
3673 /* Call the unplug handler chain. This can never fail. */
3674 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort);
3675 object_unparent(OBJECT(dev));
3678 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev)
3680 MachineState *ms = MACHINE(hotplug_dev);
3681 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
3682 CPUCore *cc = CPU_CORE(dev);
3683 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
3685 if (smc->pre_2_10_has_unused_icps) {
3686 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
3687 int i;
3689 for (i = 0; i < cc->nr_threads; i++) {
3690 CPUState *cs = CPU(sc->threads[i]);
3692 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index);
3696 assert(core_slot);
3697 core_slot->cpu = NULL;
3698 qdev_unrealize(dev);
3701 static
3702 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
3703 Error **errp)
3705 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3706 int index;
3707 SpaprDrc *drc;
3708 CPUCore *cc = CPU_CORE(dev);
3710 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
3711 error_setg(errp, "Unable to find CPU core with core-id: %d",
3712 cc->core_id);
3713 return;
3715 if (index == 0) {
3716 error_setg(errp, "Boot CPU core may not be unplugged");
3717 return;
3720 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3721 spapr_vcpu_id(spapr, cc->core_id));
3722 g_assert(drc);
3724 if (!spapr_drc_unplug_requested(drc)) {
3725 spapr_drc_detach(drc);
3726 spapr_hotplug_req_remove_by_index(drc);
3730 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
3731 void *fdt, int *fdt_start_offset, Error **errp)
3733 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev);
3734 CPUState *cs = CPU(core->threads[0]);
3735 PowerPCCPU *cpu = POWERPC_CPU(cs);
3736 DeviceClass *dc = DEVICE_GET_CLASS(cs);
3737 int id = spapr_get_vcpu_id(cpu);
3738 g_autofree char *nodename = NULL;
3739 int offset;
3741 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
3742 offset = fdt_add_subnode(fdt, 0, nodename);
3744 spapr_dt_cpu(cs, fdt, offset, spapr);
3747 * spapr_dt_cpu() does not fill the 'name' property in the
3748 * CPU node. The function is called during boot process, before
3749 * and after CAS, and overwriting the 'name' property written
3750 * by SLOF is not allowed.
3752 * Write it manually after spapr_dt_cpu(). This makes the hotplug
3753 * CPUs more compatible with the coldplugged ones, which have
3754 * the 'name' property. Linux Kernel also relies on this
3755 * property to identify CPU nodes.
3757 _FDT((fdt_setprop_string(fdt, offset, "name", nodename)));
3759 *fdt_start_offset = offset;
3760 return 0;
3763 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev)
3765 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3766 MachineClass *mc = MACHINE_GET_CLASS(spapr);
3767 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3768 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev));
3769 CPUCore *cc = CPU_CORE(dev);
3770 CPUState *cs;
3771 SpaprDrc *drc;
3772 CPUArchId *core_slot;
3773 int index;
3774 bool hotplugged = spapr_drc_hotplugged(dev);
3775 int i;
3777 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3778 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */
3780 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3781 spapr_vcpu_id(spapr, cc->core_id));
3783 g_assert(drc || !mc->has_hotpluggable_cpus);
3785 if (drc) {
3787 * spapr_core_pre_plug() already buys us this is a brand new
3788 * core being plugged into a free slot. Nothing should already
3789 * be attached to the corresponding DRC.
3791 spapr_drc_attach(drc, dev);
3793 if (hotplugged) {
3795 * Send hotplug notification interrupt to the guest only
3796 * in case of hotplugged CPUs.
3798 spapr_hotplug_req_add_by_index(drc);
3799 } else {
3800 spapr_drc_reset(drc);
3804 core_slot->cpu = OBJECT(dev);
3807 * Set compatibility mode to match the boot CPU, which was either set
3808 * by the machine reset code or by CAS. This really shouldn't fail at
3809 * this point.
3811 if (hotplugged) {
3812 for (i = 0; i < cc->nr_threads; i++) {
3813 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr,
3814 &error_abort);
3818 if (smc->pre_2_10_has_unused_icps) {
3819 for (i = 0; i < cc->nr_threads; i++) {
3820 cs = CPU(core->threads[i]);
3821 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index);
3826 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3827 Error **errp)
3829 MachineState *machine = MACHINE(OBJECT(hotplug_dev));
3830 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
3831 CPUCore *cc = CPU_CORE(dev);
3832 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type);
3833 const char *type = object_get_typename(OBJECT(dev));
3834 CPUArchId *core_slot;
3835 int index;
3836 unsigned int smp_threads = machine->smp.threads;
3838 if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
3839 error_setg(errp, "CPU hotplug not supported for this machine");
3840 return;
3843 if (strcmp(base_core_type, type)) {
3844 error_setg(errp, "CPU core type should be %s", base_core_type);
3845 return;
3848 if (cc->core_id % smp_threads) {
3849 error_setg(errp, "invalid core id %d", cc->core_id);
3850 return;
3854 * In general we should have homogeneous threads-per-core, but old
3855 * (pre hotplug support) machine types allow the last core to have
3856 * reduced threads as a compatibility hack for when we allowed
3857 * total vcpus not a multiple of threads-per-core.
3859 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) {
3860 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads,
3861 smp_threads);
3862 return;
3865 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3866 if (!core_slot) {
3867 error_setg(errp, "core id %d out of range", cc->core_id);
3868 return;
3871 if (core_slot->cpu) {
3872 error_setg(errp, "core %d already populated", cc->core_id);
3873 return;
3876 numa_cpu_pre_plug(core_slot, dev, errp);
3879 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr,
3880 void *fdt, int *fdt_start_offset, Error **errp)
3882 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev);
3883 int intc_phandle;
3885 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp);
3886 if (intc_phandle <= 0) {
3887 return -1;
3890 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) {
3891 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index);
3892 return -1;
3895 /* generally SLOF creates these, for hotplug it's up to QEMU */
3896 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci"));
3898 return 0;
3901 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3902 Error **errp)
3904 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3905 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev);
3906 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
3907 const unsigned windows_supported = spapr_phb_windows_supported(sphb);
3908 SpaprDrc *drc;
3910 if (dev->hotplugged && !smc->dr_phb_enabled) {
3911 error_setg(errp, "PHB hotplug not supported for this machine");
3912 return false;
3915 if (sphb->index == (uint32_t)-1) {
3916 error_setg(errp, &qu