exec/memory: Use struct Object typedef
[qemu/ar7.git] / hw / intc / sifive_plic.c
blob97a1a27a9acde09bb2a58dba4340f2f4f6ef7349
1 /*
2 * SiFive PLIC (Platform Level Interrupt Controller)
4 * Copyright (c) 2017 SiFive, Inc.
6 * This provides a parameterizable interrupt controller based on SiFive's PLIC.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu/log.h"
24 #include "qemu/module.h"
25 #include "qemu/error-report.h"
26 #include "hw/sysbus.h"
27 #include "hw/pci/msi.h"
28 #include "hw/boards.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/intc/sifive_plic.h"
31 #include "target/riscv/cpu.h"
32 #include "sysemu/sysemu.h"
33 #include "migration/vmstate.h"
35 #define RISCV_DEBUG_PLIC 0
37 static PLICMode char_to_mode(char c)
39 switch (c) {
40 case 'U': return PLICMode_U;
41 case 'S': return PLICMode_S;
42 case 'H': return PLICMode_H;
43 case 'M': return PLICMode_M;
44 default:
45 error_report("plic: invalid mode '%c'", c);
46 exit(1);
50 static char mode_to_char(PLICMode m)
52 switch (m) {
53 case PLICMode_U: return 'U';
54 case PLICMode_S: return 'S';
55 case PLICMode_H: return 'H';
56 case PLICMode_M: return 'M';
57 default: return '?';
61 static void sifive_plic_print_state(SiFivePLICState *plic)
63 int i;
64 int addrid;
66 /* pending */
67 qemu_log("pending : ");
68 for (i = plic->bitfield_words - 1; i >= 0; i--) {
69 qemu_log("%08x", plic->pending[i]);
71 qemu_log("\n");
73 /* pending */
74 qemu_log("claimed : ");
75 for (i = plic->bitfield_words - 1; i >= 0; i--) {
76 qemu_log("%08x", plic->claimed[i]);
78 qemu_log("\n");
80 for (addrid = 0; addrid < plic->num_addrs; addrid++) {
81 qemu_log("hart%d-%c enable: ",
82 plic->addr_config[addrid].hartid,
83 mode_to_char(plic->addr_config[addrid].mode));
84 for (i = plic->bitfield_words - 1; i >= 0; i--) {
85 qemu_log("%08x", plic->enable[addrid * plic->bitfield_words + i]);
87 qemu_log("\n");
91 static uint32_t atomic_set_masked(uint32_t *a, uint32_t mask, uint32_t value)
93 uint32_t old, new, cmp = qatomic_read(a);
95 do {
96 old = cmp;
97 new = (old & ~mask) | (value & mask);
98 cmp = qatomic_cmpxchg(a, old, new);
99 } while (old != cmp);
101 return old;
104 static void sifive_plic_set_pending(SiFivePLICState *plic, int irq, bool level)
106 atomic_set_masked(&plic->pending[irq >> 5], 1 << (irq & 31), -!!level);
109 static void sifive_plic_set_claimed(SiFivePLICState *plic, int irq, bool level)
111 atomic_set_masked(&plic->claimed[irq >> 5], 1 << (irq & 31), -!!level);
114 static int sifive_plic_irqs_pending(SiFivePLICState *plic, uint32_t addrid)
116 int i, j;
117 for (i = 0; i < plic->bitfield_words; i++) {
118 uint32_t pending_enabled_not_claimed =
119 (plic->pending[i] & ~plic->claimed[i]) &
120 plic->enable[addrid * plic->bitfield_words + i];
121 if (!pending_enabled_not_claimed) {
122 continue;
124 for (j = 0; j < 32; j++) {
125 int irq = (i << 5) + j;
126 uint32_t prio = plic->source_priority[irq];
127 int enabled = pending_enabled_not_claimed & (1 << j);
128 if (enabled && prio > plic->target_priority[addrid]) {
129 return 1;
133 return 0;
136 static void sifive_plic_update(SiFivePLICState *plic)
138 int addrid;
140 /* raise irq on harts where this irq is enabled */
141 for (addrid = 0; addrid < plic->num_addrs; addrid++) {
142 uint32_t hartid = plic->addr_config[addrid].hartid;
143 PLICMode mode = plic->addr_config[addrid].mode;
144 CPUState *cpu = qemu_get_cpu(hartid);
145 CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
146 if (!env) {
147 continue;
149 int level = sifive_plic_irqs_pending(plic, addrid);
150 switch (mode) {
151 case PLICMode_M:
152 riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(level));
153 break;
154 case PLICMode_S:
155 riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(level));
156 break;
157 default:
158 break;
162 if (RISCV_DEBUG_PLIC) {
163 sifive_plic_print_state(plic);
167 static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid)
169 int i, j;
170 uint32_t max_irq = 0;
171 uint32_t max_prio = plic->target_priority[addrid];
173 for (i = 0; i < plic->bitfield_words; i++) {
174 uint32_t pending_enabled_not_claimed =
175 (plic->pending[i] & ~plic->claimed[i]) &
176 plic->enable[addrid * plic->bitfield_words + i];
177 if (!pending_enabled_not_claimed) {
178 continue;
180 for (j = 0; j < 32; j++) {
181 int irq = (i << 5) + j;
182 uint32_t prio = plic->source_priority[irq];
183 int enabled = pending_enabled_not_claimed & (1 << j);
184 if (enabled && prio > max_prio) {
185 max_irq = irq;
186 max_prio = prio;
191 if (max_irq) {
192 sifive_plic_set_pending(plic, max_irq, false);
193 sifive_plic_set_claimed(plic, max_irq, true);
195 return max_irq;
198 static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
200 SiFivePLICState *plic = opaque;
202 /* writes must be 4 byte words */
203 if ((addr & 0x3) != 0) {
204 goto err;
207 if (addr >= plic->priority_base && /* 4 bytes per source */
208 addr < plic->priority_base + (plic->num_sources << 2))
210 uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
211 if (RISCV_DEBUG_PLIC) {
212 qemu_log("plic: read priority: irq=%d priority=%d\n",
213 irq, plic->source_priority[irq]);
215 return plic->source_priority[irq];
216 } else if (addr >= plic->pending_base && /* 1 bit per source */
217 addr < plic->pending_base + (plic->num_sources >> 3))
219 uint32_t word = (addr - plic->pending_base) >> 2;
220 if (RISCV_DEBUG_PLIC) {
221 qemu_log("plic: read pending: word=%d value=%d\n",
222 word, plic->pending[word]);
224 return plic->pending[word];
225 } else if (addr >= plic->enable_base && /* 1 bit per source */
226 addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
228 uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride;
229 uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2;
230 if (wordid < plic->bitfield_words) {
231 if (RISCV_DEBUG_PLIC) {
232 qemu_log("plic: read enable: hart%d-%c word=%d value=%x\n",
233 plic->addr_config[addrid].hartid,
234 mode_to_char(plic->addr_config[addrid].mode), wordid,
235 plic->enable[addrid * plic->bitfield_words + wordid]);
237 return plic->enable[addrid * plic->bitfield_words + wordid];
239 } else if (addr >= plic->context_base && /* 1 bit per source */
240 addr < plic->context_base + plic->num_addrs * plic->context_stride)
242 uint32_t addrid = (addr - plic->context_base) / plic->context_stride;
243 uint32_t contextid = (addr & (plic->context_stride - 1));
244 if (contextid == 0) {
245 if (RISCV_DEBUG_PLIC) {
246 qemu_log("plic: read priority: hart%d-%c priority=%x\n",
247 plic->addr_config[addrid].hartid,
248 mode_to_char(plic->addr_config[addrid].mode),
249 plic->target_priority[addrid]);
251 return plic->target_priority[addrid];
252 } else if (contextid == 4) {
253 uint32_t value = sifive_plic_claim(plic, addrid);
254 if (RISCV_DEBUG_PLIC) {
255 qemu_log("plic: read claim: hart%d-%c irq=%x\n",
256 plic->addr_config[addrid].hartid,
257 mode_to_char(plic->addr_config[addrid].mode),
258 value);
260 sifive_plic_update(plic);
261 return value;
265 err:
266 qemu_log_mask(LOG_GUEST_ERROR,
267 "%s: Invalid register read 0x%" HWADDR_PRIx "\n",
268 __func__, addr);
269 return 0;
272 static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
273 unsigned size)
275 SiFivePLICState *plic = opaque;
277 /* writes must be 4 byte words */
278 if ((addr & 0x3) != 0) {
279 goto err;
282 if (addr >= plic->priority_base && /* 4 bytes per source */
283 addr < plic->priority_base + (plic->num_sources << 2))
285 uint32_t irq = ((addr - plic->priority_base) >> 2) + 1;
286 plic->source_priority[irq] = value & 7;
287 if (RISCV_DEBUG_PLIC) {
288 qemu_log("plic: write priority: irq=%d priority=%d\n",
289 irq, plic->source_priority[irq]);
291 sifive_plic_update(plic);
292 return;
293 } else if (addr >= plic->pending_base && /* 1 bit per source */
294 addr < plic->pending_base + (plic->num_sources >> 3))
296 qemu_log_mask(LOG_GUEST_ERROR,
297 "%s: invalid pending write: 0x%" HWADDR_PRIx "",
298 __func__, addr);
299 return;
300 } else if (addr >= plic->enable_base && /* 1 bit per source */
301 addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
303 uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride;
304 uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2;
305 if (wordid < plic->bitfield_words) {
306 plic->enable[addrid * plic->bitfield_words + wordid] = value;
307 if (RISCV_DEBUG_PLIC) {
308 qemu_log("plic: write enable: hart%d-%c word=%d value=%x\n",
309 plic->addr_config[addrid].hartid,
310 mode_to_char(plic->addr_config[addrid].mode), wordid,
311 plic->enable[addrid * plic->bitfield_words + wordid]);
313 return;
315 } else if (addr >= plic->context_base && /* 4 bytes per reg */
316 addr < plic->context_base + plic->num_addrs * plic->context_stride)
318 uint32_t addrid = (addr - plic->context_base) / plic->context_stride;
319 uint32_t contextid = (addr & (plic->context_stride - 1));
320 if (contextid == 0) {
321 if (RISCV_DEBUG_PLIC) {
322 qemu_log("plic: write priority: hart%d-%c priority=%x\n",
323 plic->addr_config[addrid].hartid,
324 mode_to_char(plic->addr_config[addrid].mode),
325 plic->target_priority[addrid]);
327 if (value <= plic->num_priorities) {
328 plic->target_priority[addrid] = value;
329 sifive_plic_update(plic);
331 return;
332 } else if (contextid == 4) {
333 if (RISCV_DEBUG_PLIC) {
334 qemu_log("plic: write claim: hart%d-%c irq=%x\n",
335 plic->addr_config[addrid].hartid,
336 mode_to_char(plic->addr_config[addrid].mode),
337 (uint32_t)value);
339 if (value < plic->num_sources) {
340 sifive_plic_set_claimed(plic, value, false);
341 sifive_plic_update(plic);
343 return;
347 err:
348 qemu_log_mask(LOG_GUEST_ERROR,
349 "%s: Invalid register write 0x%" HWADDR_PRIx "\n",
350 __func__, addr);
353 static const MemoryRegionOps sifive_plic_ops = {
354 .read = sifive_plic_read,
355 .write = sifive_plic_write,
356 .endianness = DEVICE_LITTLE_ENDIAN,
357 .valid = {
358 .min_access_size = 4,
359 .max_access_size = 4
363 static Property sifive_plic_properties[] = {
364 DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
365 DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0),
366 DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 0),
367 DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
368 DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
369 DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
370 DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0),
371 DEFINE_PROP_UINT32("enable-stride", SiFivePLICState, enable_stride, 0),
372 DEFINE_PROP_UINT32("context-base", SiFivePLICState, context_base, 0),
373 DEFINE_PROP_UINT32("context-stride", SiFivePLICState, context_stride, 0),
374 DEFINE_PROP_UINT32("aperture-size", SiFivePLICState, aperture_size, 0),
375 DEFINE_PROP_END_OF_LIST(),
379 * parse PLIC hart/mode address offset config
381 * "M" 1 hart with M mode
382 * "MS,MS" 2 harts, 0-1 with M and S mode
383 * "M,MS,MS,MS,MS" 5 harts, 0 with M mode, 1-5 with M and S mode
385 static void parse_hart_config(SiFivePLICState *plic)
387 int addrid, hartid, modes;
388 const char *p;
389 char c;
391 /* count and validate hart/mode combinations */
392 addrid = 0, hartid = 0, modes = 0;
393 p = plic->hart_config;
394 while ((c = *p++)) {
395 if (c == ',') {
396 addrid += ctpop8(modes);
397 modes = 0;
398 hartid++;
399 } else {
400 int m = 1 << char_to_mode(c);
401 if (modes == (modes | m)) {
402 error_report("plic: duplicate mode '%c' in config: %s",
403 c, plic->hart_config);
404 exit(1);
406 modes |= m;
409 if (modes) {
410 addrid += ctpop8(modes);
412 hartid++;
414 plic->num_addrs = addrid;
415 plic->num_harts = hartid;
417 /* store hart/mode combinations */
418 plic->addr_config = g_new(PLICAddr, plic->num_addrs);
419 addrid = 0, hartid = plic->hartid_base;
420 p = plic->hart_config;
421 while ((c = *p++)) {
422 if (c == ',') {
423 hartid++;
424 } else {
425 plic->addr_config[addrid].addrid = addrid;
426 plic->addr_config[addrid].hartid = hartid;
427 plic->addr_config[addrid].mode = char_to_mode(c);
428 addrid++;
433 static void sifive_plic_irq_request(void *opaque, int irq, int level)
435 SiFivePLICState *plic = opaque;
436 if (RISCV_DEBUG_PLIC) {
437 qemu_log("sifive_plic_irq_request: irq=%d level=%d\n", irq, level);
439 sifive_plic_set_pending(plic, irq, level > 0);
440 sifive_plic_update(plic);
443 static void sifive_plic_realize(DeviceState *dev, Error **errp)
445 SiFivePLICState *plic = SIFIVE_PLIC(dev);
446 int i;
448 memory_region_init_io(&plic->mmio, OBJECT(dev), &sifive_plic_ops, plic,
449 TYPE_SIFIVE_PLIC, plic->aperture_size);
450 parse_hart_config(plic);
451 plic->bitfield_words = (plic->num_sources + 31) >> 5;
452 plic->num_enables = plic->bitfield_words * plic->num_addrs;
453 plic->source_priority = g_new0(uint32_t, plic->num_sources);
454 plic->target_priority = g_new(uint32_t, plic->num_addrs);
455 plic->pending = g_new0(uint32_t, plic->bitfield_words);
456 plic->claimed = g_new0(uint32_t, plic->bitfield_words);
457 plic->enable = g_new0(uint32_t, plic->num_enables);
458 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &plic->mmio);
459 qdev_init_gpio_in(dev, sifive_plic_irq_request, plic->num_sources);
461 /* We can't allow the supervisor to control SEIP as this would allow the
462 * supervisor to clear a pending external interrupt which will result in
463 * lost a interrupt in the case a PLIC is attached. The SEIP bit must be
464 * hardware controlled when a PLIC is attached.
466 for (i = 0; i < plic->num_harts; i++) {
467 RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(plic->hartid_base + i));
468 if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
469 error_report("SEIP already claimed");
470 exit(1);
474 msi_nonbroken = true;
477 static const VMStateDescription vmstate_sifive_plic = {
478 .name = "riscv_sifive_plic",
479 .version_id = 1,
480 .minimum_version_id = 1,
481 .fields = (VMStateField[]) {
482 VMSTATE_VARRAY_UINT32(source_priority, SiFivePLICState,
483 num_sources, 0,
484 vmstate_info_uint32, uint32_t),
485 VMSTATE_VARRAY_UINT32(target_priority, SiFivePLICState,
486 num_addrs, 0,
487 vmstate_info_uint32, uint32_t),
488 VMSTATE_VARRAY_UINT32(pending, SiFivePLICState, bitfield_words, 0,
489 vmstate_info_uint32, uint32_t),
490 VMSTATE_VARRAY_UINT32(claimed, SiFivePLICState, bitfield_words, 0,
491 vmstate_info_uint32, uint32_t),
492 VMSTATE_VARRAY_UINT32(enable, SiFivePLICState, num_enables, 0,
493 vmstate_info_uint32, uint32_t),
494 VMSTATE_END_OF_LIST()
498 static void sifive_plic_class_init(ObjectClass *klass, void *data)
500 DeviceClass *dc = DEVICE_CLASS(klass);
502 device_class_set_props(dc, sifive_plic_properties);
503 dc->realize = sifive_plic_realize;
504 dc->vmsd = &vmstate_sifive_plic;
507 static const TypeInfo sifive_plic_info = {
508 .name = TYPE_SIFIVE_PLIC,
509 .parent = TYPE_SYS_BUS_DEVICE,
510 .instance_size = sizeof(SiFivePLICState),
511 .class_init = sifive_plic_class_init,
514 static void sifive_plic_register_types(void)
516 type_register_static(&sifive_plic_info);
519 type_init(sifive_plic_register_types)
522 * Create PLIC device.
524 DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
525 uint32_t hartid_base, uint32_t num_sources,
526 uint32_t num_priorities, uint32_t priority_base,
527 uint32_t pending_base, uint32_t enable_base,
528 uint32_t enable_stride, uint32_t context_base,
529 uint32_t context_stride, uint32_t aperture_size)
531 DeviceState *dev = qdev_new(TYPE_SIFIVE_PLIC);
532 assert(enable_stride == (enable_stride & -enable_stride));
533 assert(context_stride == (context_stride & -context_stride));
534 qdev_prop_set_string(dev, "hart-config", hart_config);
535 qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
536 qdev_prop_set_uint32(dev, "num-sources", num_sources);
537 qdev_prop_set_uint32(dev, "num-priorities", num_priorities);
538 qdev_prop_set_uint32(dev, "priority-base", priority_base);
539 qdev_prop_set_uint32(dev, "pending-base", pending_base);
540 qdev_prop_set_uint32(dev, "enable-base", enable_base);
541 qdev_prop_set_uint32(dev, "enable-stride", enable_stride);
542 qdev_prop_set_uint32(dev, "context-base", context_base);
543 qdev_prop_set_uint32(dev, "context-stride", context_stride);
544 qdev_prop_set_uint32(dev, "aperture-size", aperture_size);
545 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
546 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
547 return dev;