hw/char/lm32_uart.c

   1 /*
   2  *  QEMU model of the LatticeMico32 UART block.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://www.latticesemi.com/documents/mico32uart.pdf
  22  */
  23
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/irq.h"
  27 #include "hw/qdev-properties.h"
  28 #include "hw/qdev-properties-system.h"
  29 #include "hw/sysbus.h"
  30 #include "migration/vmstate.h"
  31 #include "trace.h"
  32 #include "chardev/char-fe.h"
  33 #include "qemu/error-report.h"
  34 #include "qemu/module.h"
  35 #include "qom/object.h"
  36
  37 enum {
  38     R_RXTX = 0,
  39     R_IER,
  40     R_IIR,
  41     R_LCR,
  42     R_MCR,
  43     R_LSR,
  44     R_MSR,
  45     R_DIV,
  46     R_MAX
  47 };
  48
  49 enum {
  50     IER_RBRI = (1<<0),
  51     IER_THRI = (1<<1),
  52     IER_RLSI = (1<<2),
  53     IER_MSI  = (1<<3),
  54 };
  55
  56 enum {
  57     IIR_STAT = (1<<0),
  58     IIR_ID0  = (1<<1),
  59     IIR_ID1  = (1<<2),
  60 };
  61
  62 enum {
  63     LCR_WLS0 = (1<<0),
  64     LCR_WLS1 = (1<<1),
  65     LCR_STB  = (1<<2),
  66     LCR_PEN  = (1<<3),
  67     LCR_EPS  = (1<<4),
  68     LCR_SP   = (1<<5),
  69     LCR_SB   = (1<<6),
  70 };
  71
  72 enum {
  73     MCR_DTR  = (1<<0),
  74     MCR_RTS  = (1<<1),
  75 };
  76
  77 enum {
  78     LSR_DR   = (1<<0),
  79     LSR_OE   = (1<<1),
  80     LSR_PE   = (1<<2),
  81     LSR_FE   = (1<<3),
  82     LSR_BI   = (1<<4),
  83     LSR_THRE = (1<<5),
  84     LSR_TEMT = (1<<6),
  85 };
  86
  87 enum {
  88     MSR_DCTS = (1<<0),
  89     MSR_DDSR = (1<<1),
  90     MSR_TERI = (1<<2),
  91     MSR_DDCD = (1<<3),
  92     MSR_CTS  = (1<<4),
  93     MSR_DSR  = (1<<5),
  94     MSR_RI   = (1<<6),
  95     MSR_DCD  = (1<<7),
  96 };
  97
  98 #define TYPE_LM32_UART "lm32-uart"
  99 OBJECT_DECLARE_SIMPLE_TYPE(LM32UartState, LM32_UART)
 100
 101 struct LM32UartState {
 102     SysBusDevice parent_obj;
 103
 104     MemoryRegion iomem;
 105     CharBackend chr;
 106     qemu_irq irq;
 107
 108     uint32_t regs[R_MAX];
 109 };
 110
 111 static void uart_update_irq(LM32UartState *s)
 112 {
 113     unsigned int irq;
 114
 115     if ((s->regs[R_LSR] & (LSR_OE | LSR_PE | LSR_FE | LSR_BI))
 116             && (s->regs[R_IER] & IER_RLSI)) {
 117         irq = 1;
 118         s->regs[R_IIR] = IIR_ID1 | IIR_ID0;
 119     } else if ((s->regs[R_LSR] & LSR_DR) && (s->regs[R_IER] & IER_RBRI)) {
 120         irq = 1;
 121         s->regs[R_IIR] = IIR_ID1;
 122     } else if ((s->regs[R_LSR] & LSR_THRE) && (s->regs[R_IER] & IER_THRI)) {
 123         irq = 1;
 124         s->regs[R_IIR] = IIR_ID0;
 125     } else if ((s->regs[R_MSR] & 0x0f) && (s->regs[R_IER] & IER_MSI)) {
 126         irq = 1;
 127         s->regs[R_IIR] = 0;
 128     } else {
 129         irq = 0;
 130         s->regs[R_IIR] = IIR_STAT;
 131     }
 132
 133     trace_lm32_uart_irq_state(irq);
 134     qemu_set_irq(s->irq, irq);
 135 }
 136
 137 static uint64_t uart_read(void *opaque, hwaddr addr,
 138                           unsigned size)
 139 {
 140     LM32UartState *s = opaque;
 141     uint32_t r = 0;
 142
 143     addr >>= 2;
 144     switch (addr) {
 145     case R_RXTX:
 146         r = s->regs[R_RXTX];
 147         s->regs[R_LSR] &= ~LSR_DR;
 148         uart_update_irq(s);
 149         qemu_chr_fe_accept_input(&s->chr);
 150         break;
 151     case R_IIR:
 152     case R_LSR:
 153     case R_MSR:
 154         r = s->regs[addr];
 155         break;
 156     case R_IER:
 157     case R_LCR:
 158     case R_MCR:
 159     case R_DIV:
 160         error_report("lm32_uart: read access to write only register 0x"
 161                 TARGET_FMT_plx, addr << 2);
 162         break;
 163     default:
 164         error_report("lm32_uart: read access to unknown register 0x"
 165                 TARGET_FMT_plx, addr << 2);
 166         break;
 167     }
 168
 169     trace_lm32_uart_memory_read(addr << 2, r);
 170     return r;
 171 }
 172
 173 static void uart_write(void *opaque, hwaddr addr,
 174                        uint64_t value, unsigned size)
 175 {
 176     LM32UartState *s = opaque;
 177     unsigned char ch = value;
 178
 179     trace_lm32_uart_memory_write(addr, value);
 180
 181     addr >>= 2;
 182     switch (addr) {
 183     case R_RXTX:
 184         /* XXX this blocks entire thread. Rewrite to use
 185          * qemu_chr_fe_write and background I/O callbacks */
 186         qemu_chr_fe_write_all(&s->chr, &ch, 1);
 187         break;
 188     case R_IER:
 189     case R_LCR:
 190     case R_MCR:
 191     case R_DIV:
 192         s->regs[addr] = value;
 193         break;
 194     case R_IIR:
 195     case R_LSR:
 196     case R_MSR:
 197         error_report("lm32_uart: write access to read only register 0x"
 198                 TARGET_FMT_plx, addr << 2);
 199         break;
 200     default:
 201         error_report("lm32_uart: write access to unknown register 0x"
 202                 TARGET_FMT_plx, addr << 2);
 203         break;
 204     }
 205     uart_update_irq(s);
 206 }
 207
 208 static const MemoryRegionOps uart_ops = {
 209     .read = uart_read,
 210     .write = uart_write,
 211     .endianness = DEVICE_NATIVE_ENDIAN,
 212     .valid = {
 213         .min_access_size = 4,
 214         .max_access_size = 4,
 215     },
 216 };
 217
 218 static void uart_rx(void *opaque, const uint8_t *buf, int size)
 219 {
 220     LM32UartState *s = opaque;
 221
 222     if (s->regs[R_LSR] & LSR_DR) {
 223         s->regs[R_LSR] |= LSR_OE;
 224     }
 225
 226     s->regs[R_LSR] |= LSR_DR;
 227     s->regs[R_RXTX] = *buf;
 228
 229     uart_update_irq(s);
 230 }
 231
 232 static int uart_can_rx(void *opaque)
 233 {
 234     LM32UartState *s = opaque;
 235
 236     return !(s->regs[R_LSR] & LSR_DR);
 237 }
 238
 239 static void uart_event(void *opaque, QEMUChrEvent event)
 240 {
 241 }
 242
 243 static void uart_reset(DeviceState *d)
 244 {
 245     LM32UartState *s = LM32_UART(d);
 246     int i;
 247
 248     for (i = 0; i < R_MAX; i++) {
 249         s->regs[i] = 0;
 250     }
 251
 252     /* defaults */
 253     s->regs[R_LSR] = LSR_THRE | LSR_TEMT;
 254 }
 255
 256 static void lm32_uart_init(Object *obj)
 257 {
 258     LM32UartState *s = LM32_UART(obj);
 259     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 260
 261     sysbus_init_irq(dev, &s->irq);
 262
 263     memory_region_init_io(&s->iomem, obj, &uart_ops, s,
 264                           "uart", R_MAX * 4);
 265     sysbus_init_mmio(dev, &s->iomem);
 266 }
 267
 268 static void lm32_uart_realize(DeviceState *dev, Error **errp)
 269 {
 270     LM32UartState *s = LM32_UART(dev);
 271
 272     qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx,
 273                              uart_event, NULL, s, NULL, true);
 274 }
 275
 276 static const VMStateDescription vmstate_lm32_uart = {
 277     .name = "lm32-uart",
 278     .version_id = 1,
 279     .minimum_version_id = 1,
 280     .fields = (VMStateField[]) {
 281         VMSTATE_UINT32_ARRAY(regs, LM32UartState, R_MAX),
 282         VMSTATE_END_OF_LIST()
 283     }
 284 };
 285
 286 static Property lm32_uart_properties[] = {
 287     DEFINE_PROP_CHR("chardev", LM32UartState, chr),
 288     DEFINE_PROP_END_OF_LIST(),
 289 };
 290
 291 static void lm32_uart_class_init(ObjectClass *klass, void *data)
 292 {
 293     DeviceClass *dc = DEVICE_CLASS(klass);
 294
 295     dc->reset = uart_reset;
 296     dc->vmsd = &vmstate_lm32_uart;
 297     device_class_set_props(dc, lm32_uart_properties);
 298     dc->realize = lm32_uart_realize;
 299 }
 300
 301 static const TypeInfo lm32_uart_info = {
 302     .name          = TYPE_LM32_UART,
 303     .parent        = TYPE_SYS_BUS_DEVICE,
 304     .instance_size = sizeof(LM32UartState),
 305     .instance_init = lm32_uart_init,
 306     .class_init    = lm32_uart_class_init,
 307 };
 308
 309 static void lm32_uart_register_types(void)
 310 {
 311     type_register_static(&lm32_uart_info);
 312 }
 313
 314 type_init(lm32_uart_register_types)