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exec/memory: Use struct Object typedef
[qemu/ar7.git] / hw / arm / omap2.c
blob16d388fc79d5e8a680fd86a08a78bf6ec7ecd09c
1 /*
2 * TI OMAP processors emulation.
3 *
4 * Copyright (C) 2007-2008 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/error-report.h"
23 #include "qapi/error.h"
24 #include "cpu.h"
25 #include "exec/address-spaces.h"
26 #include "sysemu/blockdev.h"
27 #include "sysemu/qtest.h"
28 #include "sysemu/reset.h"
29 #include "sysemu/runstate.h"
30 #include "hw/boards.h"
31 #include "hw/irq.h"
32 #include "hw/qdev-properties.h"
33 #include "hw/arm/boot.h"
34 #include "hw/arm/omap.h"
35 #include "sysemu/sysemu.h"
36 #include "qemu/timer.h"
37 #include "chardev/char-fe.h"
38 #include "hw/block/flash.h"
39 #include "hw/arm/soc_dma.h"
40 #include "hw/sysbus.h"
41 #include "audio/audio.h"
42
43 /* Enhanced Audio Controller (CODEC only) */
44 struct omap_eac_s {
45 qemu_irq irq;
46 MemoryRegion iomem;
47
48 uint16_t sysconfig;
49 uint8_t config[4];
50 uint8_t control;
51 uint8_t address;
52 uint16_t data;
53 uint8_t vtol;
54 uint8_t vtsl;
55 uint16_t mixer;
56 uint16_t gain[4];
57 uint8_t att;
58 uint16_t max[7];
59
60 struct {
61 qemu_irq txdrq;
62 qemu_irq rxdrq;
63 uint32_t (*txrx)(void *opaque, uint32_t, int);
64 void *opaque;
65
66 #define EAC_BUF_LEN 1024
67 uint32_t rxbuf[EAC_BUF_LEN];
68 int rxoff;
69 int rxlen;
70 int rxavail;
71 uint32_t txbuf[EAC_BUF_LEN];
72 int txlen;
73 int txavail;
74
75 int enable;
76 int rate;
77
78 uint16_t config[4];
79
80 /* These need to be moved to the actual codec */
81 QEMUSoundCard card;
82 SWVoiceIn *in_voice;
83 SWVoiceOut *out_voice;
84 int hw_enable;
85 } codec;
86
87 struct {
88 uint8_t control;
89 uint16_t config;
90 } modem, bt;
91 };
92
93 static inline void omap_eac_interrupt_update(struct omap_eac_s *s)
94 {
95 qemu_set_irq(s->irq, (s->codec.config[1] >> 14) & 1); /* AURDI */
96 }
97
98 static inline void omap_eac_in_dmarequest_update(struct omap_eac_s *s)
99 {
100 qemu_set_irq(s->codec.rxdrq, (s->codec.rxavail || s->codec.rxlen) &&
101 ((s->codec.config[1] >> 12) & 1)); /* DMAREN */
102 }
103
104 static inline void omap_eac_out_dmarequest_update(struct omap_eac_s *s)
105 {
106 qemu_set_irq(s->codec.txdrq, s->codec.txlen < s->codec.txavail &&
107 ((s->codec.config[1] >> 11) & 1)); /* DMAWEN */
108 }
109
110 static inline void omap_eac_in_refill(struct omap_eac_s *s)
111 {
112 int left = MIN(EAC_BUF_LEN - s->codec.rxlen, s->codec.rxavail) << 2;
113 int start = ((s->codec.rxoff + s->codec.rxlen) & (EAC_BUF_LEN - 1)) << 2;
114 int leftwrap = MIN(left, (EAC_BUF_LEN << 2) - start);
115 int recv = 1;
116 uint8_t *buf = (uint8_t *) s->codec.rxbuf + start;
117
118 left -= leftwrap;
119 start = 0;
120 while (leftwrap && (recv = AUD_read(s->codec.in_voice, buf + start,
121 leftwrap)) > 0) { /* Be defensive */
122 start += recv;
123 leftwrap -= recv;
124 }
125 if (recv <= 0)
126 s->codec.rxavail = 0;
127 else
128 s->codec.rxavail -= start >> 2;
129 s->codec.rxlen += start >> 2;
130
131 if (recv > 0 && left > 0) {
132 start = 0;
133 while (left && (recv = AUD_read(s->codec.in_voice,
134 (uint8_t *) s->codec.rxbuf + start,
135 left)) > 0) { /* Be defensive */
136 start += recv;
137 left -= recv;
138 }
139 if (recv <= 0)
140 s->codec.rxavail = 0;
141 else
142 s->codec.rxavail -= start >> 2;
143 s->codec.rxlen += start >> 2;
144 }
145 }
146
147 static inline void omap_eac_out_empty(struct omap_eac_s *s)
148 {
149 int left = s->codec.txlen << 2;
150 int start = 0;
151 int sent = 1;
152
153 while (left && (sent = AUD_write(s->codec.out_voice,
154 (uint8_t *) s->codec.txbuf + start,
155 left)) > 0) { /* Be defensive */
156 start += sent;
157 left -= sent;
158 }
159
160 if (!sent) {
161 s->codec.txavail = 0;
162 omap_eac_out_dmarequest_update(s);
163 }
164
165 if (start)
166 s->codec.txlen = 0;
167 }
168
169 static void omap_eac_in_cb(void *opaque, int avail_b)
170 {
171 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
172
173 s->codec.rxavail = avail_b >> 2;
174 omap_eac_in_refill(s);
175 /* TODO: possibly discard current buffer if overrun */
176 omap_eac_in_dmarequest_update(s);
177 }
178
179 static void omap_eac_out_cb(void *opaque, int free_b)
180 {
181 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
182
183 s->codec.txavail = free_b >> 2;
184 if (s->codec.txlen)
185 omap_eac_out_empty(s);
186 else
187 omap_eac_out_dmarequest_update(s);
188 }
189
190 static void omap_eac_enable_update(struct omap_eac_s *s)
191 {
192 s->codec.enable = !(s->codec.config[1] & 1) && /* EACPWD */
193 (s->codec.config[1] & 2) && /* AUDEN */
194 s->codec.hw_enable;
195 }
196
197 static const int omap_eac_fsint[4] = {
198 8000,
199 11025,
200 22050,
201 44100,
202 };
203
204 static const int omap_eac_fsint2[8] = {
205 8000,
206 11025,
207 22050,
208 44100,
209 48000,
210 0, 0, 0,
211 };
212
213 static const int omap_eac_fsint3[16] = {
214 8000,
215 11025,
216 16000,
217 22050,
218 24000,
219 32000,
220 44100,
221 48000,
222 0, 0, 0, 0, 0, 0, 0, 0,
223 };
224
225 static void omap_eac_rate_update(struct omap_eac_s *s)
226 {
227 int fsint[3];
228
229 fsint[2] = (s->codec.config[3] >> 9) & 0xf;
230 fsint[1] = (s->codec.config[2] >> 0) & 0x7;
231 fsint[0] = (s->codec.config[0] >> 6) & 0x3;
232 if (fsint[2] < 0xf)
233 s->codec.rate = omap_eac_fsint3[fsint[2]];
234 else if (fsint[1] < 0x7)
235 s->codec.rate = omap_eac_fsint2[fsint[1]];
236 else
237 s->codec.rate = omap_eac_fsint[fsint[0]];
238 }
239
240 static void omap_eac_volume_update(struct omap_eac_s *s)
241 {
242 /* TODO */
243 }
244
245 static void omap_eac_format_update(struct omap_eac_s *s)
246 {
247 struct audsettings fmt;
248
249 /* The hardware buffers at most one sample */
250 if (s->codec.rxlen)
251 s->codec.rxlen = 1;
252
253 if (s->codec.in_voice) {
254 AUD_set_active_in(s->codec.in_voice, 0);
255 AUD_close_in(&s->codec.card, s->codec.in_voice);
256 s->codec.in_voice = NULL;
257 }
258 if (s->codec.out_voice) {
259 omap_eac_out_empty(s);
260 AUD_set_active_out(s->codec.out_voice, 0);
261 AUD_close_out(&s->codec.card, s->codec.out_voice);
262 s->codec.out_voice = NULL;
263 s->codec.txavail = 0;
264 }
265 /* Discard what couldn't be written */
266 s->codec.txlen = 0;
267
268 omap_eac_enable_update(s);
269 if (!s->codec.enable)
270 return;
271
272 omap_eac_rate_update(s);
273 fmt.endianness = ((s->codec.config[0] >> 8) & 1); /* LI_BI */
274 fmt.nchannels = ((s->codec.config[0] >> 10) & 1) ? 2 : 1; /* MN_ST */
275 fmt.freq = s->codec.rate;
276 /* TODO: signedness possibly depends on the CODEC hardware - or
277 * does I2S specify it? */
278 /* All register writes are 16 bits so we we store 16-bit samples
279 * in the buffers regardless of AGCFR[B8_16] value. */
280 fmt.fmt = AUDIO_FORMAT_U16;
281
282 s->codec.in_voice = AUD_open_in(&s->codec.card, s->codec.in_voice,
283 "eac.codec.in", s, omap_eac_in_cb, &fmt);
284 s->codec.out_voice = AUD_open_out(&s->codec.card, s->codec.out_voice,
285 "eac.codec.out", s, omap_eac_out_cb, &fmt);
286
287 omap_eac_volume_update(s);
288
289 AUD_set_active_in(s->codec.in_voice, 1);
290 AUD_set_active_out(s->codec.out_voice, 1);
291 }
292
293 static void omap_eac_reset(struct omap_eac_s *s)
294 {
295 s->sysconfig = 0;
296 s->config[0] = 0x0c;
297 s->config[1] = 0x09;
298 s->config[2] = 0xab;
299 s->config[3] = 0x03;
300 s->control = 0x00;
301 s->address = 0x00;
302 s->data = 0x0000;
303 s->vtol = 0x00;
304 s->vtsl = 0x00;
305 s->mixer = 0x0000;
306 s->gain[0] = 0xe7e7;
307 s->gain[1] = 0x6767;
308 s->gain[2] = 0x6767;
309 s->gain[3] = 0x6767;
310 s->att = 0xce;
311 s->max[0] = 0;
312 s->max[1] = 0;
313 s->max[2] = 0;
314 s->max[3] = 0;
315 s->max[4] = 0;
316 s->max[5] = 0;
317 s->max[6] = 0;
318
319 s->modem.control = 0x00;
320 s->modem.config = 0x0000;
321 s->bt.control = 0x00;
322 s->bt.config = 0x0000;
323 s->codec.config[0] = 0x0649;
324 s->codec.config[1] = 0x0000;
325 s->codec.config[2] = 0x0007;
326 s->codec.config[3] = 0x1ffc;
327 s->codec.rxoff = 0;
328 s->codec.rxlen = 0;
329 s->codec.txlen = 0;
330 s->codec.rxavail = 0;
331 s->codec.txavail = 0;
332
333 omap_eac_format_update(s);
334 omap_eac_interrupt_update(s);
335 }
336
337 static uint64_t omap_eac_read(void *opaque, hwaddr addr,
338 unsigned size)
339 {
340 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
341 uint32_t ret;
342
343 if (size != 2) {
344 return omap_badwidth_read16(opaque, addr);
345 }
346
347 switch (addr) {
348 case 0x000: /* CPCFR1 */
349 return s->config[0];
350 case 0x004: /* CPCFR2 */
351 return s->config[1];
352 case 0x008: /* CPCFR3 */
353 return s->config[2];
354 case 0x00c: /* CPCFR4 */
355 return s->config[3];
356
357 case 0x010: /* CPTCTL */
358 return s->control | ((s->codec.rxavail + s->codec.rxlen > 0) << 7) |
359 ((s->codec.txlen < s->codec.txavail) << 5);
360
361 case 0x014: /* CPTTADR */
362 return s->address;
363 case 0x018: /* CPTDATL */
364 return s->data & 0xff;
365 case 0x01c: /* CPTDATH */
366 return s->data >> 8;
367 case 0x020: /* CPTVSLL */
368 return s->vtol;
369 case 0x024: /* CPTVSLH */
370 return s->vtsl | (3 << 5); /* CRDY1 | CRDY2 */
371 case 0x040: /* MPCTR */
372 return s->modem.control;
373 case 0x044: /* MPMCCFR */
374 return s->modem.config;
375 case 0x060: /* BPCTR */
376 return s->bt.control;
377 case 0x064: /* BPMCCFR */
378 return s->bt.config;
379 case 0x080: /* AMSCFR */
380 return s->mixer;
381 case 0x084: /* AMVCTR */
382 return s->gain[0];
383 case 0x088: /* AM1VCTR */
384 return s->gain[1];
385 case 0x08c: /* AM2VCTR */
386 return s->gain[2];
387 case 0x090: /* AM3VCTR */
388 return s->gain[3];
389 case 0x094: /* ASTCTR */
390 return s->att;
391 case 0x098: /* APD1LCR */
392 return s->max[0];
393 case 0x09c: /* APD1RCR */
394 return s->max[1];
395 case 0x0a0: /* APD2LCR */
396 return s->max[2];
397 case 0x0a4: /* APD2RCR */
398 return s->max[3];
399 case 0x0a8: /* APD3LCR */
400 return s->max[4];
401 case 0x0ac: /* APD3RCR */
402 return s->max[5];
403 case 0x0b0: /* APD4R */
404 return s->max[6];
405 case 0x0b4: /* ADWR */
406 /* This should be write-only? Docs list it as read-only. */
407 return 0x0000;
408 case 0x0b8: /* ADRDR */
409 if (likely(s->codec.rxlen > 1)) {
410 ret = s->codec.rxbuf[s->codec.rxoff ++];
411 s->codec.rxlen --;
412 s->codec.rxoff &= EAC_BUF_LEN - 1;
413 return ret;
414 } else if (s->codec.rxlen) {
415 ret = s->codec.rxbuf[s->codec.rxoff ++];
416 s->codec.rxlen --;
417 s->codec.rxoff &= EAC_BUF_LEN - 1;
418 if (s->codec.rxavail)
419 omap_eac_in_refill(s);
420 omap_eac_in_dmarequest_update(s);
421 return ret;
422 }
423 return 0x0000;
424 case 0x0bc: /* AGCFR */
425 return s->codec.config[0];
426 case 0x0c0: /* AGCTR */
427 return s->codec.config[1] | ((s->codec.config[1] & 2) << 14);
428 case 0x0c4: /* AGCFR2 */
429 return s->codec.config[2];
430 case 0x0c8: /* AGCFR3 */
431 return s->codec.config[3];
432 case 0x0cc: /* MBPDMACTR */
433 case 0x0d0: /* MPDDMARR */
434 case 0x0d8: /* MPUDMARR */
435 case 0x0e4: /* BPDDMARR */
436 case 0x0ec: /* BPUDMARR */
437 return 0x0000;
438
439 case 0x100: /* VERSION_NUMBER */
440 return 0x0010;
441
442 case 0x104: /* SYSCONFIG */
443 return s->sysconfig;
444
445 case 0x108: /* SYSSTATUS */
446 return 1 | 0xe; /* RESETDONE | stuff */
447 }
448
449 OMAP_BAD_REG(addr);
450 return 0;
451 }
452
453 static void omap_eac_write(void *opaque, hwaddr addr,
454 uint64_t value, unsigned size)
455 {
456 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
457
458 if (size != 2) {
459 omap_badwidth_write16(opaque, addr, value);
460 return;
461 }
462
463 switch (addr) {
464 case 0x098: /* APD1LCR */
465 case 0x09c: /* APD1RCR */
466 case 0x0a0: /* APD2LCR */
467 case 0x0a4: /* APD2RCR */
468 case 0x0a8: /* APD3LCR */
469 case 0x0ac: /* APD3RCR */
470 case 0x0b0: /* APD4R */
471 case 0x0b8: /* ADRDR */
472 case 0x0d0: /* MPDDMARR */
473 case 0x0d8: /* MPUDMARR */
474 case 0x0e4: /* BPDDMARR */
475 case 0x0ec: /* BPUDMARR */
476 case 0x100: /* VERSION_NUMBER */
477 case 0x108: /* SYSSTATUS */
478 OMAP_RO_REG(addr);
479 return;
480
481 case 0x000: /* CPCFR1 */
482 s->config[0] = value & 0xff;
483 omap_eac_format_update(s);
484 break;
485 case 0x004: /* CPCFR2 */
486 s->config[1] = value & 0xff;
487 omap_eac_format_update(s);
488 break;
489 case 0x008: /* CPCFR3 */
490 s->config[2] = value & 0xff;
491 omap_eac_format_update(s);
492 break;
493 case 0x00c: /* CPCFR4 */
494 s->config[3] = value & 0xff;
495 omap_eac_format_update(s);
496 break;
497
498 case 0x010: /* CPTCTL */
499 /* Assuming TXF and TXE bits are read-only... */
500 s->control = value & 0x5f;
501 omap_eac_interrupt_update(s);
502 break;
503
504 case 0x014: /* CPTTADR */
505 s->address = value & 0xff;
506 break;
507 case 0x018: /* CPTDATL */
508 s->data &= 0xff00;
509 s->data |= value & 0xff;
510 break;
511 case 0x01c: /* CPTDATH */
512 s->data &= 0x00ff;
513 s->data |= value << 8;
514 break;
515 case 0x020: /* CPTVSLL */
516 s->vtol = value & 0xf8;
517 break;
518 case 0x024: /* CPTVSLH */
519 s->vtsl = value & 0x9f;
520 break;
521 case 0x040: /* MPCTR */
522 s->modem.control = value & 0x8f;
523 break;
524 case 0x044: /* MPMCCFR */
525 s->modem.config = value & 0x7fff;
526 break;
527 case 0x060: /* BPCTR */
528 s->bt.control = value & 0x8f;
529 break;
530 case 0x064: /* BPMCCFR */
531 s->bt.config = value & 0x7fff;
532 break;
533 case 0x080: /* AMSCFR */
534 s->mixer = value & 0x0fff;
535 break;
536 case 0x084: /* AMVCTR */
537 s->gain[0] = value & 0xffff;
538 break;
539 case 0x088: /* AM1VCTR */
540 s->gain[1] = value & 0xff7f;
541 break;
542 case 0x08c: /* AM2VCTR */
543 s->gain[2] = value & 0xff7f;
544 break;
545 case 0x090: /* AM3VCTR */
546 s->gain[3] = value & 0xff7f;
547 break;
548 case 0x094: /* ASTCTR */
549 s->att = value & 0xff;
550 break;
551
552 case 0x0b4: /* ADWR */
553 s->codec.txbuf[s->codec.txlen ++] = value;
554 if (unlikely(s->codec.txlen == EAC_BUF_LEN ||
555 s->codec.txlen == s->codec.txavail)) {
556 if (s->codec.txavail)
557 omap_eac_out_empty(s);
558 /* Discard what couldn't be written */
559 s->codec.txlen = 0;
560 }
561 break;
562
563 case 0x0bc: /* AGCFR */
564 s->codec.config[0] = value & 0x07ff;
565 omap_eac_format_update(s);
566 break;
567 case 0x0c0: /* AGCTR */
568 s->codec.config[1] = value & 0x780f;
569 omap_eac_format_update(s);
570 break;
571 case 0x0c4: /* AGCFR2 */
572 s->codec.config[2] = value & 0x003f;
573 omap_eac_format_update(s);
574 break;
575 case 0x0c8: /* AGCFR3 */
576 s->codec.config[3] = value & 0xffff;
577 omap_eac_format_update(s);
578 break;
579 case 0x0cc: /* MBPDMACTR */
580 case 0x0d4: /* MPDDMAWR */
581 case 0x0e0: /* MPUDMAWR */
582 case 0x0e8: /* BPDDMAWR */
583 case 0x0f0: /* BPUDMAWR */
584 break;
585
586 case 0x104: /* SYSCONFIG */
587 if (value & (1 << 1)) /* SOFTRESET */
588 omap_eac_reset(s);
589 s->sysconfig = value & 0x31d;
590 break;
591
592 default:
593 OMAP_BAD_REG(addr);
594 return;
595 }
596 }
597
598 static const MemoryRegionOps omap_eac_ops = {
599 .read = omap_eac_read,
600 .write = omap_eac_write,
601 .endianness = DEVICE_NATIVE_ENDIAN,
602 };
603
604 static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
605 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
606 {
607 struct omap_eac_s *s = g_new0(struct omap_eac_s, 1);
608
609 s->irq = irq;
610 s->codec.rxdrq = *drq ++;
611 s->codec.txdrq = *drq;
612 omap_eac_reset(s);
613
614 AUD_register_card("OMAP EAC", &s->codec.card);
615
616 memory_region_init_io(&s->iomem, NULL, &omap_eac_ops, s, "omap.eac",
617 omap_l4_region_size(ta, 0));
618 omap_l4_attach(ta, 0, &s->iomem);
619
620 return s;
621 }
622
623 /* STI/XTI (emulation interface) console - reverse engineered only */
624 struct omap_sti_s {
625 qemu_irq irq;
626 MemoryRegion iomem;
627 MemoryRegion iomem_fifo;
628 CharBackend chr;
629
630 uint32_t sysconfig;
631 uint32_t systest;
632 uint32_t irqst;
633 uint32_t irqen;
634 uint32_t clkcontrol;
635 uint32_t serial_config;
636 };
637
638 #define STI_TRACE_CONSOLE_CHANNEL 239
639 #define STI_TRACE_CONTROL_CHANNEL 253
640
641 static inline void omap_sti_interrupt_update(struct omap_sti_s *s)
642 {
643 qemu_set_irq(s->irq, s->irqst & s->irqen);
644 }
645
646 static void omap_sti_reset(struct omap_sti_s *s)
647 {
648 s->sysconfig = 0;
649 s->irqst = 0;
650 s->irqen = 0;
651 s->clkcontrol = 0;
652 s->serial_config = 0;
653
654 omap_sti_interrupt_update(s);
655 }
656
657 static uint64_t omap_sti_read(void *opaque, hwaddr addr,
658 unsigned size)
659 {
660 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
661
662 if (size != 4) {
663 return omap_badwidth_read32(opaque, addr);
664 }
665
666 switch (addr) {
667 case 0x00: /* STI_REVISION */
668 return 0x10;
669
670 case 0x10: /* STI_SYSCONFIG */
671 return s->sysconfig;
672
673 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
674 return 0x00;
675
676 case 0x18: /* STI_IRQSTATUS */
677 return s->irqst;
678
679 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
680 return s->irqen;
681
682 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
683 case 0x28: /* STI_RX_DR / XTI_RXDATA */
684 /* TODO */
685 return 0;
686
687 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
688 return s->clkcontrol;
689
690 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
691 return s->serial_config;
692 }
693
694 OMAP_BAD_REG(addr);
695 return 0;
696 }
697
698 static void omap_sti_write(void *opaque, hwaddr addr,
699 uint64_t value, unsigned size)
700 {
701 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
702
703 if (size != 4) {
704 omap_badwidth_write32(opaque, addr, value);
705 return;
706 }
707
708 switch (addr) {
709 case 0x00: /* STI_REVISION */
710 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
711 OMAP_RO_REG(addr);
712 return;
713
714 case 0x10: /* STI_SYSCONFIG */
715 if (value & (1 << 1)) /* SOFTRESET */
716 omap_sti_reset(s);
717 s->sysconfig = value & 0xfe;
718 break;
719
720 case 0x18: /* STI_IRQSTATUS */
721 s->irqst &= ~value;
722 omap_sti_interrupt_update(s);
723 break;
724
725 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
726 s->irqen = value & 0xffff;
727 omap_sti_interrupt_update(s);
728 break;
729
730 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
731 s->clkcontrol = value & 0xff;
732 break;
733
734 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
735 s->serial_config = value & 0xff;
736 break;
737
738 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
739 case 0x28: /* STI_RX_DR / XTI_RXDATA */
740 /* TODO */
741 return;
742
743 default:
744 OMAP_BAD_REG(addr);
745 return;
746 }
747 }
748
749 static const MemoryRegionOps omap_sti_ops = {
750 .read = omap_sti_read,
751 .write = omap_sti_write,
752 .endianness = DEVICE_NATIVE_ENDIAN,
753 };
754
755 static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr,
756 unsigned size)
757 {
758 OMAP_BAD_REG(addr);
759 return 0;
760 }
761
762 static void omap_sti_fifo_write(void *opaque, hwaddr addr,
763 uint64_t value, unsigned size)
764 {
765 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
766 int ch = addr >> 6;
767 uint8_t byte = value;
768
769 if (size != 1) {
770 omap_badwidth_write8(opaque, addr, size);
771 return;
772 }
773
774 if (ch == STI_TRACE_CONTROL_CHANNEL) {
775 /* Flush channel <i>value</i>. */
776 /* XXX this blocks entire thread. Rewrite to use
777 * qemu_chr_fe_write and background I/O callbacks */
778 qemu_chr_fe_write_all(&s->chr, (const uint8_t *) "\r", 1);
779 } else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) {
780 if (value == 0xc0 || value == 0xc3) {
781 /* Open channel <i>ch</i>. */
782 } else if (value == 0x00) {
783 qemu_chr_fe_write_all(&s->chr, (const uint8_t *) "\n", 1);
784 } else {
785 qemu_chr_fe_write_all(&s->chr, &byte, 1);
786 }
787 }
788 }
789
790 static const MemoryRegionOps omap_sti_fifo_ops = {
791 .read = omap_sti_fifo_read,
792 .write = omap_sti_fifo_write,
793 .endianness = DEVICE_NATIVE_ENDIAN,
794 };
795
796 static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
797 MemoryRegion *sysmem,
798 hwaddr channel_base, qemu_irq irq, omap_clk clk,
799 Chardev *chr)
800 {
801 struct omap_sti_s *s = g_new0(struct omap_sti_s, 1);
802
803 s->irq = irq;
804 omap_sti_reset(s);
805
806 qemu_chr_fe_init(&s->chr, chr ?: qemu_chr_new("null", "null", NULL),
807 &error_abort);
808
809 memory_region_init_io(&s->iomem, NULL, &omap_sti_ops, s, "omap.sti",
810 omap_l4_region_size(ta, 0));
811 omap_l4_attach(ta, 0, &s->iomem);
812
813 memory_region_init_io(&s->iomem_fifo, NULL, &omap_sti_fifo_ops, s,
814 "omap.sti.fifo", 0x10000);
815 memory_region_add_subregion(sysmem, channel_base, &s->iomem_fifo);
816
817 return s;
818 }
819
820 /* L4 Interconnect */
821 #define L4TA(n) (n)
822 #define L4TAO(n) ((n) + 39)
823
824 static const struct omap_l4_region_s omap_l4_region[125] = {
825 [ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */
826 [ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */
827 [ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */
828 [ 3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */
829 [ 4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */
830 [ 5] = { 0x04000, 0x1000, 32 | 16 }, /* 32K Timer */
831 [ 6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */
832 [ 7] = { 0x08000, 0x800, 32 }, /* PRCM Region A */
833 [ 8] = { 0x08800, 0x800, 32 }, /* PRCM Region B */
834 [ 9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */
835 [ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */
836 [ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */
837 [ 12] = { 0x14000, 0x1000, 32 }, /* Test/emulation (TAP) */
838 [ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */
839 [ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */
840 [ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */
841 [ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */
842 [ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */
843 [ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */
844 [ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */
845 [ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */
846 [ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */
847 [ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */
848 [ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */
849 [ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */
850 [ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */
851 [ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */
852 [ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */
853 [ 28] = { 0x50000, 0x400, 32 | 16 | 8 }, /* Display top */
854 [ 29] = { 0x50400, 0x400, 32 | 16 | 8 }, /* Display control */
855 [ 30] = { 0x50800, 0x400, 32 | 16 | 8 }, /* Display RFBI */
856 [ 31] = { 0x50c00, 0x400, 32 | 16 | 8 }, /* Display encoder */
857 [ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */
858 [ 33] = { 0x52000, 0x400, 32 | 16 | 8 }, /* Camera top */
859 [ 34] = { 0x52400, 0x400, 32 | 16 | 8 }, /* Camera core */
860 [ 35] = { 0x52800, 0x400, 32 | 16 | 8 }, /* Camera DMA */
861 [ 36] = { 0x52c00, 0x400, 32 | 16 | 8 }, /* Camera MMU */
862 [ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */
863 [ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */
864 [ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */
865 [ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */
866 [ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */
867 [ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */
868 [ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */
869 [ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */
870 [ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */
871 [ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */
872 [ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */
873 [ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */
874 [ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */
875 [ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */
876 [ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */
877 [ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */
878 [ 53] = { 0x66000, 0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */
879 [ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */
880 [ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */
881 [ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */
882 [ 57] = { 0x6a000, 0x1000, 16 | 8 }, /* UART1 */
883 [ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */
884 [ 59] = { 0x6c000, 0x1000, 16 | 8 }, /* UART2 */
885 [ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */
886 [ 61] = { 0x6e000, 0x1000, 16 | 8 }, /* UART3 */
887 [ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */
888 [ 63] = { 0x70000, 0x1000, 16 }, /* I2C1 */
889 [ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */
890 [ 65] = { 0x72000, 0x1000, 16 }, /* I2C2 */
891 [ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */
892 [ 67] = { 0x74000, 0x1000, 16 }, /* McBSP1 */
893 [ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */
894 [ 69] = { 0x76000, 0x1000, 16 }, /* McBSP2 */
895 [ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */
896 [ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */
897 [ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */
898 [ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */
899 [ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */
900 [ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */
901 [ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */
902 [ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */
903 [ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */
904 [ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */
905 [ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */
906 [ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */
907 [ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */
908 [ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */
909 [ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */
910 [ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */
911 [ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */
912 [ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */
913 [ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */
914 [ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */
915 [ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */
916 [ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */
917 [ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */
918 [ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */
919 [ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */
920 [ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */
921 [ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */
922 [ 97] = { 0x90000, 0x1000, 16 }, /* EAC */
923 [ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */
924 [ 99] = { 0x92000, 0x1000, 16 }, /* FAC */
925 [100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */
926 [101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */
927 [102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */
928 [103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */
929 [104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */
930 [105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */
931 [106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */
932 [107] = { 0x9c000, 0x1000, 16 | 8 }, /* MMC SDIO */
933 [108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */
934 [109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */
935 [110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */
936 [111] = { 0xa0000, 0x1000, 32 }, /* RNG */
937 [112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */
938 [113] = { 0xa2000, 0x1000, 32 }, /* DES3DES */
939 [114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */
940 [115] = { 0xa4000, 0x1000, 32 }, /* SHA1MD5 */
941 [116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */
942 [117] = { 0xa6000, 0x1000, 32 }, /* AES */
943 [118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */
944 [119] = { 0xa8000, 0x2000, 32 }, /* PKA */
945 [120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */
946 [121] = { 0xb0000, 0x1000, 32 }, /* MG */
947 [122] = { 0xb1000, 0x1000, 32 | 16 | 8 },
948 [123] = { 0xb2000, 0x1000, 32 }, /* HDQ/1-Wire */
949 [124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */
950 };
951
952 static const struct omap_l4_agent_info_s omap_l4_agent_info[54] = {
953 { 0, 0, 3, 2 }, /* L4IA initiatior agent */
954 { L4TAO(1), 3, 2, 1 }, /* Control and pinout module */
955 { L4TAO(2), 5, 2, 1 }, /* 32K timer */
956 { L4TAO(3), 7, 3, 2 }, /* PRCM */
957 { L4TA(1), 10, 2, 1 }, /* BCM */
958 { L4TA(2), 12, 2, 1 }, /* Test JTAG */
959 { L4TA(3), 14, 6, 3 }, /* Quad GPIO */
960 { L4TA(4), 20, 4, 3 }, /* WD timer 1/2 */
961 { L4TA(7), 24, 2, 1 }, /* GP timer 1 */
962 { L4TA(9), 26, 2, 1 }, /* ATM11 ETB */
963 { L4TA(10), 28, 5, 4 }, /* Display subsystem */
964 { L4TA(11), 33, 5, 4 }, /* Camera subsystem */
965 { L4TA(12), 38, 2, 1 }, /* sDMA */
966 { L4TA(13), 40, 5, 4 }, /* SSI */
967 { L4TAO(4), 45, 2, 1 }, /* USB */
968 { L4TA(14), 47, 2, 1 }, /* Win Tracer1 */
969 { L4TA(15), 49, 2, 1 }, /* Win Tracer2 */
970 { L4TA(16), 51, 2, 1 }, /* Win Tracer3 */
971 { L4TA(17), 53, 2, 1 }, /* Win Tracer4 */
972 { L4TA(18), 55, 2, 1 }, /* XTI */
973 { L4TA(19), 57, 2, 1 }, /* UART1 */
974 { L4TA(20), 59, 2, 1 }, /* UART2 */
975 { L4TA(21), 61, 2, 1 }, /* UART3 */
976 { L4TAO(5), 63, 2, 1 }, /* I2C1 */
977 { L4TAO(6), 65, 2, 1 }, /* I2C2 */
978 { L4TAO(7), 67, 2, 1 }, /* McBSP1 */
979 { L4TAO(8), 69, 2, 1 }, /* McBSP2 */
980 { L4TA(5), 71, 2, 1 }, /* WD Timer 3 (DSP) */
981 { L4TA(6), 73, 2, 1 }, /* WD Timer 4 (IVA) */
982 { L4TA(8), 75, 2, 1 }, /* GP Timer 2 */
983 { L4TA(22), 77, 2, 1 }, /* GP Timer 3 */
984 { L4TA(23), 79, 2, 1 }, /* GP Timer 4 */
985 { L4TA(24), 81, 2, 1 }, /* GP Timer 5 */
986 { L4TA(25), 83, 2, 1 }, /* GP Timer 6 */
987 { L4TA(26), 85, 2, 1 }, /* GP Timer 7 */
988 { L4TA(27), 87, 2, 1 }, /* GP Timer 8 */
989 { L4TA(28), 89, 2, 1 }, /* GP Timer 9 */
990 { L4TA(29), 91, 2, 1 }, /* GP Timer 10 */
991 { L4TA(30), 93, 2, 1 }, /* GP Timer 11 */
992 { L4TA(31), 95, 2, 1 }, /* GP Timer 12 */
993 { L4TA(32), 97, 2, 1 }, /* EAC */
994 { L4TA(33), 99, 2, 1 }, /* FAC */
995 { L4TA(34), 101, 2, 1 }, /* IPC */
996 { L4TA(35), 103, 2, 1 }, /* SPI1 */
997 { L4TA(36), 105, 2, 1 }, /* SPI2 */
998 { L4TAO(9), 107, 2, 1 }, /* MMC SDIO */
999 { L4TAO(10), 109, 2, 1 },
1000 { L4TAO(11), 111, 2, 1 }, /* RNG */
1001 { L4TAO(12), 113, 2, 1 }, /* DES3DES */
1002 { L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */
1003 { L4TA(37), 117, 2, 1 }, /* AES */
1004 { L4TA(38), 119, 2, 1 }, /* PKA */
1005 { -1, 121, 2, 1 },
1006 { L4TA(39), 123, 2, 1 }, /* HDQ/1-Wire */
1007 };
1008
1009 #define omap_l4ta(bus, cs) \
1010 omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TA(cs))
1011 #define omap_l4tao(bus, cs) \
1012 omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TAO(cs))
1013
1014 /* Power, Reset, and Clock Management */
1015 struct omap_prcm_s {
1016 qemu_irq irq[3];
1017 struct omap_mpu_state_s *mpu;
1018 MemoryRegion iomem0;
1019 MemoryRegion iomem1;
1020
1021 uint32_t irqst[3];
1022 uint32_t irqen[3];
1023
1024 uint32_t sysconfig;
1025 uint32_t voltctrl;
1026 uint32_t scratch[20];
1027
1028 uint32_t clksrc[1];
1029 uint32_t clkout[1];
1030 uint32_t clkemul[1];
1031 uint32_t clkpol[1];
1032 uint32_t clksel[8];
1033 uint32_t clken[12];
1034 uint32_t clkctrl[4];
1035 uint32_t clkidle[7];
1036 uint32_t setuptime[2];
1037
1038 uint32_t wkup[3];
1039 uint32_t wken[3];
1040 uint32_t wkst[3];
1041 uint32_t rst[4];
1042 uint32_t rstctrl[1];
1043 uint32_t power[4];
1044 uint32_t rsttime_wkup;
1045
1046 uint32_t ev;
1047 uint32_t evtime[2];
1048
1049 int dpll_lock, apll_lock[2];
1050 };
1051
1052 static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
1053 {
1054 qemu_set_irq(s->irq[dom], s->irqst[dom] & s->irqen[dom]);
1055 /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
1056 }
1057
1058 static uint64_t omap_prcm_read(void *opaque, hwaddr addr,
1059 unsigned size)
1060 {
1061 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
1062 uint32_t ret;
1063
1064 if (size != 4) {
1065 return omap_badwidth_read32(opaque, addr);
1066 }
1067
1068 switch (addr) {
1069 case 0x000: /* PRCM_REVISION */
1070 return 0x10;
1071
1072 case 0x010: /* PRCM_SYSCONFIG */
1073 return s->sysconfig;
1074
1075 case 0x018: /* PRCM_IRQSTATUS_MPU */
1076 return s->irqst[0];
1077
1078 case 0x01c: /* PRCM_IRQENABLE_MPU */
1079 return s->irqen[0];
1080
1081 case 0x050: /* PRCM_VOLTCTRL */
1082 return s->voltctrl;
1083 case 0x054: /* PRCM_VOLTST */
1084 return s->voltctrl & 3;
1085
1086 case 0x060: /* PRCM_CLKSRC_CTRL */
1087 return s->clksrc[0];
1088 case 0x070: /* PRCM_CLKOUT_CTRL */
1089 return s->clkout[0];
1090 case 0x078: /* PRCM_CLKEMUL_CTRL */
1091 return s->clkemul[0];
1092 case 0x080: /* PRCM_CLKCFG_CTRL */
1093 case 0x084: /* PRCM_CLKCFG_STATUS */
1094 return 0;
1095
1096 case 0x090: /* PRCM_VOLTSETUP */
1097 return s->setuptime[0];
1098
1099 case 0x094: /* PRCM_CLKSSETUP */
1100 return s->setuptime[1];
1101
1102 case 0x098: /* PRCM_POLCTRL */
1103 return s->clkpol[0];
1104
1105 case 0x0b0: /* GENERAL_PURPOSE1 */
1106 case 0x0b4: /* GENERAL_PURPOSE2 */
1107 case 0x0b8: /* GENERAL_PURPOSE3 */
1108 case 0x0bc: /* GENERAL_PURPOSE4 */
1109 case 0x0c0: /* GENERAL_PURPOSE5 */
1110 case 0x0c4: /* GENERAL_PURPOSE6 */
1111 case 0x0c8: /* GENERAL_PURPOSE7 */
1112 case 0x0cc: /* GENERAL_PURPOSE8 */
1113 case 0x0d0: /* GENERAL_PURPOSE9 */
1114 case 0x0d4: /* GENERAL_PURPOSE10 */
1115 case 0x0d8: /* GENERAL_PURPOSE11 */
1116 case 0x0dc: /* GENERAL_PURPOSE12 */
1117 case 0x0e0: /* GENERAL_PURPOSE13 */
1118 case 0x0e4: /* GENERAL_PURPOSE14 */
1119 case 0x0e8: /* GENERAL_PURPOSE15 */
1120 case 0x0ec: /* GENERAL_PURPOSE16 */
1121 case 0x0f0: /* GENERAL_PURPOSE17 */
1122 case 0x0f4: /* GENERAL_PURPOSE18 */
1123 case 0x0f8: /* GENERAL_PURPOSE19 */
1124 case 0x0fc: /* GENERAL_PURPOSE20 */
1125 return s->scratch[(addr - 0xb0) >> 2];
1126
1127 case 0x140: /* CM_CLKSEL_MPU */
1128 return s->clksel[0];
1129 case 0x148: /* CM_CLKSTCTRL_MPU */
1130 return s->clkctrl[0];
1131
1132 case 0x158: /* RM_RSTST_MPU */
1133 return s->rst[0];
1134 case 0x1c8: /* PM_WKDEP_MPU */
1135 return s->wkup[0];
1136 case 0x1d4: /* PM_EVGENCTRL_MPU */
1137 return s->ev;
1138 case 0x1d8: /* PM_EVEGENONTIM_MPU */
1139 return s->evtime[0];
1140 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
1141 return s->evtime[1];
1142 case 0x1e0: /* PM_PWSTCTRL_MPU */
1143 return s->power[0];
1144 case 0x1e4: /* PM_PWSTST_MPU */
1145 return 0;
1146
1147 case 0x200: /* CM_FCLKEN1_CORE */
1148 return s->clken[0];
1149 case 0x204: /* CM_FCLKEN2_CORE */
1150 return s->clken[1];
1151 case 0x210: /* CM_ICLKEN1_CORE */
1152 return s->clken[2];
1153 case 0x214: /* CM_ICLKEN2_CORE */
1154 return s->clken[3];
1155 case 0x21c: /* CM_ICLKEN4_CORE */
1156 return s->clken[4];
1157
1158 case 0x220: /* CM_IDLEST1_CORE */
1159 /* TODO: check the actual iclk status */
1160 return 0x7ffffff9;
1161 case 0x224: /* CM_IDLEST2_CORE */
1162 /* TODO: check the actual iclk status */
1163 return 0x00000007;
1164 case 0x22c: /* CM_IDLEST4_CORE */
1165 /* TODO: check the actual iclk status */
1166 return 0x0000001f;
1167
1168 case 0x230: /* CM_AUTOIDLE1_CORE */
1169 return s->clkidle[0];
1170 case 0x234: /* CM_AUTOIDLE2_CORE */
1171 return s->clkidle[1];
1172 case 0x238: /* CM_AUTOIDLE3_CORE */
1173 return s->clkidle[2];
1174 case 0x23c: /* CM_AUTOIDLE4_CORE */
1175 return s->clkidle[3];
1176
1177 case 0x240: /* CM_CLKSEL1_CORE */
1178 return s->clksel[1];
1179 case 0x244: /* CM_CLKSEL2_CORE */
1180 return s->clksel[2];
1181
1182 case 0x248: /* CM_CLKSTCTRL_CORE */
1183 return s->clkctrl[1];
1184
1185 case 0x2a0: /* PM_WKEN1_CORE */
1186 return s->wken[0];
1187 case 0x2a4: /* PM_WKEN2_CORE */
1188 return s->wken[1];
1189
1190 case 0x2b0: /* PM_WKST1_CORE */
1191 return s->wkst[0];
1192 case 0x2b4: /* PM_WKST2_CORE */
1193 return s->wkst[1];
1194 case 0x2c8: /* PM_WKDEP_CORE */
1195 return 0x1e;
1196
1197 case 0x2e0: /* PM_PWSTCTRL_CORE */
1198 return s->power[1];
1199 case 0x2e4: /* PM_PWSTST_CORE */
1200 return 0x000030 | (s->power[1] & 0xfc00);
1201
1202 case 0x300: /* CM_FCLKEN_GFX */
1203 return s->clken[5];
1204 case 0x310: /* CM_ICLKEN_GFX */
1205 return s->clken[6];
1206 case 0x320: /* CM_IDLEST_GFX */
1207 /* TODO: check the actual iclk status */
1208 return 0x00000001;
1209 case 0x340: /* CM_CLKSEL_GFX */
1210 return s->clksel[3];
1211 case 0x348: /* CM_CLKSTCTRL_GFX */
1212 return s->clkctrl[2];
1213 case 0x350: /* RM_RSTCTRL_GFX */
1214 return s->rstctrl[0];
1215 case 0x358: /* RM_RSTST_GFX */
1216 return s->rst[1];
1217 case 0x3c8: /* PM_WKDEP_GFX */
1218 return s->wkup[1];
1219
1220 case 0x3e0: /* PM_PWSTCTRL_GFX */
1221 return s->power[2];
1222 case 0x3e4: /* PM_PWSTST_GFX */
1223 return s->power[2] & 3;
1224
1225 case 0x400: /* CM_FCLKEN_WKUP */
1226 return s->clken[7];
1227 case 0x410: /* CM_ICLKEN_WKUP */
1228 return s->clken[8];
1229 case 0x420: /* CM_IDLEST_WKUP */
1230 /* TODO: check the actual iclk status */
1231 return 0x0000003f;
1232 case 0x430: /* CM_AUTOIDLE_WKUP */
1233 return s->clkidle[4];
1234 case 0x440: /* CM_CLKSEL_WKUP */
1235 return s->clksel[4];
1236 case 0x450: /* RM_RSTCTRL_WKUP */
1237 return 0;
1238 case 0x454: /* RM_RSTTIME_WKUP */
1239 return s->rsttime_wkup;
1240 case 0x458: /* RM_RSTST_WKUP */
1241 return s->rst[2];
1242 case 0x4a0: /* PM_WKEN_WKUP */
1243 return s->wken[2];
1244 case 0x4b0: /* PM_WKST_WKUP */
1245 return s->wkst[2];
1246
1247 case 0x500: /* CM_CLKEN_PLL */
1248 return s->clken[9];
1249 case 0x520: /* CM_IDLEST_CKGEN */
1250 ret = 0x0000070 | (s->apll_lock[0] << 9) | (s->apll_lock[1] << 8);
1251 if (!(s->clksel[6] & 3))
1252 /* Core uses 32-kHz clock */
1253 ret |= 3 << 0;
1254 else if (!s->dpll_lock)
1255 /* DPLL not locked, core uses ref_clk */
1256 ret |= 1 << 0;
1257 else
1258 /* Core uses DPLL */
1259 ret |= 2 << 0;
1260 return ret;
1261 case 0x530: /* CM_AUTOIDLE_PLL */
1262 return s->clkidle[5];
1263 case 0x540: /* CM_CLKSEL1_PLL */
1264 return s->clksel[5];
1265 case 0x544: /* CM_CLKSEL2_PLL */
1266 return s->clksel[6];
1267
1268 case 0x800: /* CM_FCLKEN_DSP */
1269 return s->clken[10];
1270 case 0x810: /* CM_ICLKEN_DSP */
1271 return s->clken[11];
1272 case 0x820: /* CM_IDLEST_DSP */
1273 /* TODO: check the actual iclk status */
1274 return 0x00000103;
1275 case 0x830: /* CM_AUTOIDLE_DSP */
1276 return s->clkidle[6];
1277 case 0x840: /* CM_CLKSEL_DSP */
1278 return s->clksel[7];
1279 case 0x848: /* CM_CLKSTCTRL_DSP */
1280 return s->clkctrl[3];
1281 case 0x850: /* RM_RSTCTRL_DSP */
1282 return 0;
1283 case 0x858: /* RM_RSTST_DSP */
1284 return s->rst[3];
1285 case 0x8c8: /* PM_WKDEP_DSP */
1286 return s->wkup[2];
1287 case 0x8e0: /* PM_PWSTCTRL_DSP */
1288 return s->power[3];
1289 case 0x8e4: /* PM_PWSTST_DSP */
1290 return 0x008030 | (s->power[3] & 0x3003);
1291
1292 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
1293 return s->irqst[1];
1294 case 0x8f4: /* PRCM_IRQENABLE_DSP */
1295 return s->irqen[1];
1296
1297 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
1298 return s->irqst[2];
1299 case 0x8fc: /* PRCM_IRQENABLE_IVA */
1300 return s->irqen[2];
1301 }
1302
1303 OMAP_BAD_REG(addr);
1304 return 0;
1305 }
1306
1307 static void omap_prcm_apll_update(struct omap_prcm_s *s)
1308 {
1309 int mode[2];
1310
1311 mode[0] = (s->clken[9] >> 6) & 3;
1312 s->apll_lock[0] = (mode[0] == 3);
1313 mode[1] = (s->clken[9] >> 2) & 3;
1314 s->apll_lock[1] = (mode[1] == 3);
1315 /* TODO: update clocks */
1316
1317 if (mode[0] == 1 || mode[0] == 2 || mode[1] == 1 || mode[1] == 2)
1318 fprintf(stderr, "%s: bad EN_54M_PLL or bad EN_96M_PLL\n",
1319 __func__);
1320 }
1321
1322 static void omap_prcm_dpll_update(struct omap_prcm_s *s)
1323 {
1324 omap_clk dpll = omap_findclk(s->mpu, "dpll");
1325 omap_clk dpll_x2 = omap_findclk(s->mpu, "dpll");
1326 omap_clk core = omap_findclk(s->mpu, "core_clk");
1327 int mode = (s->clken[9] >> 0) & 3;
1328 int mult, div;
1329
1330 mult = (s->clksel[5] >> 12) & 0x3ff;
1331 div = (s->clksel[5] >> 8) & 0xf;
1332 if (mult == 0 || mult == 1)
1333 mode = 1; /* Bypass */
1334
1335 s->dpll_lock = 0;
1336 switch (mode) {
1337 case 0:
1338 fprintf(stderr, "%s: bad EN_DPLL\n", __func__);
1339 break;
1340 case 1: /* Low-power bypass mode (Default) */
1341 case 2: /* Fast-relock bypass mode */
1342 omap_clk_setrate(dpll, 1, 1);
1343 omap_clk_setrate(dpll_x2, 1, 1);
1344 break;
1345 case 3: /* Lock mode */
1346 s->dpll_lock = 1; /* After 20 FINT cycles (ref_clk / (div + 1)). */
1347
1348 omap_clk_setrate(dpll, div + 1, mult);
1349 omap_clk_setrate(dpll_x2, div + 1, mult * 2);
1350 break;
1351 }
1352
1353 switch ((s->clksel[6] >> 0) & 3) {
1354 case 0:
1355 omap_clk_reparent(core, omap_findclk(s->mpu, "clk32-kHz"));
1356 break;
1357 case 1:
1358 omap_clk_reparent(core, dpll);
1359 break;
1360 case 2:
1361 /* Default */
1362 omap_clk_reparent(core, dpll_x2);
1363 break;
1364 case 3:
1365 fprintf(stderr, "%s: bad CORE_CLK_SRC\n", __func__);
1366 break;
1367 }
1368 }
1369
1370 static void omap_prcm_write(void *opaque, hwaddr addr,
1371 uint64_t value, unsigned size)
1372 {
1373 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
1374
1375 if (size != 4) {
1376 omap_badwidth_write32(opaque, addr, value);
1377 return;
1378 }
1379
1380 switch (addr) {
1381 case 0x000: /* PRCM_REVISION */
1382 case 0x054: /* PRCM_VOLTST */
1383 case 0x084: /* PRCM_CLKCFG_STATUS */
1384 case 0x1e4: /* PM_PWSTST_MPU */
1385 case 0x220: /* CM_IDLEST1_CORE */
1386 case 0x224: /* CM_IDLEST2_CORE */
1387 case 0x22c: /* CM_IDLEST4_CORE */
1388 case 0x2c8: /* PM_WKDEP_CORE */
1389 case 0x2e4: /* PM_PWSTST_CORE */
1390 case 0x320: /* CM_IDLEST_GFX */
1391 case 0x3e4: /* PM_PWSTST_GFX */
1392 case 0x420: /* CM_IDLEST_WKUP */
1393 case 0x520: /* CM_IDLEST_CKGEN */
1394 case 0x820: /* CM_IDLEST_DSP */
1395 case 0x8e4: /* PM_PWSTST_DSP */
1396 OMAP_RO_REG(addr);
1397 return;
1398
1399 case 0x010: /* PRCM_SYSCONFIG */
1400 s->sysconfig = value & 1;
1401 break;
1402
1403 case 0x018: /* PRCM_IRQSTATUS_MPU */
1404 s->irqst[0] &= ~value;
1405 omap_prcm_int_update(s, 0);
1406 break;
1407 case 0x01c: /* PRCM_IRQENABLE_MPU */
1408 s->irqen[0] = value & 0x3f;
1409 omap_prcm_int_update(s, 0);
1410 break;
1411
1412 case 0x050: /* PRCM_VOLTCTRL */
1413 s->voltctrl = value & 0xf1c3;
1414 break;
1415
1416 case 0x060: /* PRCM_CLKSRC_CTRL */
1417 s->clksrc[0] = value & 0xdb;
1418 /* TODO update clocks */
1419 break;
1420
1421 case 0x070: /* PRCM_CLKOUT_CTRL */
1422 s->clkout[0] = value & 0xbbbb;
1423 /* TODO update clocks */
1424 break;
1425
1426 case 0x078: /* PRCM_CLKEMUL_CTRL */
1427 s->clkemul[0] = value & 1;
1428 /* TODO update clocks */
1429 break;
1430
1431 case 0x080: /* PRCM_CLKCFG_CTRL */
1432 break;
1433
1434 case 0x090: /* PRCM_VOLTSETUP */
1435 s->setuptime[0] = value & 0xffff;
1436 break;
1437 case 0x094: /* PRCM_CLKSSETUP */
1438 s->setuptime[1] = value & 0xffff;
1439 break;
1440
1441 case 0x098: /* PRCM_POLCTRL */
1442 s->clkpol[0] = value & 0x701;
1443 break;
1444
1445 case 0x0b0: /* GENERAL_PURPOSE1 */
1446 case 0x0b4: /* GENERAL_PURPOSE2 */
1447 case 0x0b8: /* GENERAL_PURPOSE3 */
1448 case 0x0bc: /* GENERAL_PURPOSE4 */
1449 case 0x0c0: /* GENERAL_PURPOSE5 */
1450 case 0x0c4: /* GENERAL_PURPOSE6 */
1451 case 0x0c8: /* GENERAL_PURPOSE7 */
1452 case 0x0cc: /* GENERAL_PURPOSE8 */
1453 case 0x0d0: /* GENERAL_PURPOSE9 */
1454 case 0x0d4: /* GENERAL_PURPOSE10 */
1455 case 0x0d8: /* GENERAL_PURPOSE11 */
1456 case 0x0dc: /* GENERAL_PURPOSE12 */
1457 case 0x0e0: /* GENERAL_PURPOSE13 */
1458 case 0x0e4: /* GENERAL_PURPOSE14 */
1459 case 0x0e8: /* GENERAL_PURPOSE15 */
1460 case 0x0ec: /* GENERAL_PURPOSE16 */
1461 case 0x0f0: /* GENERAL_PURPOSE17 */
1462 case 0x0f4: /* GENERAL_PURPOSE18 */
1463 case 0x0f8: /* GENERAL_PURPOSE19 */
1464 case 0x0fc: /* GENERAL_PURPOSE20 */
1465 s->scratch[(addr - 0xb0) >> 2] = value;
1466 break;
1467
1468 case 0x140: /* CM_CLKSEL_MPU */
1469 s->clksel[0] = value & 0x1f;
1470 /* TODO update clocks */
1471 break;
1472 case 0x148: /* CM_CLKSTCTRL_MPU */
1473 s->clkctrl[0] = value & 0x1f;
1474 break;
1475
1476 case 0x158: /* RM_RSTST_MPU */
1477 s->rst[0] &= ~value;
1478 break;
1479 case 0x1c8: /* PM_WKDEP_MPU */
1480 s->wkup[0] = value & 0x15;
1481 break;
1482
1483 case 0x1d4: /* PM_EVGENCTRL_MPU */
1484 s->ev = value & 0x1f;
1485 break;
1486 case 0x1d8: /* PM_EVEGENONTIM_MPU */
1487 s->evtime[0] = value;
1488 break;
1489 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
1490 s->evtime[1] = value;
1491 break;
1492
1493 case 0x1e0: /* PM_PWSTCTRL_MPU */
1494 s->power[0] = value & 0xc0f;
1495 break;
1496
1497 case 0x200: /* CM_FCLKEN1_CORE */
1498 s->clken[0] = value & 0xbfffffff;
1499 /* TODO update clocks */
1500 /* The EN_EAC bit only gets/puts func_96m_clk. */
1501 break;
1502 case 0x204: /* CM_FCLKEN2_CORE */
1503 s->clken[1] = value & 0x00000007;
1504 /* TODO update clocks */
1505 break;
1506 case 0x210: /* CM_ICLKEN1_CORE */
1507 s->clken[2] = value & 0xfffffff9;
1508 /* TODO update clocks */
1509 /* The EN_EAC bit only gets/puts core_l4_iclk. */
1510 break;
1511 case 0x214: /* CM_ICLKEN2_CORE */
1512 s->clken[3] = value & 0x00000007;
1513 /* TODO update clocks */
1514 break;
1515 case 0x21c: /* CM_ICLKEN4_CORE */
1516 s->clken[4] = value & 0x0000001f;
1517 /* TODO update clocks */
1518 break;
1519
1520 case 0x230: /* CM_AUTOIDLE1_CORE */
1521 s->clkidle[0] = value & 0xfffffff9;
1522 /* TODO update clocks */
1523 break;
1524 case 0x234: /* CM_AUTOIDLE2_CORE */
1525 s->clkidle[1] = value & 0x00000007;
1526 /* TODO update clocks */
1527 break;
1528 case 0x238: /* CM_AUTOIDLE3_CORE */
1529 s->clkidle[2] = value & 0x00000007;
1530 /* TODO update clocks */
1531 break;
1532 case 0x23c: /* CM_AUTOIDLE4_CORE */
1533 s->clkidle[3] = value & 0x0000001f;
1534 /* TODO update clocks */
1535 break;
1536
1537 case 0x240: /* CM_CLKSEL1_CORE */
1538 s->clksel[1] = value & 0x0fffbf7f;
1539 /* TODO update clocks */
1540 break;
1541
1542 case 0x244: /* CM_CLKSEL2_CORE */
1543 s->clksel[2] = value & 0x00fffffc;
1544 /* TODO update clocks */
1545 break;
1546
1547 case 0x248: /* CM_CLKSTCTRL_CORE */
1548 s->clkctrl[1] = value & 0x7;
1549 break;
1550
1551 case 0x2a0: /* PM_WKEN1_CORE */
1552 s->wken[0] = value & 0x04667ff8;
1553 break;
1554 case 0x2a4: /* PM_WKEN2_CORE */
1555 s->wken[1] = value & 0x00000005;
1556 break;
1557
1558 case 0x2b0: /* PM_WKST1_CORE */
1559 s->wkst[0] &= ~value;
1560 break;
1561 case 0x2b4: /* PM_WKST2_CORE */
1562 s->wkst[1] &= ~value;
1563 break;
1564
1565 case 0x2e0: /* PM_PWSTCTRL_CORE */
1566 s->power[1] = (value & 0x00fc3f) | (1 << 2);
1567 break;
1568
1569 case 0x300: /* CM_FCLKEN_GFX */
1570 s->clken[5] = value & 6;
1571 /* TODO update clocks */
1572 break;
1573 case 0x310: /* CM_ICLKEN_GFX */
1574 s->clken[6] = value & 1;
1575 /* TODO update clocks */
1576 break;
1577 case 0x340: /* CM_CLKSEL_GFX */
1578 s->clksel[3] = value & 7;
1579 /* TODO update clocks */
1580 break;
1581 case 0x348: /* CM_CLKSTCTRL_GFX */
1582 s->clkctrl[2] = value & 1;
1583 break;
1584 case 0x350: /* RM_RSTCTRL_GFX */
1585 s->rstctrl[0] = value & 1;
1586 /* TODO: reset */
1587 break;
1588 case 0x358: /* RM_RSTST_GFX */
1589 s->rst[1] &= ~value;
1590 break;
1591 case 0x3c8: /* PM_WKDEP_GFX */
1592 s->wkup[1] = value & 0x13;
1593 break;
1594 case 0x3e0: /* PM_PWSTCTRL_GFX */
1595 s->power[2] = (value & 0x00c0f) | (3 << 2);
1596 break;
1597
1598 case 0x400: /* CM_FCLKEN_WKUP */
1599 s->clken[7] = value & 0xd;
1600 /* TODO update clocks */
1601 break;
1602 case 0x410: /* CM_ICLKEN_WKUP */
1603 s->clken[8] = value & 0x3f;
1604 /* TODO update clocks */
1605 break;
1606 case 0x430: /* CM_AUTOIDLE_WKUP */
1607 s->clkidle[4] = value & 0x0000003f;
1608 /* TODO update clocks */
1609 break;
1610 case 0x440: /* CM_CLKSEL_WKUP */
1611 s->clksel[4] = value & 3;
1612 /* TODO update clocks */
1613 break;
1614 case 0x450: /* RM_RSTCTRL_WKUP */
1615 /* TODO: reset */
1616 if (value & 2)
1617 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
1618 break;
1619 case 0x454: /* RM_RSTTIME_WKUP */
1620 s->rsttime_wkup = value & 0x1fff;
1621 break;
1622 case 0x458: /* RM_RSTST_WKUP */
1623 s->rst[2] &= ~value;
1624 break;
1625 case 0x4a0: /* PM_WKEN_WKUP */
1626 s->wken[2] = value & 0x00000005;
1627 break;
1628 case 0x4b0: /* PM_WKST_WKUP */
1629 s->wkst[2] &= ~value;
1630 break;
1631
1632 case 0x500: /* CM_CLKEN_PLL */
1633 if (value & 0xffffff30)
1634 fprintf(stderr, "%s: write 0s in CM_CLKEN_PLL for "
1635 "future compatibility\n", __func__);
1636 if ((s->clken[9] ^ value) & 0xcc) {
1637 s->clken[9] &= ~0xcc;
1638 s->clken[9] |= value & 0xcc;
1639 omap_prcm_apll_update(s);
1640 }
1641 if ((s->clken[9] ^ value) & 3) {
1642 s->clken[9] &= ~3;
1643 s->clken[9] |= value & 3;
1644 omap_prcm_dpll_update(s);
1645 }
1646 break;
1647 case 0x530: /* CM_AUTOIDLE_PLL */
1648 s->clkidle[5] = value & 0x000000cf;
1649 /* TODO update clocks */
1650 break;
1651 case 0x540: /* CM_CLKSEL1_PLL */
1652 if (value & 0xfc4000d7)
1653 fprintf(stderr, "%s: write 0s in CM_CLKSEL1_PLL for "
1654 "future compatibility\n", __func__);
1655 if ((s->clksel[5] ^ value) & 0x003fff00) {
1656 s->clksel[5] = value & 0x03bfff28;
1657 omap_prcm_dpll_update(s);
1658 }
1659 /* TODO update the other clocks */
1660
1661 s->clksel[5] = value & 0x03bfff28;
1662 break;
1663 case 0x544: /* CM_CLKSEL2_PLL */
1664 if (value & ~3)
1665 fprintf(stderr, "%s: write 0s in CM_CLKSEL2_PLL[31:2] for "
1666 "future compatibility\n", __func__);
1667 if (s->clksel[6] != (value & 3)) {
1668 s->clksel[6] = value & 3;
1669 omap_prcm_dpll_update(s);
1670 }
1671 break;
1672
1673 case 0x800: /* CM_FCLKEN_DSP */
1674 s->clken[10] = value & 0x501;
1675 /* TODO update clocks */
1676 break;
1677 case 0x810: /* CM_ICLKEN_DSP */
1678 s->clken[11] = value & 0x2;
1679 /* TODO update clocks */
1680 break;
1681 case 0x830: /* CM_AUTOIDLE_DSP */
1682 s->clkidle[6] = value & 0x2;
1683 /* TODO update clocks */
1684 break;
1685 case 0x840: /* CM_CLKSEL_DSP */
1686 s->clksel[7] = value & 0x3fff;
1687 /* TODO update clocks */
1688 break;
1689 case 0x848: /* CM_CLKSTCTRL_DSP */
1690 s->clkctrl[3] = value & 0x101;
1691 break;
1692 case 0x850: /* RM_RSTCTRL_DSP */
1693 /* TODO: reset */
1694 break;
1695 case 0x858: /* RM_RSTST_DSP */
1696 s->rst[3] &= ~value;
1697 break;
1698 case 0x8c8: /* PM_WKDEP_DSP */
1699 s->wkup[2] = value & 0x13;
1700 break;
1701 case 0x8e0: /* PM_PWSTCTRL_DSP */
1702 s->power[3] = (value & 0x03017) | (3 << 2);
1703 break;
1704
1705 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
1706 s->irqst[1] &= ~value;
1707 omap_prcm_int_update(s, 1);
1708 break;
1709 case 0x8f4: /* PRCM_IRQENABLE_DSP */
1710 s->irqen[1] = value & 0x7;
1711 omap_prcm_int_update(s, 1);
1712 break;
1713
1714 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
1715 s->irqst[2] &= ~value;
1716 omap_prcm_int_update(s, 2);
1717 break;
1718 case 0x8fc: /* PRCM_IRQENABLE_IVA */
1719 s->irqen[2] = value & 0x7;
1720 omap_prcm_int_update(s, 2);
1721 break;
1722
1723 default:
1724 OMAP_BAD_REG(addr);
1725 return;
1726 }
1727 }
1728
1729 static const MemoryRegionOps omap_prcm_ops = {
1730 .read = omap_prcm_read,
1731 .write = omap_prcm_write,
1732 .endianness = DEVICE_NATIVE_ENDIAN,
1733 };
1734
1735 static void omap_prcm_reset(struct omap_prcm_s *s)
1736 {
1737 s->sysconfig = 0;
1738 s->irqst[0] = 0;
1739 s->irqst[1] = 0;
1740 s->irqst[2] = 0;
1741 s->irqen[0] = 0;
1742 s->irqen[1] = 0;
1743 s->irqen[2] = 0;
1744 s->voltctrl = 0x1040;
1745 s->ev = 0x14;
1746 s->evtime[0] = 0;
1747 s->evtime[1] = 0;
1748 s->clkctrl[0] = 0;
1749 s->clkctrl[1] = 0;
1750 s->clkctrl[2] = 0;
1751 s->clkctrl[3] = 0;
1752 s->clken[1] = 7;
1753 s->clken[3] = 7;
1754 s->clken[4] = 0;
1755 s->clken[5] = 0;
1756 s->clken[6] = 0;
1757 s->clken[7] = 0xc;
1758 s->clken[8] = 0x3e;
1759 s->clken[9] = 0x0d;
1760 s->clken[10] = 0;
1761 s->clken[11] = 0;
1762 s->clkidle[0] = 0;
1763 s->clkidle[2] = 7;
1764 s->clkidle[3] = 0;
1765 s->clkidle[4] = 0;
1766 s->clkidle[5] = 0x0c;
1767 s->clkidle[6] = 0;
1768 s->clksel[0] = 0x01;
1769 s->clksel[1] = 0x02100121;
1770 s->clksel[2] = 0x00000000;
1771 s->clksel[3] = 0x01;
1772 s->clksel[4] = 0;
1773 s->clksel[7] = 0x0121;
1774 s->wkup[0] = 0x15;
1775 s->wkup[1] = 0x13;
1776 s->wkup[2] = 0x13;
1777 s->wken[0] = 0x04667ff8;
1778 s->wken[1] = 0x00000005;
1779 s->wken[2] = 5;
1780 s->wkst[0] = 0;
1781 s->wkst[1] = 0;
1782 s->wkst[2] = 0;
1783 s->power[0] = 0x00c;
1784 s->power[1] = 4;
1785 s->power[2] = 0x0000c;
1786 s->power[3] = 0x14;
1787 s->rstctrl[0] = 1;
1788 s->rst[3] = 1;
1789 omap_prcm_apll_update(s);
1790 omap_prcm_dpll_update(s);
1791 }
1792
1793 static void omap_prcm_coldreset(struct omap_prcm_s *s)
1794 {
1795 s->setuptime[0] = 0;
1796 s->setuptime[1] = 0;
1797 memset(&s->scratch, 0, sizeof(s->scratch));
1798 s->rst[0] = 0x01;
1799 s->rst[1] = 0x00;
1800 s->rst[2] = 0x01;
1801 s->clken[0] = 0;
1802 s->clken[2] = 0;
1803 s->clkidle[1] = 0;
1804 s->clksel[5] = 0;
1805 s->clksel[6] = 2;
1806 s->clksrc[0] = 0x43;
1807 s->clkout[0] = 0x0303;
1808 s->clkemul[0] = 0;
1809 s->clkpol[0] = 0x100;
1810 s->rsttime_wkup = 0x1002;
1811
1812 omap_prcm_reset(s);
1813 }
1814
1815 static struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
1816 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
1817 struct omap_mpu_state_s *mpu)
1818 {
1819 struct omap_prcm_s *s = g_new0(struct omap_prcm_s, 1);
1820
1821 s->irq[0] = mpu_int;
1822 s->irq[1] = dsp_int;
1823 s->irq[2] = iva_int;
1824 s->mpu = mpu;
1825 omap_prcm_coldreset(s);
1826
1827 memory_region_init_io(&s->iomem0, NULL, &omap_prcm_ops, s, "omap.pcrm0",
1828 omap_l4_region_size(ta, 0));
1829 memory_region_init_io(&s->iomem1, NULL, &omap_prcm_ops, s, "omap.pcrm1",
1830 omap_l4_region_size(ta, 1));
1831 omap_l4_attach(ta, 0, &s->iomem0);
1832 omap_l4_attach(ta, 1, &s->iomem1);
1833
1834 return s;
1835 }
1836
1837 /* System and Pinout control */
1838 struct omap_sysctl_s {
1839 struct omap_mpu_state_s *mpu;
1840 MemoryRegion iomem;
1841
1842 uint32_t sysconfig;
1843 uint32_t devconfig;
1844 uint32_t psaconfig;
1845 uint32_t padconf[0x45];
1846 uint8_t obs;
1847 uint32_t msuspendmux[5];
1848 };
1849
1850 static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr)
1851 {
1852
1853 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
1854 int pad_offset, byte_offset;
1855 int value;
1856
1857 switch (addr) {
1858 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
1859 pad_offset = (addr - 0x30) >> 2;
1860 byte_offset = (addr - 0x30) & (4 - 1);
1861
1862 value = s->padconf[pad_offset];
1863 value = (value >> (byte_offset * 8)) & 0xff;
1864
1865 return value;
1866
1867 default:
1868 break;
1869 }
1870
1871 OMAP_BAD_REG(addr);
1872 return 0;
1873 }
1874
1875 static uint32_t omap_sysctl_read(void *opaque, hwaddr addr)
1876 {
1877 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
1878
1879 switch (addr) {
1880 case 0x000: /* CONTROL_REVISION */
1881 return 0x20;
1882
1883 case 0x010: /* CONTROL_SYSCONFIG */
1884 return s->sysconfig;
1885
1886 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
1887 return s->padconf[(addr - 0x30) >> 2];
1888
1889 case 0x270: /* CONTROL_DEBOBS */
1890 return s->obs;
1891
1892 case 0x274: /* CONTROL_DEVCONF */
1893 return s->devconfig;
1894
1895 case 0x28c: /* CONTROL_EMU_SUPPORT */
1896 return 0;
1897
1898 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
1899 return s->msuspendmux[0];
1900 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
1901 return s->msuspendmux[1];
1902 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
1903 return s->msuspendmux[2];
1904 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
1905 return s->msuspendmux[3];
1906 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
1907 return s->msuspendmux[4];
1908 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
1909 return 0;
1910
1911 case 0x2b8: /* CONTROL_PSA_CTRL */
1912 return s->psaconfig;
1913 case 0x2bc: /* CONTROL_PSA_CMD */
1914 case 0x2c0: /* CONTROL_PSA_VALUE */
1915 return 0;
1916
1917 case 0x2b0: /* CONTROL_SEC_CTRL */
1918 return 0x800000f1;
1919 case 0x2d0: /* CONTROL_SEC_EMU */
1920 return 0x80000015;
1921 case 0x2d4: /* CONTROL_SEC_TAP */
1922 return 0x8000007f;
1923 case 0x2b4: /* CONTROL_SEC_TEST */
1924 case 0x2f0: /* CONTROL_SEC_STATUS */
1925 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
1926 /* Secure mode is not present on general-pusrpose device. Outside
1927 * secure mode these values cannot be read or written. */
1928 return 0;
1929
1930 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
1931 return 0xff;
1932 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
1933 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
1934 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
1935 /* No secure mode so no Extended Secure RAM present. */
1936 return 0;
1937
1938 case 0x2f8: /* CONTROL_STATUS */
1939 /* Device Type => General-purpose */
1940 return 0x0300;
1941 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
1942
1943 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
1944 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
1945 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
1946 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
1947 return 0xdecafbad;
1948
1949 case 0x310: /* CONTROL_RAND_KEY_0 */
1950 case 0x314: /* CONTROL_RAND_KEY_1 */
1951 case 0x318: /* CONTROL_RAND_KEY_2 */
1952 case 0x31c: /* CONTROL_RAND_KEY_3 */
1953 case 0x320: /* CONTROL_CUST_KEY_0 */
1954 case 0x324: /* CONTROL_CUST_KEY_1 */
1955 case 0x330: /* CONTROL_TEST_KEY_0 */
1956 case 0x334: /* CONTROL_TEST_KEY_1 */
1957 case 0x338: /* CONTROL_TEST_KEY_2 */
1958 case 0x33c: /* CONTROL_TEST_KEY_3 */
1959 case 0x340: /* CONTROL_TEST_KEY_4 */
1960 case 0x344: /* CONTROL_TEST_KEY_5 */
1961 case 0x348: /* CONTROL_TEST_KEY_6 */
1962 case 0x34c: /* CONTROL_TEST_KEY_7 */
1963 case 0x350: /* CONTROL_TEST_KEY_8 */
1964 case 0x354: /* CONTROL_TEST_KEY_9 */
1965 /* Can only be accessed in secure mode and when C_FieldAccEnable
1966 * bit is set in CONTROL_SEC_CTRL.
1967 * TODO: otherwise an interconnect access error is generated. */
1968 return 0;
1969 }
1970
1971 OMAP_BAD_REG(addr);
1972 return 0;
1973 }
1974
1975 static void omap_sysctl_write8(void *opaque, hwaddr addr,
1976 uint32_t value)
1977 {
1978 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
1979 int pad_offset, byte_offset;
1980 int prev_value;
1981
1982 switch (addr) {
1983 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
1984 pad_offset = (addr - 0x30) >> 2;
1985 byte_offset = (addr - 0x30) & (4 - 1);
1986
1987 prev_value = s->padconf[pad_offset];
1988 prev_value &= ~(0xff << (byte_offset * 8));
1989 prev_value |= ((value & 0x1f1f1f1f) << (byte_offset * 8)) & 0x1f1f1f1f;
1990 s->padconf[pad_offset] = prev_value;
1991 break;
1992
1993 default:
1994 OMAP_BAD_REG(addr);
1995 break;
1996 }
1997 }
1998
1999 static void omap_sysctl_write(void *opaque, hwaddr addr,
2000 uint32_t value)
2001 {
2002 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
2003
2004 switch (addr) {
2005 case 0x000: /* CONTROL_REVISION */
2006 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
2007 case 0x2c0: /* CONTROL_PSA_VALUE */
2008 case 0x2f8: /* CONTROL_STATUS */
2009 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
2010 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
2011 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
2012 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
2013 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
2014 case 0x310: /* CONTROL_RAND_KEY_0 */
2015 case 0x314: /* CONTROL_RAND_KEY_1 */
2016 case 0x318: /* CONTROL_RAND_KEY_2 */
2017 case 0x31c: /* CONTROL_RAND_KEY_3 */
2018 case 0x320: /* CONTROL_CUST_KEY_0 */
2019 case 0x324: /* CONTROL_CUST_KEY_1 */
2020 case 0x330: /* CONTROL_TEST_KEY_0 */
2021 case 0x334: /* CONTROL_TEST_KEY_1 */
2022 case 0x338: /* CONTROL_TEST_KEY_2 */
2023 case 0x33c: /* CONTROL_TEST_KEY_3 */
2024 case 0x340: /* CONTROL_TEST_KEY_4 */
2025 case 0x344: /* CONTROL_TEST_KEY_5 */
2026 case 0x348: /* CONTROL_TEST_KEY_6 */
2027 case 0x34c: /* CONTROL_TEST_KEY_7 */
2028 case 0x350: /* CONTROL_TEST_KEY_8 */
2029 case 0x354: /* CONTROL_TEST_KEY_9 */
2030 OMAP_RO_REG(addr);
2031 return;
2032
2033 case 0x010: /* CONTROL_SYSCONFIG */
2034 s->sysconfig = value & 0x1e;
2035 break;
2036
2037 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
2038 /* XXX: should check constant bits */
2039 s->padconf[(addr - 0x30) >> 2] = value & 0x1f1f1f1f;
2040 break;
2041
2042 case 0x270: /* CONTROL_DEBOBS */
2043 s->obs = value & 0xff;
2044 break;
2045
2046 case 0x274: /* CONTROL_DEVCONF */
2047 s->devconfig = value & 0xffffc7ff;
2048 break;
2049
2050 case 0x28c: /* CONTROL_EMU_SUPPORT */
2051 break;
2052
2053 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
2054 s->msuspendmux[0] = value & 0x3fffffff;
2055 break;
2056 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
2057 s->msuspendmux[1] = value & 0x3fffffff;
2058 break;
2059 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
2060 s->msuspendmux[2] = value & 0x3fffffff;
2061 break;
2062 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
2063 s->msuspendmux[3] = value & 0x3fffffff;
2064 break;
2065 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
2066 s->msuspendmux[4] = value & 0x3fffffff;
2067 break;
2068
2069 case 0x2b8: /* CONTROL_PSA_CTRL */
2070 s->psaconfig = value & 0x1c;
2071 s->psaconfig |= (value & 0x20) ? 2 : 1;
2072 break;
2073 case 0x2bc: /* CONTROL_PSA_CMD */
2074 break;
2075
2076 case 0x2b0: /* CONTROL_SEC_CTRL */
2077 case 0x2b4: /* CONTROL_SEC_TEST */
2078 case 0x2d0: /* CONTROL_SEC_EMU */
2079 case 0x2d4: /* CONTROL_SEC_TAP */
2080 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
2081 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
2082 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
2083 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
2084 case 0x2f0: /* CONTROL_SEC_STATUS */
2085 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
2086 break;
2087
2088 default:
2089 OMAP_BAD_REG(addr);
2090 return;
2091 }
2092 }
2093
2094 static uint64_t omap_sysctl_readfn(void *opaque, hwaddr addr,
2095 unsigned size)
2096 {
2097 switch (size) {
2098 case 1:
2099 return omap_sysctl_read8(opaque, addr);
2100 case 2:
2101 return omap_badwidth_read32(opaque, addr); /* TODO */
2102 case 4:
2103 return omap_sysctl_read(opaque, addr);
2104 default:
2105 g_assert_not_reached();
2106 }
2107 }
2108
2109 static void omap_sysctl_writefn(void *opaque, hwaddr addr,
2110 uint64_t value, unsigned size)
2111 {
2112 switch (size) {
2113 case 1:
2114 omap_sysctl_write8(opaque, addr, value);
2115 break;
2116 case 2:
2117 omap_badwidth_write32(opaque, addr, value); /* TODO */
2118 break;
2119 case 4:
2120 omap_sysctl_write(opaque, addr, value);
2121 break;
2122 default:
2123 g_assert_not_reached();
2124 }
2125 }
2126
2127 static const MemoryRegionOps omap_sysctl_ops = {
2128 .read = omap_sysctl_readfn,
2129 .write = omap_sysctl_writefn,
2130 .valid.min_access_size = 1,
2131 .valid.max_access_size = 4,
2132 .endianness = DEVICE_NATIVE_ENDIAN,
2133 };
2134
2135 static void omap_sysctl_reset(struct omap_sysctl_s *s)
2136 {
2137 /* (power-on reset) */
2138 s->sysconfig = 0;
2139 s->obs = 0;
2140 s->devconfig = 0x0c000000;
2141 s->msuspendmux[0] = 0x00000000;
2142 s->msuspendmux[1] = 0x00000000;
2143 s->msuspendmux[2] = 0x00000000;
2144 s->msuspendmux[3] = 0x00000000;
2145 s->msuspendmux[4] = 0x00000000;
2146 s->psaconfig = 1;
2147
2148 s->padconf[0x00] = 0x000f0f0f;
2149 s->padconf[0x01] = 0x00000000;
2150 s->padconf[0x02] = 0x00000000;
2151 s->padconf[0x03] = 0x00000000;
2152 s->padconf[0x04] = 0x00000000;
2153 s->padconf[0x05] = 0x00000000;
2154 s->padconf[0x06] = 0x00000000;
2155 s->padconf[0x07] = 0x00000000;
2156 s->padconf[0x08] = 0x08080800;
2157 s->padconf[0x09] = 0x08080808;
2158 s->padconf[0x0a] = 0x08080808;
2159 s->padconf[0x0b] = 0x08080808;
2160 s->padconf[0x0c] = 0x08080808;
2161 s->padconf[0x0d] = 0x08080800;
2162 s->padconf[0x0e] = 0x08080808;
2163 s->padconf[0x0f] = 0x08080808;
2164 s->padconf[0x10] = 0x18181808; /* | 0x07070700 if SBoot3 */
2165 s->padconf[0x11] = 0x18181818; /* | 0x07070707 if SBoot3 */
2166 s->padconf[0x12] = 0x18181818; /* | 0x07070707 if SBoot3 */
2167 s->padconf[0x13] = 0x18181818; /* | 0x07070707 if SBoot3 */
2168 s->padconf[0x14] = 0x18181818; /* | 0x00070707 if SBoot3 */
2169 s->padconf[0x15] = 0x18181818;
2170 s->padconf[0x16] = 0x18181818; /* | 0x07000000 if SBoot3 */
2171 s->padconf[0x17] = 0x1f001f00;
2172 s->padconf[0x18] = 0x1f1f1f1f;
2173 s->padconf[0x19] = 0x00000000;
2174 s->padconf[0x1a] = 0x1f180000;
2175 s->padconf[0x1b] = 0x00001f1f;
2176 s->padconf[0x1c] = 0x1f001f00;
2177 s->padconf[0x1d] = 0x00000000;
2178 s->padconf[0x1e] = 0x00000000;
2179 s->padconf[0x1f] = 0x08000000;
2180 s->padconf[0x20] = 0x08080808;
2181 s->padconf[0x21] = 0x08080808;
2182 s->padconf[0x22] = 0x0f080808;
2183 s->padconf[0x23] = 0x0f0f0f0f;
2184 s->padconf[0x24] = 0x000f0f0f;
2185 s->padconf[0x25] = 0x1f1f1f0f;
2186 s->padconf[0x26] = 0x080f0f1f;
2187 s->padconf[0x27] = 0x070f1808;
2188 s->padconf[0x28] = 0x0f070707;
2189 s->padconf[0x29] = 0x000f0f1f;
2190 s->padconf[0x2a] = 0x0f0f0f1f;
2191 s->padconf[0x2b] = 0x08000000;
2192 s->padconf[0x2c] = 0x0000001f;
2193 s->padconf[0x2d] = 0x0f0f1f00;
2194 s->padconf[0x2e] = 0x1f1f0f0f;
2195 s->padconf[0x2f] = 0x0f1f1f1f;
2196 s->padconf[0x30] = 0x0f0f0f0f;
2197 s->padconf[0x31] = 0x0f1f0f1f;
2198 s->padconf[0x32] = 0x0f0f0f0f;
2199 s->padconf[0x33] = 0x0f1f0f1f;
2200 s->padconf[0x34] = 0x1f1f0f0f;
2201 s->padconf[0x35] = 0x0f0f1f1f;
2202 s->padconf[0x36] = 0x0f0f1f0f;
2203 s->padconf[0x37] = 0x0f0f0f0f;
2204 s->padconf[0x38] = 0x1f18180f;
2205 s->padconf[0x39] = 0x1f1f1f1f;
2206 s->padconf[0x3a] = 0x00001f1f;
2207 s->padconf[0x3b] = 0x00000000;
2208 s->padconf[0x3c] = 0x00000000;
2209 s->padconf[0x3d] = 0x0f0f0f0f;
2210 s->padconf[0x3e] = 0x18000f0f;
2211 s->padconf[0x3f] = 0x00070000;
2212 s->padconf[0x40] = 0x00000707;
2213 s->padconf[0x41] = 0x0f1f0700;
2214 s->padconf[0x42] = 0x1f1f070f;
2215 s->padconf[0x43] = 0x0008081f;
2216 s->padconf[0x44] = 0x00000800;
2217 }
2218
2219 static struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
2220 omap_clk iclk, struct omap_mpu_state_s *mpu)
2221 {
2222 struct omap_sysctl_s *s = g_new0(struct omap_sysctl_s, 1);
2223
2224 s->mpu = mpu;
2225 omap_sysctl_reset(s);
2226
2227 memory_region_init_io(&s->iomem, NULL, &omap_sysctl_ops, s, "omap.sysctl",
2228 omap_l4_region_size(ta, 0));
2229 omap_l4_attach(ta, 0, &s->iomem);
2230
2231 return s;
2232 }
2233
2234 /* General chip reset */
2235 static void omap2_mpu_reset(void *opaque)
2236 {
2237 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
2238
2239 omap_dma_reset(mpu->dma);
2240 omap_prcm_reset(mpu->prcm);
2241 omap_sysctl_reset(mpu->sysc);
2242 omap_gp_timer_reset(mpu->gptimer[0]);
2243 omap_gp_timer_reset(mpu->gptimer[1]);
2244 omap_gp_timer_reset(mpu->gptimer[2]);
2245 omap_gp_timer_reset(mpu->gptimer[3]);
2246 omap_gp_timer_reset(mpu->gptimer[4]);
2247 omap_gp_timer_reset(mpu->gptimer[5]);
2248 omap_gp_timer_reset(mpu->gptimer[6]);
2249 omap_gp_timer_reset(mpu->gptimer[7]);
2250 omap_gp_timer_reset(mpu->gptimer[8]);
2251 omap_gp_timer_reset(mpu->gptimer[9]);
2252 omap_gp_timer_reset(mpu->gptimer[10]);
2253 omap_gp_timer_reset(mpu->gptimer[11]);
2254 omap_synctimer_reset(mpu->synctimer);
2255 omap_sdrc_reset(mpu->sdrc);
2256 omap_gpmc_reset(mpu->gpmc);
2257 omap_dss_reset(mpu->dss);
2258 omap_uart_reset(mpu->uart[0]);
2259 omap_uart_reset(mpu->uart[1]);
2260 omap_uart_reset(mpu->uart[2]);
2261 omap_mmc_reset(mpu->mmc);
2262 omap_mcspi_reset(mpu->mcspi[0]);
2263 omap_mcspi_reset(mpu->mcspi[1]);
2264 cpu_reset(CPU(mpu->cpu));
2265 }
2266
2267 static int omap2_validate_addr(struct omap_mpu_state_s *s,
2268 hwaddr addr)
2269 {
2270 return 1;
2271 }
2272
2273 static const struct dma_irq_map omap2_dma_irq_map[] = {
2274 { 0, OMAP_INT_24XX_SDMA_IRQ0 },
2275 { 0, OMAP_INT_24XX_SDMA_IRQ1 },
2276 { 0, OMAP_INT_24XX_SDMA_IRQ2 },
2277 { 0, OMAP_INT_24XX_SDMA_IRQ3 },
2278 };
2279
2280 struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sdram,
2281 const char *cpu_type)
2282 {
2283 struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);
2284 qemu_irq dma_irqs[4];
2285 DriveInfo *dinfo;
2286 int i;
2287 SysBusDevice *busdev;
2288 struct omap_target_agent_s *ta;
2289 MemoryRegion *sysmem = get_system_memory();
2290
2291 /* Core */
2292 s->mpu_model = omap2420;
2293 s->cpu = ARM_CPU(cpu_create(cpu_type));
2294 s->sram_size = OMAP242X_SRAM_SIZE;
2295
2296 s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0);
2297
2298 /* Clocks */
2299 omap_clk_init(s);
2300
2301 /* Memory-mapped stuff */
2302 memory_region_init_ram(&s->sram, NULL, "omap2.sram", s->sram_size,
2303 &error_fatal);
2304 memory_region_add_subregion(sysmem, OMAP2_SRAM_BASE, &s->sram);
2305
2306 s->l4 = omap_l4_init(sysmem, OMAP2_L4_BASE, 54);
2307
2308 /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
2309 s->ih[0] = qdev_new("omap2-intc");
2310 qdev_prop_set_uint8(s->ih[0], "revision", 0x21);
2311 omap_intc_set_fclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "mpu_intc_fclk"));
2312 omap_intc_set_iclk(OMAP_INTC(s->ih[0]), omap_findclk(s, "mpu_intc_iclk"));
2313 busdev = SYS_BUS_DEVICE(s->ih[0]);
2314 sysbus_realize_and_unref(busdev, &error_fatal);
2315 sysbus_connect_irq(busdev, 0,
2316 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
2317 sysbus_connect_irq(busdev, 1,
2318 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ));
2319 sysbus_mmio_map(busdev, 0, 0x480fe000);
2320 s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3),
2321 qdev_get_gpio_in(s->ih[0],
2322 OMAP_INT_24XX_PRCM_MPU_IRQ),
2323 NULL, NULL, s);
2324
2325 s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1),
2326 omap_findclk(s, "omapctrl_iclk"), s);
2327
2328 for (i = 0; i < 4; i++) {
2329 dma_irqs[i] = qdev_get_gpio_in(s->ih[omap2_dma_irq_map[i].ih],
2330 omap2_dma_irq_map[i].intr);
2331 }
2332 s->dma = omap_dma4_init(0x48056000, dma_irqs, sysmem, s, 256, 32,
2333 omap_findclk(s, "sdma_iclk"),
2334 omap_findclk(s, "sdma_fclk"));
2335 s->port->addr_valid = omap2_validate_addr;
2336
2337 /* Register SDRAM and SRAM ports for fast DMA transfers. */
2338 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(sdram),
2339 OMAP2_Q2_BASE, memory_region_size(sdram));
2340 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sram),
2341 OMAP2_SRAM_BASE, s->sram_size);
2342
2343 s->uart[0] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 19),
2344 qdev_get_gpio_in(s->ih[0],
2345 OMAP_INT_24XX_UART1_IRQ),
2346 omap_findclk(s, "uart1_fclk"),
2347 omap_findclk(s, "uart1_iclk"),
2348 s->drq[OMAP24XX_DMA_UART1_TX],
2349 s->drq[OMAP24XX_DMA_UART1_RX],
2350 "uart1",
2351 serial_hd(0));
2352 s->uart[1] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 20),
2353 qdev_get_gpio_in(s->ih[0],
2354 OMAP_INT_24XX_UART2_IRQ),
2355 omap_findclk(s, "uart2_fclk"),
2356 omap_findclk(s, "uart2_iclk"),
2357 s->drq[OMAP24XX_DMA_UART2_TX],
2358 s->drq[OMAP24XX_DMA_UART2_RX],
2359 "uart2",
2360 serial_hd(0) ? serial_hd(1) : NULL);
2361 s->uart[2] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 21),
2362 qdev_get_gpio_in(s->ih[0],
2363 OMAP_INT_24XX_UART3_IRQ),
2364 omap_findclk(s, "uart3_fclk"),
2365 omap_findclk(s, "uart3_iclk"),
2366 s->drq[OMAP24XX_DMA_UART3_TX],
2367 s->drq[OMAP24XX_DMA_UART3_RX],
2368 "uart3",
2369 serial_hd(0) && serial_hd(1) ? serial_hd(2) : NULL);
2370
2371 s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7),
2372 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER1),
2373 omap_findclk(s, "wu_gpt1_clk"),
2374 omap_findclk(s, "wu_l4_iclk"));
2375 s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8),
2376 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER2),
2377 omap_findclk(s, "core_gpt2_clk"),
2378 omap_findclk(s, "core_l4_iclk"));
2379 s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22),
2380 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER3),
2381 omap_findclk(s, "core_gpt3_clk"),
2382 omap_findclk(s, "core_l4_iclk"));
2383 s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23),
2384 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER4),
2385 omap_findclk(s, "core_gpt4_clk"),
2386 omap_findclk(s, "core_l4_iclk"));
2387 s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24),
2388 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER5),
2389 omap_findclk(s, "core_gpt5_clk"),
2390 omap_findclk(s, "core_l4_iclk"));
2391 s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25),
2392 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER6),
2393 omap_findclk(s, "core_gpt6_clk"),
2394 omap_findclk(s, "core_l4_iclk"));
2395 s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26),
2396 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER7),
2397 omap_findclk(s, "core_gpt7_clk"),
2398 omap_findclk(s, "core_l4_iclk"));
2399 s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27),
2400 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER8),
2401 omap_findclk(s, "core_gpt8_clk"),
2402 omap_findclk(s, "core_l4_iclk"));
2403 s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28),
2404 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER9),
2405 omap_findclk(s, "core_gpt9_clk"),
2406 omap_findclk(s, "core_l4_iclk"));
2407 s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29),
2408 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER10),
2409 omap_findclk(s, "core_gpt10_clk"),
2410 omap_findclk(s, "core_l4_iclk"));
2411 s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30),
2412 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER11),
2413 omap_findclk(s, "core_gpt11_clk"),
2414 omap_findclk(s, "core_l4_iclk"));
2415 s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31),
2416 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER12),
2417 omap_findclk(s, "core_gpt12_clk"),
2418 omap_findclk(s, "core_l4_iclk"));
2419
2420 omap_tap_init(omap_l4ta(s->l4, 2), s);
2421
2422 s->synctimer = omap_synctimer_init(omap_l4tao(s->l4, 2), s,
2423 omap_findclk(s, "clk32-kHz"),
2424 omap_findclk(s, "core_l4_iclk"));
2425
2426 s->i2c[0] = qdev_new("omap_i2c");
2427 qdev_prop_set_uint8(s->i2c[0], "revision", 0x34);
2428 omap_i2c_set_iclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "i2c1.iclk"));
2429 omap_i2c_set_fclk(OMAP_I2C(s->i2c[0]), omap_findclk(s, "i2c1.fclk"));
2430 busdev = SYS_BUS_DEVICE(s->i2c[0]);
2431 sysbus_realize_and_unref(busdev, &error_fatal);
2432 sysbus_connect_irq(busdev, 0,
2433 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C1_IRQ));
2434 sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C1_TX]);
2435 sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C1_RX]);
2436 sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 5), 0));
2437
2438 s->i2c[1] = qdev_new("omap_i2c");
2439 qdev_prop_set_uint8(s->i2c[1], "revision", 0x34);
2440 omap_i2c_set_iclk(OMAP_I2C(s->i2c[1]), omap_findclk(s, "i2c2.iclk"));
2441 omap_i2c_set_fclk(OMAP_I2C(s->i2c[1]), omap_findclk(s, "i2c2.fclk"));
2442 busdev = SYS_BUS_DEVICE(s->i2c[1]);
2443 sysbus_realize_and_unref(busdev, &error_fatal);
2444 sysbus_connect_irq(busdev, 0,
2445 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C2_IRQ));
2446 sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C2_TX]);
2447 sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C2_RX]);
2448 sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 6), 0));
2449
2450 s->gpio = qdev_new("omap2-gpio");
2451 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
2452 omap2_gpio_set_iclk(OMAP2_GPIO(s->gpio), omap_findclk(s, "gpio_iclk"));
2453 omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 0, omap_findclk(s, "gpio1_dbclk"));
2454 omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 1, omap_findclk(s, "gpio2_dbclk"));
2455 omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 2, omap_findclk(s, "gpio3_dbclk"));
2456 omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 3, omap_findclk(s, "gpio4_dbclk"));
2457 if (s->mpu_model == omap2430) {
2458 omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 4,
2459 omap_findclk(s, "gpio5_dbclk"));
2460 }
2461 busdev = SYS_BUS_DEVICE(s->gpio);
2462 sysbus_realize_and_unref(busdev, &error_fatal);
2463 sysbus_connect_irq(busdev, 0,
2464 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK1));
2465 sysbus_connect_irq(busdev, 3,
2466 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK2));
2467 sysbus_connect_irq(busdev, 6,
2468 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK3));
2469 sysbus_connect_irq(busdev, 9,
2470 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK4));
2471 if (s->mpu_model == omap2430) {
2472 sysbus_connect_irq(busdev, 12,
2473 qdev_get_gpio_in(s->ih[0],
2474 OMAP_INT_243X_GPIO_BANK5));
2475 }
2476 ta = omap_l4ta(s->l4, 3);
2477 sysbus_mmio_map(busdev, 0, omap_l4_region_base(ta, 1));
2478 sysbus_mmio_map(busdev, 1, omap_l4_region_base(ta, 0));
2479 sysbus_mmio_map(busdev, 2, omap_l4_region_base(ta, 2));
2480 sysbus_mmio_map(busdev, 3, omap_l4_region_base(ta, 4));
2481 sysbus_mmio_map(busdev, 4, omap_l4_region_base(ta, 5));
2482
2483 s->sdrc = omap_sdrc_init(sysmem, 0x68009000);
2484 s->gpmc = omap_gpmc_init(s, 0x6800a000,
2485 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPMC_IRQ),
2486 s->drq[OMAP24XX_DMA_GPMC]);
2487
2488 dinfo = drive_get(IF_SD, 0, 0);
2489 if (!dinfo && !qtest_enabled()) {
2490 warn_report("missing SecureDigital device");
2491 }
2492 s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9),
2493 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
2494 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MMC_IRQ),
2495 &s->drq[OMAP24XX_DMA_MMC1_TX],
2496 omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk"));
2497
2498 s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4,
2499 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MCSPI1_IRQ),
2500 &s->drq[OMAP24XX_DMA_SPI1_TX0],
2501 omap_findclk(s, "spi1_fclk"),
2502 omap_findclk(s, "spi1_iclk"));
2503 s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2,
2504 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MCSPI2_IRQ),
2505 &s->drq[OMAP24XX_DMA_SPI2_TX0],
2506 omap_findclk(s, "spi2_fclk"),
2507 omap_findclk(s, "spi2_iclk"));
2508
2509 s->dss = omap_dss_init(omap_l4ta(s->l4, 10), sysmem, 0x68000800,
2510 /* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
2511 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_DSS_IRQ),
2512 s->drq[OMAP24XX_DMA_DSS],
2513 omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"),
2514 omap_findclk(s, "dss_54m_clk"),
2515 omap_findclk(s, "dss_l3_iclk"),
2516 omap_findclk(s, "dss_l4_iclk"));
2517
2518 omap_sti_init(omap_l4ta(s->l4, 18), sysmem, 0x54000000,
2519 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_STI),
2520 omap_findclk(s, "emul_ck"),
2521 serial_hd(0) && serial_hd(1) && serial_hd(2) ?
2522 serial_hd(3) : NULL);
2523
2524 s->eac = omap_eac_init(omap_l4ta(s->l4, 32),
2525 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_EAC_IRQ),
2526 /* Ten consecutive lines */
2527 &s->drq[OMAP24XX_DMA_EAC_AC_RD],
2528 omap_findclk(s, "func_96m_clk"),
2529 omap_findclk(s, "core_l4_iclk"));
2530
2531 /* All register mappings (includin those not currenlty implemented):
2532 * SystemControlMod 48000000 - 48000fff
2533 * SystemControlL4 48001000 - 48001fff
2534 * 32kHz Timer Mod 48004000 - 48004fff
2535 * 32kHz Timer L4 48005000 - 48005fff
2536 * PRCM ModA 48008000 - 480087ff
2537 * PRCM ModB 48008800 - 48008fff
2538 * PRCM L4 48009000 - 48009fff
2539 * TEST-BCM Mod 48012000 - 48012fff
2540 * TEST-BCM L4 48013000 - 48013fff
2541 * TEST-TAP Mod 48014000 - 48014fff
2542 * TEST-TAP L4 48015000 - 48015fff
2543 * GPIO1 Mod 48018000 - 48018fff
2544 * GPIO Top 48019000 - 48019fff
2545 * GPIO2 Mod 4801a000 - 4801afff
2546 * GPIO L4 4801b000 - 4801bfff
2547 * GPIO3 Mod 4801c000 - 4801cfff
2548 * GPIO4 Mod 4801e000 - 4801efff
2549 * WDTIMER1 Mod 48020000 - 48010fff
2550 * WDTIMER Top 48021000 - 48011fff
2551 * WDTIMER2 Mod 48022000 - 48012fff
2552 * WDTIMER L4 48023000 - 48013fff
2553 * WDTIMER3 Mod 48024000 - 48014fff
2554 * WDTIMER3 L4 48025000 - 48015fff
2555 * WDTIMER4 Mod 48026000 - 48016fff
2556 * WDTIMER4 L4 48027000 - 48017fff
2557 * GPTIMER1 Mod 48028000 - 48018fff
2558 * GPTIMER1 L4 48029000 - 48019fff
2559 * GPTIMER2 Mod 4802a000 - 4801afff
2560 * GPTIMER2 L4 4802b000 - 4801bfff
2561 * L4-Config AP 48040000 - 480407ff
2562 * L4-Config IP 48040800 - 48040fff
2563 * L4-Config LA 48041000 - 48041fff
2564 * ARM11ETB Mod 48048000 - 48049fff
2565 * ARM11ETB L4 4804a000 - 4804afff
2566 * DISPLAY Top 48050000 - 480503ff
2567 * DISPLAY DISPC 48050400 - 480507ff
2568 * DISPLAY RFBI 48050800 - 48050bff
2569 * DISPLAY VENC 48050c00 - 48050fff
2570 * DISPLAY L4 48051000 - 48051fff
2571 * CAMERA Top 48052000 - 480523ff
2572 * CAMERA core 48052400 - 480527ff
2573 * CAMERA DMA 48052800 - 48052bff
2574 * CAMERA MMU 48052c00 - 48052fff
2575 * CAMERA L4 48053000 - 48053fff
2576 * SDMA Mod 48056000 - 48056fff
2577 * SDMA L4 48057000 - 48057fff
2578 * SSI Top 48058000 - 48058fff
2579 * SSI GDD 48059000 - 48059fff
2580 * SSI Port1 4805a000 - 4805afff
2581 * SSI Port2 4805b000 - 4805bfff
2582 * SSI L4 4805c000 - 4805cfff
2583 * USB Mod 4805e000 - 480fefff
2584 * USB L4 4805f000 - 480fffff
2585 * WIN_TRACER1 Mod 48060000 - 48060fff
2586 * WIN_TRACER1 L4 48061000 - 48061fff
2587 * WIN_TRACER2 Mod 48062000 - 48062fff
2588 * WIN_TRACER2 L4 48063000 - 48063fff
2589 * WIN_TRACER3 Mod 48064000 - 48064fff
2590 * WIN_TRACER3 L4 48065000 - 48065fff
2591 * WIN_TRACER4 Top 48066000 - 480660ff
2592 * WIN_TRACER4 ETT 48066100 - 480661ff
2593 * WIN_TRACER4 WT 48066200 - 480662ff
2594 * WIN_TRACER4 L4 48067000 - 48067fff
2595 * XTI Mod 48068000 - 48068fff
2596 * XTI L4 48069000 - 48069fff
2597 * UART1 Mod 4806a000 - 4806afff
2598 * UART1 L4 4806b000 - 4806bfff
2599 * UART2 Mod 4806c000 - 4806cfff
2600 * UART2 L4 4806d000 - 4806dfff
2601 * UART3 Mod 4806e000 - 4806efff
2602 * UART3 L4 4806f000 - 4806ffff
2603 * I2C1 Mod 48070000 - 48070fff
2604 * I2C1 L4 48071000 - 48071fff
2605 * I2C2 Mod 48072000 - 48072fff
2606 * I2C2 L4 48073000 - 48073fff
2607 * McBSP1 Mod 48074000 - 48074fff
2608 * McBSP1 L4 48075000 - 48075fff
2609 * McBSP2 Mod 48076000 - 48076fff
2610 * McBSP2 L4 48077000 - 48077fff
2611 * GPTIMER3 Mod 48078000 - 48078fff
2612 * GPTIMER3 L4 48079000 - 48079fff
2613 * GPTIMER4 Mod 4807a000 - 4807afff
2614 * GPTIMER4 L4 4807b000 - 4807bfff
2615 * GPTIMER5 Mod 4807c000 - 4807cfff
2616 * GPTIMER5 L4 4807d000 - 4807dfff
2617 * GPTIMER6 Mod 4807e000 - 4807efff
2618 * GPTIMER6 L4 4807f000 - 4807ffff
2619 * GPTIMER7 Mod 48080000 - 48080fff
2620 * GPTIMER7 L4 48081000 - 48081fff
2621 * GPTIMER8 Mod 48082000 - 48082fff
2622 * GPTIMER8 L4 48083000 - 48083fff
2623 * GPTIMER9 Mod 48084000 - 48084fff
2624 * GPTIMER9 L4 48085000 - 48085fff
2625 * GPTIMER10 Mod 48086000 - 48086fff
2626 * GPTIMER10 L4 48087000 - 48087fff
2627 * GPTIMER11 Mod 48088000 - 48088fff
2628 * GPTIMER11 L4 48089000 - 48089fff
2629 * GPTIMER12 Mod 4808a000 - 4808afff
2630 * GPTIMER12 L4 4808b000 - 4808bfff
2631 * EAC Mod 48090000 - 48090fff
2632 * EAC L4 48091000 - 48091fff
2633 * FAC Mod 48092000 - 48092fff
2634 * FAC L4 48093000 - 48093fff
2635 * MAILBOX Mod 48094000 - 48094fff
2636 * MAILBOX L4 48095000 - 48095fff
2637 * SPI1 Mod 48098000 - 48098fff
2638 * SPI1 L4 48099000 - 48099fff
2639 * SPI2 Mod 4809a000 - 4809afff
2640 * SPI2 L4 4809b000 - 4809bfff
2641 * MMC/SDIO Mod 4809c000 - 4809cfff
2642 * MMC/SDIO L4 4809d000 - 4809dfff
2643 * MS_PRO Mod 4809e000 - 4809efff
2644 * MS_PRO L4 4809f000 - 4809ffff
2645 * RNG Mod 480a0000 - 480a0fff
2646 * RNG L4 480a1000 - 480a1fff
2647 * DES3DES Mod 480a2000 - 480a2fff
2648 * DES3DES L4 480a3000 - 480a3fff
2649 * SHA1MD5 Mod 480a4000 - 480a4fff
2650 * SHA1MD5 L4 480a5000 - 480a5fff
2651 * AES Mod 480a6000 - 480a6fff
2652 * AES L4 480a7000 - 480a7fff
2653 * PKA Mod 480a8000 - 480a9fff
2654 * PKA L4 480aa000 - 480aafff
2655 * MG Mod 480b0000 - 480b0fff
2656 * MG L4 480b1000 - 480b1fff
2657 * HDQ/1-wire Mod 480b2000 - 480b2fff
2658 * HDQ/1-wire L4 480b3000 - 480b3fff
2659 * MPU interrupt 480fe000 - 480fefff
2660 * STI channel base 54000000 - 5400ffff
2661 * IVA RAM 5c000000 - 5c01ffff
2662 * IVA ROM 5c020000 - 5c027fff
2663 * IMG_BUF_A 5c040000 - 5c040fff
2664 * IMG_BUF_B 5c042000 - 5c042fff
2665 * VLCDS 5c048000 - 5c0487ff
2666 * IMX_COEF 5c049000 - 5c04afff
2667 * IMX_CMD 5c051000 - 5c051fff
2668 * VLCDQ 5c053000 - 5c0533ff
2669 * VLCDH 5c054000 - 5c054fff
2670 * SEQ_CMD 5c055000 - 5c055fff
2671 * IMX_REG 5c056000 - 5c0560ff
2672 * VLCD_REG 5c056100 - 5c0561ff
2673 * SEQ_REG 5c056200 - 5c0562ff
2674 * IMG_BUF_REG 5c056300 - 5c0563ff
2675 * SEQIRQ_REG 5c056400 - 5c0564ff
2676 * OCP_REG 5c060000 - 5c060fff
2677 * SYSC_REG 5c070000 - 5c070fff
2678 * MMU_REG 5d000000 - 5d000fff
2679 * sDMA R 68000400 - 680005ff
2680 * sDMA W 68000600 - 680007ff
2681 * Display Control 68000800 - 680009ff
2682 * DSP subsystem 68000a00 - 68000bff
2683 * MPU subsystem 68000c00 - 68000dff
2684 * IVA subsystem 68001000 - 680011ff
2685 * USB 68001200 - 680013ff
2686 * Camera 68001400 - 680015ff
2687 * VLYNQ (firewall) 68001800 - 68001bff
2688 * VLYNQ 68001e00 - 68001fff
2689 * SSI 68002000 - 680021ff
2690 * L4 68002400 - 680025ff
2691 * DSP (firewall) 68002800 - 68002bff
2692 * DSP subsystem 68002e00 - 68002fff
2693 * IVA (firewall) 68003000 - 680033ff
2694 * IVA 68003600 - 680037ff
2695 * GFX 68003a00 - 68003bff
2696 * CMDWR emulation 68003c00 - 68003dff
2697 * SMS 68004000 - 680041ff
2698 * OCM 68004200 - 680043ff
2699 * GPMC 68004400 - 680045ff
2700 * RAM (firewall) 68005000 - 680053ff
2701 * RAM (err login) 68005400 - 680057ff
2702 * ROM (firewall) 68005800 - 68005bff
2703 * ROM (err login) 68005c00 - 68005fff
2704 * GPMC (firewall) 68006000 - 680063ff
2705 * GPMC (err login) 68006400 - 680067ff
2706 * SMS (err login) 68006c00 - 68006fff
2707 * SMS registers 68008000 - 68008fff
2708 * SDRC registers 68009000 - 68009fff
2709 * GPMC registers 6800a000 6800afff
2710 */
2711
2712 qemu_register_reset(omap2_mpu_reset, s);
2713
2714 return s;
2715 }
AR7 emulation for QEMU