2 * TI OMAP interrupt controller emulation.
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
5 * Copyright (C) 2007-2008 Nokia Corporation
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
23 #include "hw/qdev-properties.h"
24 #include "hw/arm/omap.h"
25 #include "hw/sysbus.h"
26 #include "qemu/error-report.h"
27 #include "qemu/module.h"
28 #include "qapi/error.h"
30 /* Interrupt Handlers */
31 struct omap_intr_handler_bank_s
{
38 unsigned char priority
[32];
41 #define TYPE_OMAP_INTC "common-omap-intc"
42 #define OMAP_INTC(obj) \
43 OBJECT_CHECK(struct omap_intr_handler_s, (obj), TYPE_OMAP_INTC)
45 struct omap_intr_handler_s
{
46 SysBusDevice parent_obj
;
49 qemu_irq parent_intr
[2];
64 struct omap_intr_handler_bank_s bank
[3];
67 static void omap_inth_sir_update(struct omap_intr_handler_s
*s
, int is_fiq
)
69 int i
, j
, sir_intr
, p_intr
, p
;
74 /* Find the interrupt line with the highest dynamic priority.
75 * Note: 0 denotes the hightest priority.
76 * If all interrupts have the same priority, the default order is IRQ_N,
77 * IRQ_N-1,...,IRQ_0. */
78 for (j
= 0; j
< s
->nbanks
; ++j
) {
79 level
= s
->bank
[j
].irqs
& ~s
->bank
[j
].mask
&
80 (is_fiq
? s
->bank
[j
].fiq
: ~s
->bank
[j
].fiq
);
84 p
= s
->bank
[j
].priority
[i
];
87 sir_intr
= 32 * j
+ i
;
92 s
->sir_intr
[is_fiq
] = sir_intr
;
95 static inline void omap_inth_update(struct omap_intr_handler_s
*s
, int is_fiq
)
98 uint32_t has_intr
= 0;
100 for (i
= 0; i
< s
->nbanks
; ++i
)
101 has_intr
|= s
->bank
[i
].irqs
& ~s
->bank
[i
].mask
&
102 (is_fiq
? s
->bank
[i
].fiq
: ~s
->bank
[i
].fiq
);
104 if (s
->new_agr
[is_fiq
] & has_intr
& s
->mask
) {
105 s
->new_agr
[is_fiq
] = 0;
106 omap_inth_sir_update(s
, is_fiq
);
107 qemu_set_irq(s
->parent_intr
[is_fiq
], 1);
111 #define INT_FALLING_EDGE 0
112 #define INT_LOW_LEVEL 1
114 static void omap_set_intr(void *opaque
, int irq
, int req
)
116 struct omap_intr_handler_s
*ih
= (struct omap_intr_handler_s
*) opaque
;
119 struct omap_intr_handler_bank_s
*bank
= &ih
->bank
[irq
>> 5];
123 rise
= ~bank
->irqs
& (1 << n
);
124 if (~bank
->sens_edge
& (1 << n
))
125 rise
&= ~bank
->inputs
;
127 bank
->inputs
|= (1 << n
);
130 omap_inth_update(ih
, 0);
131 omap_inth_update(ih
, 1);
134 rise
= bank
->sens_edge
& bank
->irqs
& (1 << n
);
136 bank
->inputs
&= ~(1 << n
);
140 /* Simplified version with no edge detection */
141 static void omap_set_intr_noedge(void *opaque
, int irq
, int req
)
143 struct omap_intr_handler_s
*ih
= (struct omap_intr_handler_s
*) opaque
;
146 struct omap_intr_handler_bank_s
*bank
= &ih
->bank
[irq
>> 5];
150 rise
= ~bank
->inputs
& (1 << n
);
152 bank
->irqs
|= bank
->inputs
|= rise
;
153 omap_inth_update(ih
, 0);
154 omap_inth_update(ih
, 1);
157 bank
->irqs
= (bank
->inputs
&= ~(1 << n
)) | bank
->swi
;
160 static uint64_t omap_inth_read(void *opaque
, hwaddr addr
,
163 struct omap_intr_handler_s
*s
= (struct omap_intr_handler_s
*) opaque
;
164 int i
, offset
= addr
;
165 int bank_no
= offset
>> 8;
167 struct omap_intr_handler_bank_s
*bank
= &s
->bank
[bank_no
];
177 case 0x10: /* SIR_IRQ_CODE */
178 case 0x14: /* SIR_FIQ_CODE */
181 line_no
= s
->sir_intr
[(offset
- 0x10) >> 2];
182 bank
= &s
->bank
[line_no
>> 5];
184 if (((bank
->sens_edge
>> i
) & 1) == INT_FALLING_EDGE
)
185 bank
->irqs
&= ~(1 << i
);
188 case 0x18: /* CONTROL_REG */
193 case 0x1c: /* ILR0 */
194 case 0x20: /* ILR1 */
195 case 0x24: /* ILR2 */
196 case 0x28: /* ILR3 */
197 case 0x2c: /* ILR4 */
198 case 0x30: /* ILR5 */
199 case 0x34: /* ILR6 */
200 case 0x38: /* ILR7 */
201 case 0x3c: /* ILR8 */
202 case 0x40: /* ILR9 */
203 case 0x44: /* ILR10 */
204 case 0x48: /* ILR11 */
205 case 0x4c: /* ILR12 */
206 case 0x50: /* ILR13 */
207 case 0x54: /* ILR14 */
208 case 0x58: /* ILR15 */
209 case 0x5c: /* ILR16 */
210 case 0x60: /* ILR17 */
211 case 0x64: /* ILR18 */
212 case 0x68: /* ILR19 */
213 case 0x6c: /* ILR20 */
214 case 0x70: /* ILR21 */
215 case 0x74: /* ILR22 */
216 case 0x78: /* ILR23 */
217 case 0x7c: /* ILR24 */
218 case 0x80: /* ILR25 */
219 case 0x84: /* ILR26 */
220 case 0x88: /* ILR27 */
221 case 0x8c: /* ILR28 */
222 case 0x90: /* ILR29 */
223 case 0x94: /* ILR30 */
224 case 0x98: /* ILR31 */
225 i
= (offset
- 0x1c) >> 2;
226 return (bank
->priority
[i
] << 2) |
227 (((bank
->sens_edge
>> i
) & 1) << 1) |
228 ((bank
->fiq
>> i
) & 1);
238 static void omap_inth_write(void *opaque
, hwaddr addr
,
239 uint64_t value
, unsigned size
)
241 struct omap_intr_handler_s
*s
= (struct omap_intr_handler_s
*) opaque
;
242 int i
, offset
= addr
;
243 int bank_no
= offset
>> 8;
244 struct omap_intr_handler_bank_s
*bank
= &s
->bank
[bank_no
];
249 /* Important: ignore the clearing if the IRQ is level-triggered and
250 the input bit is 1 */
251 bank
->irqs
&= value
| (bank
->inputs
& bank
->sens_edge
);
256 omap_inth_update(s
, 0);
257 omap_inth_update(s
, 1);
260 case 0x10: /* SIR_IRQ_CODE */
261 case 0x14: /* SIR_FIQ_CODE */
265 case 0x18: /* CONTROL_REG */
269 qemu_set_irq(s
->parent_intr
[1], 0);
271 omap_inth_update(s
, 1);
274 qemu_set_irq(s
->parent_intr
[0], 0);
276 omap_inth_update(s
, 0);
280 case 0x1c: /* ILR0 */
281 case 0x20: /* ILR1 */
282 case 0x24: /* ILR2 */
283 case 0x28: /* ILR3 */
284 case 0x2c: /* ILR4 */
285 case 0x30: /* ILR5 */
286 case 0x34: /* ILR6 */
287 case 0x38: /* ILR7 */
288 case 0x3c: /* ILR8 */
289 case 0x40: /* ILR9 */
290 case 0x44: /* ILR10 */
291 case 0x48: /* ILR11 */
292 case 0x4c: /* ILR12 */
293 case 0x50: /* ILR13 */
294 case 0x54: /* ILR14 */
295 case 0x58: /* ILR15 */
296 case 0x5c: /* ILR16 */
297 case 0x60: /* ILR17 */
298 case 0x64: /* ILR18 */
299 case 0x68: /* ILR19 */
300 case 0x6c: /* ILR20 */
301 case 0x70: /* ILR21 */
302 case 0x74: /* ILR22 */
303 case 0x78: /* ILR23 */
304 case 0x7c: /* ILR24 */
305 case 0x80: /* ILR25 */
306 case 0x84: /* ILR26 */
307 case 0x88: /* ILR27 */
308 case 0x8c: /* ILR28 */
309 case 0x90: /* ILR29 */
310 case 0x94: /* ILR30 */
311 case 0x98: /* ILR31 */
312 i
= (offset
- 0x1c) >> 2;
313 bank
->priority
[i
] = (value
>> 2) & 0x1f;
314 bank
->sens_edge
&= ~(1 << i
);
315 bank
->sens_edge
|= ((value
>> 1) & 1) << i
;
316 bank
->fiq
&= ~(1 << i
);
317 bank
->fiq
|= (value
& 1) << i
;
321 for (i
= 0; i
< 32; i
++)
322 if (value
& (1 << i
)) {
323 omap_set_intr(s
, 32 * bank_no
+ i
, 1);
331 static const MemoryRegionOps omap_inth_mem_ops
= {
332 .read
= omap_inth_read
,
333 .write
= omap_inth_write
,
334 .endianness
= DEVICE_NATIVE_ENDIAN
,
336 .min_access_size
= 4,
337 .max_access_size
= 4,
341 static void omap_inth_reset(DeviceState
*dev
)
343 struct omap_intr_handler_s
*s
= OMAP_INTC(dev
);
346 for (i
= 0; i
< s
->nbanks
; ++i
){
347 s
->bank
[i
].irqs
= 0x00000000;
348 s
->bank
[i
].mask
= 0xffffffff;
349 s
->bank
[i
].sens_edge
= 0x00000000;
350 s
->bank
[i
].fiq
= 0x00000000;
351 s
->bank
[i
].inputs
= 0x00000000;
352 s
->bank
[i
].swi
= 0x00000000;
353 memset(s
->bank
[i
].priority
, 0, sizeof(s
->bank
[i
].priority
));
356 s
->bank
[i
].sens_edge
= 0xffffffff;
366 qemu_set_irq(s
->parent_intr
[0], 0);
367 qemu_set_irq(s
->parent_intr
[1], 0);
370 static void omap_intc_init(Object
*obj
)
372 DeviceState
*dev
= DEVICE(obj
);
373 struct omap_intr_handler_s
*s
= OMAP_INTC(obj
);
374 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
377 sysbus_init_irq(sbd
, &s
->parent_intr
[0]);
378 sysbus_init_irq(sbd
, &s
->parent_intr
[1]);
379 qdev_init_gpio_in(dev
, omap_set_intr
, s
->nbanks
* 32);
380 memory_region_init_io(&s
->mmio
, obj
, &omap_inth_mem_ops
, s
,
381 "omap-intc", s
->size
);
382 sysbus_init_mmio(sbd
, &s
->mmio
);
385 static void omap_intc_realize(DeviceState
*dev
, Error
**errp
)
387 struct omap_intr_handler_s
*s
= OMAP_INTC(dev
);
390 error_setg(errp
, "omap-intc: clk not connected");
394 static Property omap_intc_properties
[] = {
395 DEFINE_PROP_UINT32("size", struct omap_intr_handler_s
, size
, 0x100),
396 DEFINE_PROP_PTR("clk", struct omap_intr_handler_s
, iclk
),
397 DEFINE_PROP_END_OF_LIST(),
400 static void omap_intc_class_init(ObjectClass
*klass
, void *data
)
402 DeviceClass
*dc
= DEVICE_CLASS(klass
);
404 dc
->reset
= omap_inth_reset
;
405 dc
->props
= omap_intc_properties
;
406 /* Reason: pointer property "clk" */
407 dc
->user_creatable
= false;
408 dc
->realize
= omap_intc_realize
;
411 static const TypeInfo omap_intc_info
= {
413 .parent
= TYPE_OMAP_INTC
,
414 .instance_init
= omap_intc_init
,
415 .class_init
= omap_intc_class_init
,
418 static uint64_t omap2_inth_read(void *opaque
, hwaddr addr
,
421 struct omap_intr_handler_s
*s
= (struct omap_intr_handler_s
*) opaque
;
423 int bank_no
, line_no
;
424 struct omap_intr_handler_bank_s
*bank
= NULL
;
426 if ((offset
& 0xf80) == 0x80) {
427 bank_no
= (offset
& 0x60) >> 5;
428 if (bank_no
< s
->nbanks
) {
430 bank
= &s
->bank
[bank_no
];
438 case 0x00: /* INTC_REVISION */
441 case 0x10: /* INTC_SYSCONFIG */
442 return (s
->autoidle
>> 2) & 1;
444 case 0x14: /* INTC_SYSSTATUS */
445 return 1; /* RESETDONE */
447 case 0x40: /* INTC_SIR_IRQ */
448 return s
->sir_intr
[0];
450 case 0x44: /* INTC_SIR_FIQ */
451 return s
->sir_intr
[1];
453 case 0x48: /* INTC_CONTROL */
454 return (!s
->mask
) << 2; /* GLOBALMASK */
456 case 0x4c: /* INTC_PROTECTION */
459 case 0x50: /* INTC_IDLE */
460 return s
->autoidle
& 3;
462 /* Per-bank registers */
463 case 0x80: /* INTC_ITR */
466 case 0x84: /* INTC_MIR */
469 case 0x88: /* INTC_MIR_CLEAR */
470 case 0x8c: /* INTC_MIR_SET */
473 case 0x90: /* INTC_ISR_SET */
476 case 0x94: /* INTC_ISR_CLEAR */
479 case 0x98: /* INTC_PENDING_IRQ */
480 return bank
->irqs
& ~bank
->mask
& ~bank
->fiq
;
482 case 0x9c: /* INTC_PENDING_FIQ */
483 return bank
->irqs
& ~bank
->mask
& bank
->fiq
;
485 /* Per-line registers */
486 case 0x100 ... 0x300: /* INTC_ILR */
487 bank_no
= (offset
- 0x100) >> 7;
488 if (bank_no
> s
->nbanks
)
490 bank
= &s
->bank
[bank_no
];
491 line_no
= (offset
& 0x7f) >> 2;
492 return (bank
->priority
[line_no
] << 2) |
493 ((bank
->fiq
>> line_no
) & 1);
499 static void omap2_inth_write(void *opaque
, hwaddr addr
,
500 uint64_t value
, unsigned size
)
502 struct omap_intr_handler_s
*s
= (struct omap_intr_handler_s
*) opaque
;
504 int bank_no
, line_no
;
505 struct omap_intr_handler_bank_s
*bank
= NULL
;
507 if ((offset
& 0xf80) == 0x80) {
508 bank_no
= (offset
& 0x60) >> 5;
509 if (bank_no
< s
->nbanks
) {
511 bank
= &s
->bank
[bank_no
];
519 case 0x10: /* INTC_SYSCONFIG */
521 s
->autoidle
|= (value
& 1) << 2;
522 if (value
& 2) { /* SOFTRESET */
523 omap_inth_reset(DEVICE(s
));
527 case 0x48: /* INTC_CONTROL */
528 s
->mask
= (value
& 4) ? 0 : ~0; /* GLOBALMASK */
529 if (value
& 2) { /* NEWFIQAGR */
530 qemu_set_irq(s
->parent_intr
[1], 0);
532 omap_inth_update(s
, 1);
534 if (value
& 1) { /* NEWIRQAGR */
535 qemu_set_irq(s
->parent_intr
[0], 0);
537 omap_inth_update(s
, 0);
541 case 0x4c: /* INTC_PROTECTION */
542 /* TODO: Make a bitmap (or sizeof(char)map) of access privileges
543 * for every register, see Chapter 3 and 4 for privileged mode. */
545 fprintf(stderr
, "%s: protection mode enable attempt\n",
549 case 0x50: /* INTC_IDLE */
551 s
->autoidle
|= value
& 3;
554 /* Per-bank registers */
555 case 0x84: /* INTC_MIR */
557 omap_inth_update(s
, 0);
558 omap_inth_update(s
, 1);
561 case 0x88: /* INTC_MIR_CLEAR */
562 bank
->mask
&= ~value
;
563 omap_inth_update(s
, 0);
564 omap_inth_update(s
, 1);
567 case 0x8c: /* INTC_MIR_SET */
571 case 0x90: /* INTC_ISR_SET */
572 bank
->irqs
|= bank
->swi
|= value
;
573 omap_inth_update(s
, 0);
574 omap_inth_update(s
, 1);
577 case 0x94: /* INTC_ISR_CLEAR */
579 bank
->irqs
= bank
->swi
& bank
->inputs
;
582 /* Per-line registers */
583 case 0x100 ... 0x300: /* INTC_ILR */
584 bank_no
= (offset
- 0x100) >> 7;
585 if (bank_no
> s
->nbanks
)
587 bank
= &s
->bank
[bank_no
];
588 line_no
= (offset
& 0x7f) >> 2;
589 bank
->priority
[line_no
] = (value
>> 2) & 0x3f;
590 bank
->fiq
&= ~(1 << line_no
);
591 bank
->fiq
|= (value
& 1) << line_no
;
594 case 0x00: /* INTC_REVISION */
595 case 0x14: /* INTC_SYSSTATUS */
596 case 0x40: /* INTC_SIR_IRQ */
597 case 0x44: /* INTC_SIR_FIQ */
598 case 0x80: /* INTC_ITR */
599 case 0x98: /* INTC_PENDING_IRQ */
600 case 0x9c: /* INTC_PENDING_FIQ */
607 static const MemoryRegionOps omap2_inth_mem_ops
= {
608 .read
= omap2_inth_read
,
609 .write
= omap2_inth_write
,
610 .endianness
= DEVICE_NATIVE_ENDIAN
,
612 .min_access_size
= 4,
613 .max_access_size
= 4,
617 static void omap2_intc_init(Object
*obj
)
619 DeviceState
*dev
= DEVICE(obj
);
620 struct omap_intr_handler_s
*s
= OMAP_INTC(obj
);
621 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
625 sysbus_init_irq(sbd
, &s
->parent_intr
[0]);
626 sysbus_init_irq(sbd
, &s
->parent_intr
[1]);
627 qdev_init_gpio_in(dev
, omap_set_intr_noedge
, s
->nbanks
* 32);
628 memory_region_init_io(&s
->mmio
, obj
, &omap2_inth_mem_ops
, s
,
629 "omap2-intc", 0x1000);
630 sysbus_init_mmio(sbd
, &s
->mmio
);
633 static void omap2_intc_realize(DeviceState
*dev
, Error
**errp
)
635 struct omap_intr_handler_s
*s
= OMAP_INTC(dev
);
638 error_setg(errp
, "omap2-intc: iclk not connected");
642 error_setg(errp
, "omap2-intc: fclk not connected");
647 static Property omap2_intc_properties
[] = {
648 DEFINE_PROP_UINT8("revision", struct omap_intr_handler_s
,
650 DEFINE_PROP_PTR("iclk", struct omap_intr_handler_s
, iclk
),
651 DEFINE_PROP_PTR("fclk", struct omap_intr_handler_s
, fclk
),
652 DEFINE_PROP_END_OF_LIST(),
655 static void omap2_intc_class_init(ObjectClass
*klass
, void *data
)
657 DeviceClass
*dc
= DEVICE_CLASS(klass
);
659 dc
->reset
= omap_inth_reset
;
660 dc
->props
= omap2_intc_properties
;
661 /* Reason: pointer property "iclk", "fclk" */
662 dc
->user_creatable
= false;
663 dc
->realize
= omap2_intc_realize
;
666 static const TypeInfo omap2_intc_info
= {
667 .name
= "omap2-intc",
668 .parent
= TYPE_OMAP_INTC
,
669 .instance_init
= omap2_intc_init
,
670 .class_init
= omap2_intc_class_init
,
673 static const TypeInfo omap_intc_type_info
= {
674 .name
= TYPE_OMAP_INTC
,
675 .parent
= TYPE_SYS_BUS_DEVICE
,
676 .instance_size
= sizeof(struct omap_intr_handler_s
),
680 static void omap_intc_register_types(void)
682 type_register_static(&omap_intc_type_info
);
683 type_register_static(&omap_intc_info
);
684 type_register_static(&omap2_intc_info
);
687 type_init(omap_intc_register_types
)