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hw/riscv: opentitan: Fixup resetvec
[qemu/ar7.git]
/
include
/
crypto
/
sm4.h
blob
9bd3ebc62e850669d8558fa963ea7960a3d1e104
1
#ifndef QEMU_SM4_H
2
#define QEMU_SM4_H
3
4
extern
const uint8_t
sm4_sbox
[
256
];
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#endif