4 * Copyright (c) 2009 Ulrich Hecht
5 * Copyright (c) 2010 Alexander Graf
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 /* #define DEBUG_INLINE_BRANCHES */
22 #define S390X_DEBUG_DISAS
23 /* #define S390X_DEBUG_DISAS_VERBOSE */
25 #ifdef S390X_DEBUG_DISAS_VERBOSE
26 # define LOG_DISAS(...) qemu_log(__VA_ARGS__)
28 # define LOG_DISAS(...) do { } while (0)
31 #include "qemu/osdep.h"
33 #include "s390x-internal.h"
34 #include "disas/disas.h"
35 #include "exec/exec-all.h"
36 #include "tcg/tcg-op.h"
37 #include "tcg/tcg-op-gvec.h"
39 #include "qemu/host-utils.h"
40 #include "exec/cpu_ldst.h"
41 #include "exec/helper-proto.h"
42 #include "exec/helper-gen.h"
44 #include "exec/translator.h"
46 #include "qemu/atomic128.h"
48 #define HELPER_H "helper.h"
49 #include "exec/helper-info.c.inc"
53 /* Information that (most) every instruction needs to manipulate. */
54 typedef struct DisasContext DisasContext
;
55 typedef struct DisasInsn DisasInsn
;
56 typedef struct DisasFields DisasFields
;
59 * Define a structure to hold the decoded fields. We'll store each inside
60 * an array indexed by an enum. In order to conserve memory, we'll arrange
61 * for fields that do not exist at the same time to overlap, thus the "C"
62 * for compact. For checking purposes there is an "O" for original index
63 * as well that will be applied to availability bitmaps.
66 enum DisasFieldIndexO
{
95 enum DisasFieldIndexC
{
136 unsigned presentC
:16;
137 unsigned int presentO
;
141 struct DisasContext
{
142 DisasContextBase base
;
143 const DisasInsn
*insn
;
148 * During translate_one(), pc_tmp is used to determine the instruction
149 * to be executed after base.pc_next - e.g. next sequential instruction
150 * or a branch target.
155 bool exit_to_mainloop
;
158 /* Information carried about a condition to be evaluated. */
163 struct { TCGv_i64 a
, b
; } s64
;
164 struct { TCGv_i32 a
, b
; } s32
;
168 #ifdef DEBUG_INLINE_BRANCHES
169 static uint64_t inline_branch_hit
[CC_OP_MAX
];
170 static uint64_t inline_branch_miss
[CC_OP_MAX
];
173 static void pc_to_link_info(TCGv_i64 out
, DisasContext
*s
, uint64_t pc
)
175 if (s
->base
.tb
->flags
& FLAG_MASK_32
) {
176 if (s
->base
.tb
->flags
& FLAG_MASK_64
) {
177 tcg_gen_movi_i64(out
, pc
);
182 assert(!(s
->base
.tb
->flags
& FLAG_MASK_64
));
183 tcg_gen_deposit_i64(out
, out
, tcg_constant_i64(pc
), 0, 32);
186 static TCGv_i64 psw_addr
;
187 static TCGv_i64 psw_mask
;
188 static TCGv_i64 gbea
;
190 static TCGv_i32 cc_op
;
191 static TCGv_i64 cc_src
;
192 static TCGv_i64 cc_dst
;
193 static TCGv_i64 cc_vr
;
195 static char cpu_reg_names
[16][4];
196 static TCGv_i64 regs
[16];
198 void s390x_translate_init(void)
202 psw_addr
= tcg_global_mem_new_i64(cpu_env
,
203 offsetof(CPUS390XState
, psw
.addr
),
205 psw_mask
= tcg_global_mem_new_i64(cpu_env
,
206 offsetof(CPUS390XState
, psw
.mask
),
208 gbea
= tcg_global_mem_new_i64(cpu_env
,
209 offsetof(CPUS390XState
, gbea
),
212 cc_op
= tcg_global_mem_new_i32(cpu_env
, offsetof(CPUS390XState
, cc_op
),
214 cc_src
= tcg_global_mem_new_i64(cpu_env
, offsetof(CPUS390XState
, cc_src
),
216 cc_dst
= tcg_global_mem_new_i64(cpu_env
, offsetof(CPUS390XState
, cc_dst
),
218 cc_vr
= tcg_global_mem_new_i64(cpu_env
, offsetof(CPUS390XState
, cc_vr
),
221 for (i
= 0; i
< 16; i
++) {
222 snprintf(cpu_reg_names
[i
], sizeof(cpu_reg_names
[0]), "r%d", i
);
223 regs
[i
] = tcg_global_mem_new(cpu_env
,
224 offsetof(CPUS390XState
, regs
[i
]),
229 static inline int vec_full_reg_offset(uint8_t reg
)
232 return offsetof(CPUS390XState
, vregs
[reg
][0]);
235 static inline int vec_reg_offset(uint8_t reg
, uint8_t enr
, MemOp es
)
237 /* Convert element size (es) - e.g. MO_8 - to bytes */
238 const uint8_t bytes
= 1 << es
;
239 int offs
= enr
* bytes
;
242 * vregs[n][0] is the lowest 8 byte and vregs[n][1] the highest 8 byte
243 * of the 16 byte vector, on both, little and big endian systems.
245 * Big Endian (target/possible host)
246 * B: [ 0][ 1][ 2][ 3][ 4][ 5][ 6][ 7] - [ 8][ 9][10][11][12][13][14][15]
247 * HW: [ 0][ 1][ 2][ 3] - [ 4][ 5][ 6][ 7]
248 * W: [ 0][ 1] - [ 2][ 3]
251 * Little Endian (possible host)
252 * B: [ 7][ 6][ 5][ 4][ 3][ 2][ 1][ 0] - [15][14][13][12][11][10][ 9][ 8]
253 * HW: [ 3][ 2][ 1][ 0] - [ 7][ 6][ 5][ 4]
254 * W: [ 1][ 0] - [ 3][ 2]
257 * For 16 byte elements, the two 8 byte halves will not form a host
258 * int128 if the host is little endian, since they're in the wrong order.
259 * Some operations (e.g. xor) do not care. For operations like addition,
260 * the two 8 byte elements have to be loaded separately. Let's force all
261 * 16 byte operations to handle it in a special way.
263 g_assert(es
<= MO_64
);
267 return offs
+ vec_full_reg_offset(reg
);
270 static inline int freg64_offset(uint8_t reg
)
273 return vec_reg_offset(reg
, 0, MO_64
);
276 static inline int freg32_offset(uint8_t reg
)
279 return vec_reg_offset(reg
, 0, MO_32
);
282 static TCGv_i64
load_reg(int reg
)
284 TCGv_i64 r
= tcg_temp_new_i64();
285 tcg_gen_mov_i64(r
, regs
[reg
]);
289 static TCGv_i64
load_freg(int reg
)
291 TCGv_i64 r
= tcg_temp_new_i64();
293 tcg_gen_ld_i64(r
, cpu_env
, freg64_offset(reg
));
297 static TCGv_i64
load_freg32_i64(int reg
)
299 TCGv_i64 r
= tcg_temp_new_i64();
301 tcg_gen_ld32u_i64(r
, cpu_env
, freg32_offset(reg
));
305 static TCGv_i128
load_freg_128(int reg
)
307 TCGv_i64 h
= load_freg(reg
);
308 TCGv_i64 l
= load_freg(reg
+ 2);
309 TCGv_i128 r
= tcg_temp_new_i128();
311 tcg_gen_concat_i64_i128(r
, l
, h
);
315 static void store_reg(int reg
, TCGv_i64 v
)
317 tcg_gen_mov_i64(regs
[reg
], v
);
320 static void store_freg(int reg
, TCGv_i64 v
)
322 tcg_gen_st_i64(v
, cpu_env
, freg64_offset(reg
));
325 static void store_reg32_i64(int reg
, TCGv_i64 v
)
327 /* 32 bit register writes keep the upper half */
328 tcg_gen_deposit_i64(regs
[reg
], regs
[reg
], v
, 0, 32);
331 static void store_reg32h_i64(int reg
, TCGv_i64 v
)
333 tcg_gen_deposit_i64(regs
[reg
], regs
[reg
], v
, 32, 32);
336 static void store_freg32_i64(int reg
, TCGv_i64 v
)
338 tcg_gen_st32_i64(v
, cpu_env
, freg32_offset(reg
));
341 static void update_psw_addr(DisasContext
*s
)
344 tcg_gen_movi_i64(psw_addr
, s
->base
.pc_next
);
347 static void per_branch(DisasContext
*s
, bool to_next
)
349 #ifndef CONFIG_USER_ONLY
350 tcg_gen_movi_i64(gbea
, s
->base
.pc_next
);
352 if (s
->base
.tb
->flags
& FLAG_MASK_PER
) {
353 TCGv_i64 next_pc
= to_next
? tcg_constant_i64(s
->pc_tmp
) : psw_addr
;
354 gen_helper_per_branch(cpu_env
, gbea
, next_pc
);
359 static void per_branch_cond(DisasContext
*s
, TCGCond cond
,
360 TCGv_i64 arg1
, TCGv_i64 arg2
)
362 #ifndef CONFIG_USER_ONLY
363 if (s
->base
.tb
->flags
& FLAG_MASK_PER
) {
364 TCGLabel
*lab
= gen_new_label();
365 tcg_gen_brcond_i64(tcg_invert_cond(cond
), arg1
, arg2
, lab
);
367 tcg_gen_movi_i64(gbea
, s
->base
.pc_next
);
368 gen_helper_per_branch(cpu_env
, gbea
, psw_addr
);
372 TCGv_i64 pc
= tcg_constant_i64(s
->base
.pc_next
);
373 tcg_gen_movcond_i64(cond
, gbea
, arg1
, arg2
, gbea
, pc
);
378 static void per_breaking_event(DisasContext
*s
)
380 tcg_gen_movi_i64(gbea
, s
->base
.pc_next
);
383 static void update_cc_op(DisasContext
*s
)
385 if (s
->cc_op
!= CC_OP_DYNAMIC
&& s
->cc_op
!= CC_OP_STATIC
) {
386 tcg_gen_movi_i32(cc_op
, s
->cc_op
);
390 static inline uint64_t ld_code2(CPUS390XState
*env
, DisasContext
*s
,
393 return (uint64_t)translator_lduw(env
, &s
->base
, pc
);
396 static inline uint64_t ld_code4(CPUS390XState
*env
, DisasContext
*s
,
399 return (uint64_t)(uint32_t)translator_ldl(env
, &s
->base
, pc
);
402 static int get_mem_index(DisasContext
*s
)
404 #ifdef CONFIG_USER_ONLY
407 if (!(s
->base
.tb
->flags
& FLAG_MASK_DAT
)) {
411 switch (s
->base
.tb
->flags
& FLAG_MASK_ASC
) {
412 case PSW_ASC_PRIMARY
>> FLAG_MASK_PSW_SHIFT
:
413 return MMU_PRIMARY_IDX
;
414 case PSW_ASC_SECONDARY
>> FLAG_MASK_PSW_SHIFT
:
415 return MMU_SECONDARY_IDX
;
416 case PSW_ASC_HOME
>> FLAG_MASK_PSW_SHIFT
:
419 g_assert_not_reached();
425 static void gen_exception(int excp
)
427 gen_helper_exception(cpu_env
, tcg_constant_i32(excp
));
430 static void gen_program_exception(DisasContext
*s
, int code
)
432 /* Remember what pgm exception this was. */
433 tcg_gen_st_i32(tcg_constant_i32(code
), cpu_env
,
434 offsetof(CPUS390XState
, int_pgm_code
));
436 tcg_gen_st_i32(tcg_constant_i32(s
->ilen
), cpu_env
,
437 offsetof(CPUS390XState
, int_pgm_ilen
));
445 /* Trigger exception. */
446 gen_exception(EXCP_PGM
);
449 static inline void gen_illegal_opcode(DisasContext
*s
)
451 gen_program_exception(s
, PGM_OPERATION
);
454 static inline void gen_data_exception(uint8_t dxc
)
456 gen_helper_data_exception(cpu_env
, tcg_constant_i32(dxc
));
459 static inline void gen_trap(DisasContext
*s
)
461 /* Set DXC to 0xff */
462 gen_data_exception(0xff);
465 static void gen_addi_and_wrap_i64(DisasContext
*s
, TCGv_i64 dst
, TCGv_i64 src
,
468 tcg_gen_addi_i64(dst
, src
, imm
);
469 if (!(s
->base
.tb
->flags
& FLAG_MASK_64
)) {
470 if (s
->base
.tb
->flags
& FLAG_MASK_32
) {
471 tcg_gen_andi_i64(dst
, dst
, 0x7fffffff);
473 tcg_gen_andi_i64(dst
, dst
, 0x00ffffff);
478 static TCGv_i64
get_address(DisasContext
*s
, int x2
, int b2
, int d2
)
480 TCGv_i64 tmp
= tcg_temp_new_i64();
483 * Note that d2 is limited to 20 bits, signed. If we crop negative
484 * displacements early we create larger immediate addends.
487 tcg_gen_add_i64(tmp
, regs
[b2
], regs
[x2
]);
488 gen_addi_and_wrap_i64(s
, tmp
, tmp
, d2
);
490 gen_addi_and_wrap_i64(s
, tmp
, regs
[b2
], d2
);
492 gen_addi_and_wrap_i64(s
, tmp
, regs
[x2
], d2
);
493 } else if (!(s
->base
.tb
->flags
& FLAG_MASK_64
)) {
494 if (s
->base
.tb
->flags
& FLAG_MASK_32
) {
495 tcg_gen_movi_i64(tmp
, d2
& 0x7fffffff);
497 tcg_gen_movi_i64(tmp
, d2
& 0x00ffffff);
500 tcg_gen_movi_i64(tmp
, d2
);
506 static inline bool live_cc_data(DisasContext
*s
)
508 return (s
->cc_op
!= CC_OP_DYNAMIC
509 && s
->cc_op
!= CC_OP_STATIC
513 static inline void gen_op_movi_cc(DisasContext
*s
, uint32_t val
)
515 if (live_cc_data(s
)) {
516 tcg_gen_discard_i64(cc_src
);
517 tcg_gen_discard_i64(cc_dst
);
518 tcg_gen_discard_i64(cc_vr
);
520 s
->cc_op
= CC_OP_CONST0
+ val
;
523 static void gen_op_update1_cc_i64(DisasContext
*s
, enum cc_op op
, TCGv_i64 dst
)
525 if (live_cc_data(s
)) {
526 tcg_gen_discard_i64(cc_src
);
527 tcg_gen_discard_i64(cc_vr
);
529 tcg_gen_mov_i64(cc_dst
, dst
);
533 static void gen_op_update2_cc_i64(DisasContext
*s
, enum cc_op op
, TCGv_i64 src
,
536 if (live_cc_data(s
)) {
537 tcg_gen_discard_i64(cc_vr
);
539 tcg_gen_mov_i64(cc_src
, src
);
540 tcg_gen_mov_i64(cc_dst
, dst
);
544 static void gen_op_update3_cc_i64(DisasContext
*s
, enum cc_op op
, TCGv_i64 src
,
545 TCGv_i64 dst
, TCGv_i64 vr
)
547 tcg_gen_mov_i64(cc_src
, src
);
548 tcg_gen_mov_i64(cc_dst
, dst
);
549 tcg_gen_mov_i64(cc_vr
, vr
);
553 static void set_cc_nz_u64(DisasContext
*s
, TCGv_i64 val
)
555 gen_op_update1_cc_i64(s
, CC_OP_NZ
, val
);
558 /* CC value is in env->cc_op */
559 static void set_cc_static(DisasContext
*s
)
561 if (live_cc_data(s
)) {
562 tcg_gen_discard_i64(cc_src
);
563 tcg_gen_discard_i64(cc_dst
);
564 tcg_gen_discard_i64(cc_vr
);
566 s
->cc_op
= CC_OP_STATIC
;
569 /* calculates cc into cc_op */
570 static void gen_op_calc_cc(DisasContext
*s
)
572 TCGv_i32 local_cc_op
= NULL
;
573 TCGv_i64 dummy
= NULL
;
577 dummy
= tcg_constant_i64(0);
583 local_cc_op
= tcg_constant_i32(s
->cc_op
);
599 /* s->cc_op is the cc value */
600 tcg_gen_movi_i32(cc_op
, s
->cc_op
- CC_OP_CONST0
);
603 /* env->cc_op already is the cc value */
606 tcg_gen_setcondi_i64(TCG_COND_NE
, cc_dst
, cc_dst
, 0);
607 tcg_gen_extrl_i64_i32(cc_op
, cc_dst
);
623 gen_helper_calc_cc(cc_op
, cpu_env
, local_cc_op
, dummy
, cc_dst
, dummy
);
629 case CC_OP_LTUGTU_32
:
630 case CC_OP_LTUGTU_64
:
639 gen_helper_calc_cc(cc_op
, cpu_env
, local_cc_op
, cc_src
, cc_dst
, dummy
);
646 gen_helper_calc_cc(cc_op
, cpu_env
, local_cc_op
, cc_src
, cc_dst
, cc_vr
);
649 /* unknown operation - assume 3 arguments and cc_op in env */
650 gen_helper_calc_cc(cc_op
, cpu_env
, cc_op
, cc_src
, cc_dst
, cc_vr
);
653 g_assert_not_reached();
656 /* We now have cc in cc_op as constant */
660 static bool use_goto_tb(DisasContext
*s
, uint64_t dest
)
662 if (unlikely(s
->base
.tb
->flags
& FLAG_MASK_PER
)) {
665 return translator_use_goto_tb(&s
->base
, dest
);
668 static void account_noninline_branch(DisasContext
*s
, int cc_op
)
670 #ifdef DEBUG_INLINE_BRANCHES
671 inline_branch_miss
[cc_op
]++;
675 static void account_inline_branch(DisasContext
*s
, int cc_op
)
677 #ifdef DEBUG_INLINE_BRANCHES
678 inline_branch_hit
[cc_op
]++;
682 /* Table of mask values to comparison codes, given a comparison as input.
683 For such, CC=3 should not be possible. */
684 static const TCGCond ltgt_cond
[16] = {
685 TCG_COND_NEVER
, TCG_COND_NEVER
, /* | | | x */
686 TCG_COND_GT
, TCG_COND_GT
, /* | | GT | x */
687 TCG_COND_LT
, TCG_COND_LT
, /* | LT | | x */
688 TCG_COND_NE
, TCG_COND_NE
, /* | LT | GT | x */
689 TCG_COND_EQ
, TCG_COND_EQ
, /* EQ | | | x */
690 TCG_COND_GE
, TCG_COND_GE
, /* EQ | | GT | x */
691 TCG_COND_LE
, TCG_COND_LE
, /* EQ | LT | | x */
692 TCG_COND_ALWAYS
, TCG_COND_ALWAYS
, /* EQ | LT | GT | x */
695 /* Table of mask values to comparison codes, given a logic op as input.
696 For such, only CC=0 and CC=1 should be possible. */
697 static const TCGCond nz_cond
[16] = {
698 TCG_COND_NEVER
, TCG_COND_NEVER
, /* | | x | x */
699 TCG_COND_NEVER
, TCG_COND_NEVER
,
700 TCG_COND_NE
, TCG_COND_NE
, /* | NE | x | x */
701 TCG_COND_NE
, TCG_COND_NE
,
702 TCG_COND_EQ
, TCG_COND_EQ
, /* EQ | | x | x */
703 TCG_COND_EQ
, TCG_COND_EQ
,
704 TCG_COND_ALWAYS
, TCG_COND_ALWAYS
, /* EQ | NE | x | x */
705 TCG_COND_ALWAYS
, TCG_COND_ALWAYS
,
708 /* Interpret MASK in terms of S->CC_OP, and fill in C with all the
709 details required to generate a TCG comparison. */
710 static void disas_jcc(DisasContext
*s
, DisasCompare
*c
, uint32_t mask
)
713 enum cc_op old_cc_op
= s
->cc_op
;
715 if (mask
== 15 || mask
== 0) {
716 c
->cond
= (mask
? TCG_COND_ALWAYS
: TCG_COND_NEVER
);
723 /* Find the TCG condition for the mask + cc op. */
729 cond
= ltgt_cond
[mask
];
730 if (cond
== TCG_COND_NEVER
) {
733 account_inline_branch(s
, old_cc_op
);
736 case CC_OP_LTUGTU_32
:
737 case CC_OP_LTUGTU_64
:
738 cond
= tcg_unsigned_cond(ltgt_cond
[mask
]);
739 if (cond
== TCG_COND_NEVER
) {
742 account_inline_branch(s
, old_cc_op
);
746 cond
= nz_cond
[mask
];
747 if (cond
== TCG_COND_NEVER
) {
750 account_inline_branch(s
, old_cc_op
);
765 account_inline_branch(s
, old_cc_op
);
780 account_inline_branch(s
, old_cc_op
);
784 switch (mask
& 0xa) {
785 case 8: /* src == 0 -> no one bit found */
788 case 2: /* src != 0 -> one bit found */
794 account_inline_branch(s
, old_cc_op
);
800 case 8 | 2: /* result == 0 */
803 case 4 | 1: /* result != 0 */
806 case 8 | 4: /* !carry (borrow) */
807 cond
= old_cc_op
== CC_OP_ADDU
? TCG_COND_EQ
: TCG_COND_NE
;
809 case 2 | 1: /* carry (!borrow) */
810 cond
= old_cc_op
== CC_OP_ADDU
? TCG_COND_NE
: TCG_COND_EQ
;
815 account_inline_branch(s
, old_cc_op
);
820 /* Calculate cc value. */
825 /* Jump based on CC. We'll load up the real cond below;
826 the assignment here merely avoids a compiler warning. */
827 account_noninline_branch(s
, old_cc_op
);
828 old_cc_op
= CC_OP_STATIC
;
829 cond
= TCG_COND_NEVER
;
833 /* Load up the arguments of the comparison. */
838 c
->u
.s32
.a
= tcg_temp_new_i32();
839 tcg_gen_extrl_i64_i32(c
->u
.s32
.a
, cc_dst
);
840 c
->u
.s32
.b
= tcg_constant_i32(0);
843 case CC_OP_LTUGTU_32
:
845 c
->u
.s32
.a
= tcg_temp_new_i32();
846 tcg_gen_extrl_i64_i32(c
->u
.s32
.a
, cc_src
);
847 c
->u
.s32
.b
= tcg_temp_new_i32();
848 tcg_gen_extrl_i64_i32(c
->u
.s32
.b
, cc_dst
);
855 c
->u
.s64
.b
= tcg_constant_i64(0);
858 case CC_OP_LTUGTU_64
:
866 c
->u
.s64
.a
= tcg_temp_new_i64();
867 c
->u
.s64
.b
= tcg_constant_i64(0);
868 tcg_gen_and_i64(c
->u
.s64
.a
, cc_src
, cc_dst
);
874 c
->u
.s64
.b
= tcg_constant_i64(0);
877 case 4 | 1: /* result */
881 case 2 | 1: /* carry */
885 g_assert_not_reached();
893 case 0x8 | 0x4 | 0x2: /* cc != 3 */
895 c
->u
.s32
.b
= tcg_constant_i32(3);
897 case 0x8 | 0x4 | 0x1: /* cc != 2 */
899 c
->u
.s32
.b
= tcg_constant_i32(2);
901 case 0x8 | 0x2 | 0x1: /* cc != 1 */
903 c
->u
.s32
.b
= tcg_constant_i32(1);
905 case 0x8 | 0x2: /* cc == 0 || cc == 2 => (cc & 1) == 0 */
907 c
->u
.s32
.a
= tcg_temp_new_i32();
908 c
->u
.s32
.b
= tcg_constant_i32(0);
909 tcg_gen_andi_i32(c
->u
.s32
.a
, cc_op
, 1);
911 case 0x8 | 0x4: /* cc < 2 */
913 c
->u
.s32
.b
= tcg_constant_i32(2);
915 case 0x8: /* cc == 0 */
917 c
->u
.s32
.b
= tcg_constant_i32(0);
919 case 0x4 | 0x2 | 0x1: /* cc != 0 */
921 c
->u
.s32
.b
= tcg_constant_i32(0);
923 case 0x4 | 0x1: /* cc == 1 || cc == 3 => (cc & 1) != 0 */
925 c
->u
.s32
.a
= tcg_temp_new_i32();
926 c
->u
.s32
.b
= tcg_constant_i32(0);
927 tcg_gen_andi_i32(c
->u
.s32
.a
, cc_op
, 1);
929 case 0x4: /* cc == 1 */
931 c
->u
.s32
.b
= tcg_constant_i32(1);
933 case 0x2 | 0x1: /* cc > 1 */
935 c
->u
.s32
.b
= tcg_constant_i32(1);
937 case 0x2: /* cc == 2 */
939 c
->u
.s32
.b
= tcg_constant_i32(2);
941 case 0x1: /* cc == 3 */
943 c
->u
.s32
.b
= tcg_constant_i32(3);
946 /* CC is masked by something else: (8 >> cc) & mask. */
948 c
->u
.s32
.a
= tcg_temp_new_i32();
949 c
->u
.s32
.b
= tcg_constant_i32(0);
950 tcg_gen_shr_i32(c
->u
.s32
.a
, tcg_constant_i32(8), cc_op
);
951 tcg_gen_andi_i32(c
->u
.s32
.a
, c
->u
.s32
.a
, mask
);
962 /* ====================================================================== */
963 /* Define the insn format enumeration. */
964 #define F0(N) FMT_##N,
965 #define F1(N, X1) F0(N)
966 #define F2(N, X1, X2) F0(N)
967 #define F3(N, X1, X2, X3) F0(N)
968 #define F4(N, X1, X2, X3, X4) F0(N)
969 #define F5(N, X1, X2, X3, X4, X5) F0(N)
970 #define F6(N, X1, X2, X3, X4, X5, X6) F0(N)
973 #include "insn-format.h.inc"
984 /* This is the way fields are to be accessed out of DisasFields. */
985 #define have_field(S, F) have_field1((S), FLD_O_##F)
986 #define get_field(S, F) get_field1((S), FLD_O_##F, FLD_C_##F)
988 static bool have_field1(const DisasContext
*s
, enum DisasFieldIndexO c
)
990 return (s
->fields
.presentO
>> c
) & 1;
993 static int get_field1(const DisasContext
*s
, enum DisasFieldIndexO o
,
994 enum DisasFieldIndexC c
)
996 assert(have_field1(s
, o
));
997 return s
->fields
.c
[c
];
1000 /* Describe the layout of each field in each format. */
1001 typedef struct DisasField
{
1003 unsigned int size
:8;
1004 unsigned int type
:2;
1005 unsigned int indexC
:6;
1006 enum DisasFieldIndexO indexO
:8;
1009 typedef struct DisasFormatInfo
{
1010 DisasField op
[NUM_C_FIELD
];
1013 #define R(N, B) { B, 4, 0, FLD_C_r##N, FLD_O_r##N }
1014 #define M(N, B) { B, 4, 0, FLD_C_m##N, FLD_O_m##N }
1015 #define V(N, B) { B, 4, 3, FLD_C_v##N, FLD_O_v##N }
1016 #define BD(N, BB, BD) { BB, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1017 { BD, 12, 0, FLD_C_d##N, FLD_O_d##N }
1018 #define BXD(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1019 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
1020 { 20, 12, 0, FLD_C_d##N, FLD_O_d##N }
1021 #define BDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1022 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
1023 #define BXDL(N) { 16, 4, 0, FLD_C_b##N, FLD_O_b##N }, \
1024 { 12, 4, 0, FLD_C_x##N, FLD_O_x##N }, \
1025 { 20, 20, 2, FLD_C_d##N, FLD_O_d##N }
1026 #define I(N, B, S) { B, S, 1, FLD_C_i##N, FLD_O_i##N }
1027 #define L(N, B, S) { B, S, 0, FLD_C_l##N, FLD_O_l##N }
1029 #define F0(N) { { } },
1030 #define F1(N, X1) { { X1 } },
1031 #define F2(N, X1, X2) { { X1, X2 } },
1032 #define F3(N, X1, X2, X3) { { X1, X2, X3 } },
1033 #define F4(N, X1, X2, X3, X4) { { X1, X2, X3, X4 } },
1034 #define F5(N, X1, X2, X3, X4, X5) { { X1, X2, X3, X4, X5 } },
1035 #define F6(N, X1, X2, X3, X4, X5, X6) { { X1, X2, X3, X4, X5, X6 } },
1037 static const DisasFormatInfo format_info
[] = {
1038 #include "insn-format.h.inc"
1058 /* Generally, we'll extract operands into this structures, operate upon
1059 them, and store them back. See the "in1", "in2", "prep", "wout" sets
1060 of routines below for more details. */
1062 TCGv_i64 out
, out2
, in1
, in2
;
1064 TCGv_i128 out_128
, in1_128
, in2_128
;
1067 /* Instructions can place constraints on their operands, raising specification
1068 exceptions if they are violated. To make this easy to automate, each "in1",
1069 "in2", "prep", "wout" helper will have a SPEC_<name> define that equals one
1070 of the following, or 0. To make this easy to document, we'll put the
1071 SPEC_<name> defines next to <name>. */
1073 #define SPEC_r1_even 1
1074 #define SPEC_r2_even 2
1075 #define SPEC_r3_even 4
1076 #define SPEC_r1_f128 8
1077 #define SPEC_r2_f128 16
1079 /* Return values from translate_one, indicating the state of the TB. */
1081 /* We are not using a goto_tb (for whatever reason), but have updated
1082 the PC (for whatever reason), so there's no need to do it again on
1084 #define DISAS_PC_UPDATED DISAS_TARGET_0
1086 /* We have updated the PC and CC values. */
1087 #define DISAS_PC_CC_UPDATED DISAS_TARGET_2
1090 /* Instruction flags */
1091 #define IF_AFP1 0x0001 /* r1 is a fp reg for HFP/FPS instructions */
1092 #define IF_AFP2 0x0002 /* r2 is a fp reg for HFP/FPS instructions */
1093 #define IF_AFP3 0x0004 /* r3 is a fp reg for HFP/FPS instructions */
1094 #define IF_BFP 0x0008 /* binary floating point instruction */
1095 #define IF_DFP 0x0010 /* decimal floating point instruction */
1096 #define IF_PRIV 0x0020 /* privileged instruction */
1097 #define IF_VEC 0x0040 /* vector instruction */
1098 #define IF_IO 0x0080 /* input/output instruction */
1109 /* Pre-process arguments before HELP_OP. */
1110 void (*help_in1
)(DisasContext
*, DisasOps
*);
1111 void (*help_in2
)(DisasContext
*, DisasOps
*);
1112 void (*help_prep
)(DisasContext
*, DisasOps
*);
1115 * Post-process output after HELP_OP.
1116 * Note that these are not called if HELP_OP returns DISAS_NORETURN.
1118 void (*help_wout
)(DisasContext
*, DisasOps
*);
1119 void (*help_cout
)(DisasContext
*, DisasOps
*);
1121 /* Implement the operation itself. */
1122 DisasJumpType (*help_op
)(DisasContext
*, DisasOps
*);
1127 /* ====================================================================== */
1128 /* Miscellaneous helpers, used by several operations. */
1130 static DisasJumpType
help_goto_direct(DisasContext
*s
, uint64_t dest
)
1132 if (dest
== s
->pc_tmp
) {
1133 per_branch(s
, true);
1136 if (use_goto_tb(s
, dest
)) {
1138 per_breaking_event(s
);
1140 tcg_gen_movi_i64(psw_addr
, dest
);
1141 tcg_gen_exit_tb(s
->base
.tb
, 0);
1142 return DISAS_NORETURN
;
1144 tcg_gen_movi_i64(psw_addr
, dest
);
1145 per_branch(s
, false);
1146 return DISAS_PC_UPDATED
;
1150 static DisasJumpType
help_branch(DisasContext
*s
, DisasCompare
*c
,
1151 bool is_imm
, int imm
, TCGv_i64 cdest
)
1154 uint64_t dest
= s
->base
.pc_next
+ (int64_t)imm
* 2;
1157 /* Take care of the special cases first. */
1158 if (c
->cond
== TCG_COND_NEVER
) {
1163 if (dest
== s
->pc_tmp
) {
1164 /* Branch to next. */
1165 per_branch(s
, true);
1169 if (c
->cond
== TCG_COND_ALWAYS
) {
1170 ret
= help_goto_direct(s
, dest
);
1175 /* E.g. bcr %r0 -> no branch. */
1179 if (c
->cond
== TCG_COND_ALWAYS
) {
1180 tcg_gen_mov_i64(psw_addr
, cdest
);
1181 per_branch(s
, false);
1182 ret
= DISAS_PC_UPDATED
;
1187 if (use_goto_tb(s
, s
->pc_tmp
)) {
1188 if (is_imm
&& use_goto_tb(s
, dest
)) {
1189 /* Both exits can use goto_tb. */
1192 lab
= gen_new_label();
1194 tcg_gen_brcond_i64(c
->cond
, c
->u
.s64
.a
, c
->u
.s64
.b
, lab
);
1196 tcg_gen_brcond_i32(c
->cond
, c
->u
.s32
.a
, c
->u
.s32
.b
, lab
);
1199 /* Branch not taken. */
1201 tcg_gen_movi_i64(psw_addr
, s
->pc_tmp
);
1202 tcg_gen_exit_tb(s
->base
.tb
, 0);
1206 per_breaking_event(s
);
1208 tcg_gen_movi_i64(psw_addr
, dest
);
1209 tcg_gen_exit_tb(s
->base
.tb
, 1);
1211 ret
= DISAS_NORETURN
;
1213 /* Fallthru can use goto_tb, but taken branch cannot. */
1214 /* Store taken branch destination before the brcond. This
1215 avoids having to allocate a new local temp to hold it.
1216 We'll overwrite this in the not taken case anyway. */
1218 tcg_gen_mov_i64(psw_addr
, cdest
);
1221 lab
= gen_new_label();
1223 tcg_gen_brcond_i64(c
->cond
, c
->u
.s64
.a
, c
->u
.s64
.b
, lab
);
1225 tcg_gen_brcond_i32(c
->cond
, c
->u
.s32
.a
, c
->u
.s32
.b
, lab
);
1228 /* Branch not taken. */
1231 tcg_gen_movi_i64(psw_addr
, s
->pc_tmp
);
1232 tcg_gen_exit_tb(s
->base
.tb
, 0);
1236 tcg_gen_movi_i64(psw_addr
, dest
);
1238 per_breaking_event(s
);
1239 ret
= DISAS_PC_UPDATED
;
1242 /* Fallthru cannot use goto_tb. This by itself is vanishingly rare.
1243 Most commonly we're single-stepping or some other condition that
1244 disables all use of goto_tb. Just update the PC and exit. */
1246 TCGv_i64 next
= tcg_constant_i64(s
->pc_tmp
);
1248 cdest
= tcg_constant_i64(dest
);
1252 tcg_gen_movcond_i64(c
->cond
, psw_addr
, c
->u
.s64
.a
, c
->u
.s64
.b
,
1254 per_branch_cond(s
, c
->cond
, c
->u
.s64
.a
, c
->u
.s64
.b
);
1256 TCGv_i32 t0
= tcg_temp_new_i32();
1257 TCGv_i64 t1
= tcg_temp_new_i64();
1258 TCGv_i64 z
= tcg_constant_i64(0);
1259 tcg_gen_setcond_i32(c
->cond
, t0
, c
->u
.s32
.a
, c
->u
.s32
.b
);
1260 tcg_gen_extu_i32_i64(t1
, t0
);
1261 tcg_gen_movcond_i64(TCG_COND_NE
, psw_addr
, t1
, z
, cdest
, next
);
1262 per_branch_cond(s
, TCG_COND_NE
, t1
, z
);
1265 ret
= DISAS_PC_UPDATED
;
1272 /* ====================================================================== */
1273 /* The operations. These perform the bulk of the work for any insn,
1274 usually after the operands have been loaded and output initialized. */
1276 static DisasJumpType
op_abs(DisasContext
*s
, DisasOps
*o
)
1278 tcg_gen_abs_i64(o
->out
, o
->in2
);
1282 static DisasJumpType
op_absf32(DisasContext
*s
, DisasOps
*o
)
1284 tcg_gen_andi_i64(o
->out
, o
->in2
, 0x7fffffffull
);
1288 static DisasJumpType
op_absf64(DisasContext
*s
, DisasOps
*o
)
1290 tcg_gen_andi_i64(o
->out
, o
->in2
, 0x7fffffffffffffffull
);
1294 static DisasJumpType
op_absf128(DisasContext
*s
, DisasOps
*o
)
1296 tcg_gen_andi_i64(o
->out
, o
->in1
, 0x7fffffffffffffffull
);
1297 tcg_gen_mov_i64(o
->out2
, o
->in2
);
1301 static DisasJumpType
op_add(DisasContext
*s
, DisasOps
*o
)
1303 tcg_gen_add_i64(o
->out
, o
->in1
, o
->in2
);
1307 static DisasJumpType
op_addu64(DisasContext
*s
, DisasOps
*o
)
1309 tcg_gen_movi_i64(cc_src
, 0);
1310 tcg_gen_add2_i64(o
->out
, cc_src
, o
->in1
, cc_src
, o
->in2
, cc_src
);
1314 /* Compute carry into cc_src. */
1315 static void compute_carry(DisasContext
*s
)
1319 /* The carry value is already in cc_src (1,0). */
1322 tcg_gen_addi_i64(cc_src
, cc_src
, 1);
1328 /* The carry flag is the msb of CC; compute into cc_src. */
1329 tcg_gen_extu_i32_i64(cc_src
, cc_op
);
1330 tcg_gen_shri_i64(cc_src
, cc_src
, 1);
1335 static DisasJumpType
op_addc32(DisasContext
*s
, DisasOps
*o
)
1338 tcg_gen_add_i64(o
->out
, o
->in1
, o
->in2
);
1339 tcg_gen_add_i64(o
->out
, o
->out
, cc_src
);
1343 static DisasJumpType
op_addc64(DisasContext
*s
, DisasOps
*o
)
1347 TCGv_i64 zero
= tcg_constant_i64(0);
1348 tcg_gen_add2_i64(o
->out
, cc_src
, o
->in1
, zero
, cc_src
, zero
);
1349 tcg_gen_add2_i64(o
->out
, cc_src
, o
->out
, cc_src
, o
->in2
, zero
);
1354 static DisasJumpType
op_asi(DisasContext
*s
, DisasOps
*o
)
1356 bool non_atomic
= !s390_has_feat(S390_FEAT_STFLE_45
);
1358 o
->in1
= tcg_temp_new_i64();
1360 tcg_gen_qemu_ld_tl(o
->in1
, o
->addr1
, get_mem_index(s
), s
->insn
->data
);
1362 /* Perform the atomic addition in memory. */
1363 tcg_gen_atomic_fetch_add_i64(o
->in1
, o
->addr1
, o
->in2
, get_mem_index(s
),
1367 /* Recompute also for atomic case: needed for setting CC. */
1368 tcg_gen_add_i64(o
->out
, o
->in1
, o
->in2
);
1371 tcg_gen_qemu_st_tl(o
->out
, o
->addr1
, get_mem_index(s
), s
->insn
->data
);
1376 static DisasJumpType
op_asiu64(DisasContext
*s
, DisasOps
*o
)
1378 bool non_atomic
= !s390_has_feat(S390_FEAT_STFLE_45
);
1380 o
->in1
= tcg_temp_new_i64();
1382 tcg_gen_qemu_ld_tl(o
->in1
, o
->addr1
, get_mem_index(s
), s
->insn
->data
);
1384 /* Perform the atomic addition in memory. */
1385 tcg_gen_atomic_fetch_add_i64(o
->in1
, o
->addr1
, o
->in2
, get_mem_index(s
),
1389 /* Recompute also for atomic case: needed for setting CC. */
1390 tcg_gen_movi_i64(cc_src
, 0);
1391 tcg_gen_add2_i64(o
->out
, cc_src
, o
->in1
, cc_src
, o
->in2
, cc_src
);
1394 tcg_gen_qemu_st_tl(o
->out
, o
->addr1
, get_mem_index(s
), s
->insn
->data
);
1399 static DisasJumpType
op_aeb(DisasContext
*s
, DisasOps
*o
)
1401 gen_helper_aeb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
1405 static DisasJumpType
op_adb(DisasContext
*s
, DisasOps
*o
)
1407 gen_helper_adb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
1411 static DisasJumpType
op_axb(DisasContext
*s
, DisasOps
*o
)
1413 gen_helper_axb(o
->out_128
, cpu_env
, o
->in1_128
, o
->in2_128
);
1417 static DisasJumpType
op_and(DisasContext
*s
, DisasOps
*o
)
1419 tcg_gen_and_i64(o
->out
, o
->in1
, o
->in2
);
1423 static DisasJumpType
op_andi(DisasContext
*s
, DisasOps
*o
)
1425 int shift
= s
->insn
->data
& 0xff;
1426 int size
= s
->insn
->data
>> 8;
1427 uint64_t mask
= ((1ull << size
) - 1) << shift
;
1428 TCGv_i64 t
= tcg_temp_new_i64();
1430 tcg_gen_shli_i64(t
, o
->in2
, shift
);
1431 tcg_gen_ori_i64(t
, t
, ~mask
);
1432 tcg_gen_and_i64(o
->out
, o
->in1
, t
);
1434 /* Produce the CC from only the bits manipulated. */
1435 tcg_gen_andi_i64(cc_dst
, o
->out
, mask
);
1436 set_cc_nz_u64(s
, cc_dst
);
1440 static DisasJumpType
op_andc(DisasContext
*s
, DisasOps
*o
)
1442 tcg_gen_andc_i64(o
->out
, o
->in1
, o
->in2
);
1446 static DisasJumpType
op_orc(DisasContext
*s
, DisasOps
*o
)
1448 tcg_gen_orc_i64(o
->out
, o
->in1
, o
->in2
);
1452 static DisasJumpType
op_nand(DisasContext
*s
, DisasOps
*o
)
1454 tcg_gen_nand_i64(o
->out
, o
->in1
, o
->in2
);
1458 static DisasJumpType
op_nor(DisasContext
*s
, DisasOps
*o
)
1460 tcg_gen_nor_i64(o
->out
, o
->in1
, o
->in2
);
1464 static DisasJumpType
op_nxor(DisasContext
*s
, DisasOps
*o
)
1466 tcg_gen_eqv_i64(o
->out
, o
->in1
, o
->in2
);
1470 static DisasJumpType
op_ni(DisasContext
*s
, DisasOps
*o
)
1472 o
->in1
= tcg_temp_new_i64();
1474 if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2
)) {
1475 tcg_gen_qemu_ld_tl(o
->in1
, o
->addr1
, get_mem_index(s
), s
->insn
->data
);
1477 /* Perform the atomic operation in memory. */
1478 tcg_gen_atomic_fetch_and_i64(o
->in1
, o
->addr1
, o
->in2
, get_mem_index(s
),
1482 /* Recompute also for atomic case: needed for setting CC. */
1483 tcg_gen_and_i64(o
->out
, o
->in1
, o
->in2
);
1485 if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2
)) {
1486 tcg_gen_qemu_st_tl(o
->out
, o
->addr1
, get_mem_index(s
), s
->insn
->data
);
1491 static DisasJumpType
op_bas(DisasContext
*s
, DisasOps
*o
)
1493 pc_to_link_info(o
->out
, s
, s
->pc_tmp
);
1495 tcg_gen_mov_i64(psw_addr
, o
->in2
);
1496 per_branch(s
, false);
1497 return DISAS_PC_UPDATED
;
1503 static void save_link_info(DisasContext
*s
, DisasOps
*o
)
1507 if (s
->base
.tb
->flags
& (FLAG_MASK_32
| FLAG_MASK_64
)) {
1508 pc_to_link_info(o
->out
, s
, s
->pc_tmp
);
1512 tcg_gen_andi_i64(o
->out
, o
->out
, 0xffffffff00000000ull
);
1513 tcg_gen_ori_i64(o
->out
, o
->out
, ((s
->ilen
/ 2) << 30) | s
->pc_tmp
);
1514 t
= tcg_temp_new_i64();
1515 tcg_gen_shri_i64(t
, psw_mask
, 16);
1516 tcg_gen_andi_i64(t
, t
, 0x0f000000);
1517 tcg_gen_or_i64(o
->out
, o
->out
, t
);
1518 tcg_gen_extu_i32_i64(t
, cc_op
);
1519 tcg_gen_shli_i64(t
, t
, 28);
1520 tcg_gen_or_i64(o
->out
, o
->out
, t
);
1523 static DisasJumpType
op_bal(DisasContext
*s
, DisasOps
*o
)
1525 save_link_info(s
, o
);
1527 tcg_gen_mov_i64(psw_addr
, o
->in2
);
1528 per_branch(s
, false);
1529 return DISAS_PC_UPDATED
;
1536 * Disassemble the target of a branch. The results are returned in a form
1537 * suitable for passing into help_branch():
1539 * - bool IS_IMM reflects whether the target is fixed or computed. Non-EXECUTEd
1540 * branches, whose DisasContext *S contains the relative immediate field RI,
1541 * are considered fixed. All the other branches are considered computed.
1542 * - int IMM is the value of RI.
1543 * - TCGv_i64 CDEST is the address of the computed target.
1545 #define disas_jdest(s, ri, is_imm, imm, cdest) do { \
1546 if (have_field(s, ri)) { \
1547 if (unlikely(s->ex_value)) { \
1548 cdest = tcg_temp_new_i64(); \
1549 tcg_gen_ld_i64(cdest, cpu_env, offsetof(CPUS390XState, ex_target));\
1550 tcg_gen_addi_i64(cdest, cdest, (int64_t)get_field(s, ri) * 2); \
1558 imm = is_imm ? get_field(s, ri) : 0; \
1561 static DisasJumpType
op_basi(DisasContext
*s
, DisasOps
*o
)
1567 pc_to_link_info(o
->out
, s
, s
->pc_tmp
);
1569 disas_jdest(s
, i2
, is_imm
, imm
, o
->in2
);
1570 disas_jcc(s
, &c
, 0xf);
1571 return help_branch(s
, &c
, is_imm
, imm
, o
->in2
);
1574 static DisasJumpType
op_bc(DisasContext
*s
, DisasOps
*o
)
1576 int m1
= get_field(s
, m1
);
1581 /* BCR with R2 = 0 causes no branching */
1582 if (have_field(s
, r2
) && get_field(s
, r2
) == 0) {
1584 /* Perform serialization */
1585 /* FIXME: check for fast-BCR-serialization facility */
1586 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1589 /* Perform serialization */
1590 /* FIXME: perform checkpoint-synchronisation */
1591 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1596 disas_jdest(s
, i2
, is_imm
, imm
, o
->in2
);
1597 disas_jcc(s
, &c
, m1
);
1598 return help_branch(s
, &c
, is_imm
, imm
, o
->in2
);
1601 static DisasJumpType
op_bct32(DisasContext
*s
, DisasOps
*o
)
1603 int r1
= get_field(s
, r1
);
1609 c
.cond
= TCG_COND_NE
;
1612 t
= tcg_temp_new_i64();
1613 tcg_gen_subi_i64(t
, regs
[r1
], 1);
1614 store_reg32_i64(r1
, t
);
1615 c
.u
.s32
.a
= tcg_temp_new_i32();
1616 c
.u
.s32
.b
= tcg_constant_i32(0);
1617 tcg_gen_extrl_i64_i32(c
.u
.s32
.a
, t
);
1619 disas_jdest(s
, i2
, is_imm
, imm
, o
->in2
);
1620 return help_branch(s
, &c
, is_imm
, imm
, o
->in2
);
1623 static DisasJumpType
op_bcth(DisasContext
*s
, DisasOps
*o
)
1625 int r1
= get_field(s
, r1
);
1626 int imm
= get_field(s
, i2
);
1630 c
.cond
= TCG_COND_NE
;
1633 t
= tcg_temp_new_i64();
1634 tcg_gen_shri_i64(t
, regs
[r1
], 32);
1635 tcg_gen_subi_i64(t
, t
, 1);
1636 store_reg32h_i64(r1
, t
);
1637 c
.u
.s32
.a
= tcg_temp_new_i32();
1638 c
.u
.s32
.b
= tcg_constant_i32(0);
1639 tcg_gen_extrl_i64_i32(c
.u
.s32
.a
, t
);
1641 return help_branch(s
, &c
, 1, imm
, o
->in2
);
1644 static DisasJumpType
op_bct64(DisasContext
*s
, DisasOps
*o
)
1646 int r1
= get_field(s
, r1
);
1651 c
.cond
= TCG_COND_NE
;
1654 tcg_gen_subi_i64(regs
[r1
], regs
[r1
], 1);
1655 c
.u
.s64
.a
= regs
[r1
];
1656 c
.u
.s64
.b
= tcg_constant_i64(0);
1658 disas_jdest(s
, i2
, is_imm
, imm
, o
->in2
);
1659 return help_branch(s
, &c
, is_imm
, imm
, o
->in2
);
1662 static DisasJumpType
op_bx32(DisasContext
*s
, DisasOps
*o
)
1664 int r1
= get_field(s
, r1
);
1665 int r3
= get_field(s
, r3
);
1671 c
.cond
= (s
->insn
->data
? TCG_COND_LE
: TCG_COND_GT
);
1674 t
= tcg_temp_new_i64();
1675 tcg_gen_add_i64(t
, regs
[r1
], regs
[r3
]);
1676 c
.u
.s32
.a
= tcg_temp_new_i32();
1677 c
.u
.s32
.b
= tcg_temp_new_i32();
1678 tcg_gen_extrl_i64_i32(c
.u
.s32
.a
, t
);
1679 tcg_gen_extrl_i64_i32(c
.u
.s32
.b
, regs
[r3
| 1]);
1680 store_reg32_i64(r1
, t
);
1682 disas_jdest(s
, i2
, is_imm
, imm
, o
->in2
);
1683 return help_branch(s
, &c
, is_imm
, imm
, o
->in2
);
1686 static DisasJumpType
op_bx64(DisasContext
*s
, DisasOps
*o
)
1688 int r1
= get_field(s
, r1
);
1689 int r3
= get_field(s
, r3
);
1694 c
.cond
= (s
->insn
->data
? TCG_COND_LE
: TCG_COND_GT
);
1697 if (r1
== (r3
| 1)) {
1698 c
.u
.s64
.b
= load_reg(r3
| 1);
1700 c
.u
.s64
.b
= regs
[r3
| 1];
1703 tcg_gen_add_i64(regs
[r1
], regs
[r1
], regs
[r3
]);
1704 c
.u
.s64
.a
= regs
[r1
];
1706 disas_jdest(s
, i2
, is_imm
, imm
, o
->in2
);
1707 return help_branch(s
, &c
, is_imm
, imm
, o
->in2
);
1710 static DisasJumpType
op_cj(DisasContext
*s
, DisasOps
*o
)
1712 int imm
, m3
= get_field(s
, m3
);
1716 c
.cond
= ltgt_cond
[m3
];
1717 if (s
->insn
->data
) {
1718 c
.cond
= tcg_unsigned_cond(c
.cond
);
1725 disas_jdest(s
, i4
, is_imm
, imm
, o
->out
);
1726 if (!is_imm
&& !o
->out
) {
1728 o
->out
= get_address(s
, 0, get_field(s
, b4
),
1732 return help_branch(s
, &c
, is_imm
, imm
, o
->out
);
1735 static DisasJumpType
op_ceb(DisasContext
*s
, DisasOps
*o
)
1737 gen_helper_ceb(cc_op
, cpu_env
, o
->in1
, o
->in2
);
1742 static DisasJumpType
op_cdb(DisasContext
*s
, DisasOps
*o
)
1744 gen_helper_cdb(cc_op
, cpu_env
, o
->in1
, o
->in2
);
1749 static DisasJumpType
op_cxb(DisasContext
*s
, DisasOps
*o
)
1751 gen_helper_cxb(cc_op
, cpu_env
, o
->in1_128
, o
->in2_128
);
1756 static TCGv_i32
fpinst_extract_m34(DisasContext
*s
, bool m3_with_fpe
,
1759 const bool fpe
= s390_has_feat(S390_FEAT_FLOATING_POINT_EXT
);
1760 uint8_t m3
= get_field(s
, m3
);
1761 uint8_t m4
= get_field(s
, m4
);
1763 /* m3 field was introduced with FPE */
1764 if (!fpe
&& m3_with_fpe
) {
1767 /* m4 field was introduced with FPE */
1768 if (!fpe
&& m4_with_fpe
) {
1772 /* Check for valid rounding modes. Mode 3 was introduced later. */
1773 if (m3
== 2 || m3
> 7 || (!fpe
&& m3
== 3)) {
1774 gen_program_exception(s
, PGM_SPECIFICATION
);
1778 return tcg_constant_i32(deposit32(m3
, 4, 4, m4
));
1781 static DisasJumpType
op_cfeb(DisasContext
*s
, DisasOps
*o
)
1783 TCGv_i32 m34
= fpinst_extract_m34(s
, false, true);
1786 return DISAS_NORETURN
;
1788 gen_helper_cfeb(o
->out
, cpu_env
, o
->in2
, m34
);
1793 static DisasJumpType
op_cfdb(DisasContext
*s
, DisasOps
*o
)
1795 TCGv_i32 m34
= fpinst_extract_m34(s
, false, true);
1798 return DISAS_NORETURN
;
1800 gen_helper_cfdb(o
->out
, cpu_env
, o
->in2
, m34
);
1805 static DisasJumpType
op_cfxb(DisasContext
*s
, DisasOps
*o
)
1807 TCGv_i32 m34
= fpinst_extract_m34(s
, false, true);
1810 return DISAS_NORETURN
;
1812 gen_helper_cfxb(o
->out
, cpu_env
, o
->in2_128
, m34
);
1817 static DisasJumpType
op_cgeb(DisasContext
*s
, DisasOps
*o
)
1819 TCGv_i32 m34
= fpinst_extract_m34(s
, false, true);
1822 return DISAS_NORETURN
;
1824 gen_helper_cgeb(o
->out
, cpu_env
, o
->in2
, m34
);
1829 static DisasJumpType
op_cgdb(DisasContext
*s
, DisasOps
*o
)
1831 TCGv_i32 m34
= fpinst_extract_m34(s
, false, true);
1834 return DISAS_NORETURN
;
1836 gen_helper_cgdb(o
->out
, cpu_env
, o
->in2
, m34
);
1841 static DisasJumpType
op_cgxb(DisasContext
*s
, DisasOps
*o
)
1843 TCGv_i32 m34
= fpinst_extract_m34(s
, false, true);
1846 return DISAS_NORETURN
;
1848 gen_helper_cgxb(o
->out
, cpu_env
, o
->in2_128
, m34
);
1853 static DisasJumpType
op_clfeb(DisasContext
*s
, DisasOps
*o
)
1855 TCGv_i32 m34
= fpinst_extract_m34(s
, false, false);
1858 return DISAS_NORETURN
;
1860 gen_helper_clfeb(o
->out
, cpu_env
, o
->in2
, m34
);
1865 static DisasJumpType
op_clfdb(DisasContext
*s
, DisasOps
*o
)
1867 TCGv_i32 m34
= fpinst_extract_m34(s
, false, false);
1870 return DISAS_NORETURN
;
1872 gen_helper_clfdb(o
->out
, cpu_env
, o
->in2
, m34
);
1877 static DisasJumpType
op_clfxb(DisasContext
*s
, DisasOps
*o
)
1879 TCGv_i32 m34
= fpinst_extract_m34(s
, false, false);
1882 return DISAS_NORETURN
;
1884 gen_helper_clfxb(o
->out
, cpu_env
, o
->in2_128
, m34
);
1889 static DisasJumpType
op_clgeb(DisasContext
*s
, DisasOps
*o
)
1891 TCGv_i32 m34
= fpinst_extract_m34(s
, false, false);
1894 return DISAS_NORETURN
;
1896 gen_helper_clgeb(o
->out
, cpu_env
, o
->in2
, m34
);
1901 static DisasJumpType
op_clgdb(DisasContext
*s
, DisasOps
*o
)
1903 TCGv_i32 m34
= fpinst_extract_m34(s
, false, false);
1906 return DISAS_NORETURN
;
1908 gen_helper_clgdb(o
->out
, cpu_env
, o
->in2
, m34
);
1913 static DisasJumpType
op_clgxb(DisasContext
*s
, DisasOps
*o
)
1915 TCGv_i32 m34
= fpinst_extract_m34(s
, false, false);
1918 return DISAS_NORETURN
;
1920 gen_helper_clgxb(o
->out
, cpu_env
, o
->in2_128
, m34
);
1925 static DisasJumpType
op_cegb(DisasContext
*s
, DisasOps
*o
)
1927 TCGv_i32 m34
= fpinst_extract_m34(s
, true, true);
1930 return DISAS_NORETURN
;
1932 gen_helper_cegb(o
->out
, cpu_env
, o
->in2
, m34
);
1936 static DisasJumpType
op_cdgb(DisasContext
*s
, DisasOps
*o
)
1938 TCGv_i32 m34
= fpinst_extract_m34(s
, true, true);
1941 return DISAS_NORETURN
;
1943 gen_helper_cdgb(o
->out
, cpu_env
, o
->in2
, m34
);
1947 static DisasJumpType
op_cxgb(DisasContext
*s
, DisasOps
*o
)
1949 TCGv_i32 m34
= fpinst_extract_m34(s
, true, true);
1952 return DISAS_NORETURN
;
1954 gen_helper_cxgb(o
->out_128
, cpu_env
, o
->in2
, m34
);
1958 static DisasJumpType
op_celgb(DisasContext
*s
, DisasOps
*o
)
1960 TCGv_i32 m34
= fpinst_extract_m34(s
, false, false);
1963 return DISAS_NORETURN
;
1965 gen_helper_celgb(o
->out
, cpu_env
, o
->in2
, m34
);
1969 static DisasJumpType
op_cdlgb(DisasContext
*s
, DisasOps
*o
)
1971 TCGv_i32 m34
= fpinst_extract_m34(s
, false, false);
1974 return DISAS_NORETURN
;
1976 gen_helper_cdlgb(o
->out
, cpu_env
, o
->in2
, m34
);
1980 static DisasJumpType
op_cxlgb(DisasContext
*s
, DisasOps
*o
)
1982 TCGv_i32 m34
= fpinst_extract_m34(s
, false, false);
1985 return DISAS_NORETURN
;
1987 gen_helper_cxlgb(o
->out_128
, cpu_env
, o
->in2
, m34
);
1991 static DisasJumpType
op_cksm(DisasContext
*s
, DisasOps
*o
)
1993 int r2
= get_field(s
, r2
);
1994 TCGv_i128 pair
= tcg_temp_new_i128();
1995 TCGv_i64 len
= tcg_temp_new_i64();
1997 gen_helper_cksm(pair
, cpu_env
, o
->in1
, o
->in2
, regs
[r2
+ 1]);
1999 tcg_gen_extr_i128_i64(o
->out
, len
, pair
);
2001 tcg_gen_add_i64(regs
[r2
], regs
[r2
], len
);
2002 tcg_gen_sub_i64(regs
[r2
+ 1], regs
[r2
+ 1], len
);
2007 static DisasJumpType
op_clc(DisasContext
*s
, DisasOps
*o
)
2009 int l
= get_field(s
, l1
);
2018 mop
= ctz32(l
+ 1) | MO_TE
;
2019 tcg_gen_qemu_ld_tl(cc_src
, o
->addr1
, get_mem_index(s
), mop
);
2020 tcg_gen_qemu_ld_tl(cc_dst
, o
->in2
, get_mem_index(s
), mop
);
2021 gen_op_update2_cc_i64(s
, CC_OP_LTUGTU_64
, cc_src
, cc_dst
);
2024 vl
= tcg_constant_i32(l
);
2025 gen_helper_clc(cc_op
, cpu_env
, vl
, o
->addr1
, o
->in2
);
2031 static DisasJumpType
op_clcl(DisasContext
*s
, DisasOps
*o
)
2033 int r1
= get_field(s
, r1
);
2034 int r2
= get_field(s
, r2
);
2037 /* r1 and r2 must be even. */
2038 if (r1
& 1 || r2
& 1) {
2039 gen_program_exception(s
, PGM_SPECIFICATION
);
2040 return DISAS_NORETURN
;
2043 t1
= tcg_constant_i32(r1
);
2044 t2
= tcg_constant_i32(r2
);
2045 gen_helper_clcl(cc_op
, cpu_env
, t1
, t2
);
2050 static DisasJumpType
op_clcle(DisasContext
*s
, DisasOps
*o
)
2052 int r1
= get_field(s
, r1
);
2053 int r3
= get_field(s
, r3
);
2056 /* r1 and r3 must be even. */
2057 if (r1
& 1 || r3
& 1) {
2058 gen_program_exception(s
, PGM_SPECIFICATION
);
2059 return DISAS_NORETURN
;
2062 t1
= tcg_constant_i32(r1
);
2063 t3
= tcg_constant_i32(r3
);
2064 gen_helper_clcle(cc_op
, cpu_env
, t1
, o
->in2
, t3
);
2069 static DisasJumpType
op_clclu(DisasContext
*s
, DisasOps
*o
)
2071 int r1
= get_field(s
, r1
);
2072 int r3
= get_field(s
, r3
);
2075 /* r1 and r3 must be even. */
2076 if (r1
& 1 || r3
& 1) {
2077 gen_program_exception(s
, PGM_SPECIFICATION
);
2078 return DISAS_NORETURN
;
2081 t1
= tcg_constant_i32(r1
);
2082 t3
= tcg_constant_i32(r3
);
2083 gen_helper_clclu(cc_op
, cpu_env
, t1
, o
->in2
, t3
);
2088 static DisasJumpType
op_clm(DisasContext
*s
, DisasOps
*o
)
2090 TCGv_i32 m3
= tcg_constant_i32(get_field(s
, m3
));
2091 TCGv_i32 t1
= tcg_temp_new_i32();
2093 tcg_gen_extrl_i64_i32(t1
, o
->in1
);
2094 gen_helper_clm(cc_op
, cpu_env
, t1
, m3
, o
->in2
);
2099 static DisasJumpType
op_clst(DisasContext
*s
, DisasOps
*o
)
2101 TCGv_i128 pair
= tcg_temp_new_i128();
2103 gen_helper_clst(pair
, cpu_env
, regs
[0], o
->in1
, o
->in2
);
2104 tcg_gen_extr_i128_i64(o
->in2
, o
->in1
, pair
);
2110 static DisasJumpType
op_cps(DisasContext
*s
, DisasOps
*o
)
2112 TCGv_i64 t
= tcg_temp_new_i64();
2113 tcg_gen_andi_i64(t
, o
->in1
, 0x8000000000000000ull
);
2114 tcg_gen_andi_i64(o
->out
, o
->in2
, 0x7fffffffffffffffull
);
2115 tcg_gen_or_i64(o
->out
, o
->out
, t
);
2119 static DisasJumpType
op_cs(DisasContext
*s
, DisasOps
*o
)
2121 int d2
= get_field(s
, d2
);
2122 int b2
= get_field(s
, b2
);
2125 /* Note that in1 = R3 (new value) and
2126 in2 = (zero-extended) R1 (expected value). */
2128 addr
= get_address(s
, 0, b2
, d2
);
2129 tcg_gen_atomic_cmpxchg_i64(o
->out
, addr
, o
->in2
, o
->in1
,
2130 get_mem_index(s
), s
->insn
->data
| MO_ALIGN
);
2132 /* Are the memory and expected values (un)equal? Note that this setcond
2133 produces the output CC value, thus the NE sense of the test. */
2134 cc
= tcg_temp_new_i64();
2135 tcg_gen_setcond_i64(TCG_COND_NE
, cc
, o
->in2
, o
->out
);
2136 tcg_gen_extrl_i64_i32(cc_op
, cc
);
2142 static DisasJumpType
op_cdsg(DisasContext
*s
, DisasOps
*o
)
2144 int r1
= get_field(s
, r1
);
2146 o
->out_128
= tcg_temp_new_i128();
2147 tcg_gen_concat_i64_i128(o
->out_128
, regs
[r1
+ 1], regs
[r1
]);
2149 /* Note out (R1:R1+1) = expected value and in2 (R3:R3+1) = new value. */
2150 tcg_gen_atomic_cmpxchg_i128(o
->out_128
, o
->addr1
, o
->out_128
, o
->in2_128
,
2151 get_mem_index(s
), MO_BE
| MO_128
| MO_ALIGN
);
2154 * Extract result into cc_dst:cc_src, compare vs the expected value
2155 * in the as yet unmodified input registers, then update CC_OP.
2157 tcg_gen_extr_i128_i64(cc_src
, cc_dst
, o
->out_128
);
2158 tcg_gen_xor_i64(cc_dst
, cc_dst
, regs
[r1
]);
2159 tcg_gen_xor_i64(cc_src
, cc_src
, regs
[r1
+ 1]);
2160 tcg_gen_or_i64(cc_dst
, cc_dst
, cc_src
);
2161 set_cc_nz_u64(s
, cc_dst
);
2166 static DisasJumpType
op_csst(DisasContext
*s
, DisasOps
*o
)
2168 int r3
= get_field(s
, r3
);
2169 TCGv_i32 t_r3
= tcg_constant_i32(r3
);
2171 if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2172 gen_helper_csst_parallel(cc_op
, cpu_env
, t_r3
, o
->addr1
, o
->in2
);
2174 gen_helper_csst(cc_op
, cpu_env
, t_r3
, o
->addr1
, o
->in2
);
2181 #ifndef CONFIG_USER_ONLY
2182 static DisasJumpType
op_csp(DisasContext
*s
, DisasOps
*o
)
2184 MemOp mop
= s
->insn
->data
;
2185 TCGv_i64 addr
, old
, cc
;
2186 TCGLabel
*lab
= gen_new_label();
2188 /* Note that in1 = R1 (zero-extended expected value),
2189 out = R1 (original reg), out2 = R1+1 (new value). */
2191 addr
= tcg_temp_new_i64();
2192 old
= tcg_temp_new_i64();
2193 tcg_gen_andi_i64(addr
, o
->in2
, -1ULL << (mop
& MO_SIZE
));
2194 tcg_gen_atomic_cmpxchg_i64(old
, addr
, o
->in1
, o
->out2
,
2195 get_mem_index(s
), mop
| MO_ALIGN
);
2197 /* Are the memory and expected values (un)equal? */
2198 cc
= tcg_temp_new_i64();
2199 tcg_gen_setcond_i64(TCG_COND_NE
, cc
, o
->in1
, old
);
2200 tcg_gen_extrl_i64_i32(cc_op
, cc
);
2202 /* Write back the output now, so that it happens before the
2203 following branch, so that we don't need local temps. */
2204 if ((mop
& MO_SIZE
) == MO_32
) {
2205 tcg_gen_deposit_i64(o
->out
, o
->out
, old
, 0, 32);
2207 tcg_gen_mov_i64(o
->out
, old
);
2210 /* If the comparison was equal, and the LSB of R2 was set,
2211 then we need to flush the TLB (for all cpus). */
2212 tcg_gen_xori_i64(cc
, cc
, 1);
2213 tcg_gen_and_i64(cc
, cc
, o
->in2
);
2214 tcg_gen_brcondi_i64(TCG_COND_EQ
, cc
, 0, lab
);
2216 gen_helper_purge(cpu_env
);
2223 static DisasJumpType
op_cvd(DisasContext
*s
, DisasOps
*o
)
2225 TCGv_i64 t1
= tcg_temp_new_i64();
2226 TCGv_i32 t2
= tcg_temp_new_i32();
2227 tcg_gen_extrl_i64_i32(t2
, o
->in1
);
2228 gen_helper_cvd(t1
, t2
);
2229 tcg_gen_qemu_st_i64(t1
, o
->in2
, get_mem_index(s
), MO_TEUQ
);
2233 static DisasJumpType
op_ct(DisasContext
*s
, DisasOps
*o
)
2235 int m3
= get_field(s
, m3
);
2236 TCGLabel
*lab
= gen_new_label();
2239 c
= tcg_invert_cond(ltgt_cond
[m3
]);
2240 if (s
->insn
->data
) {
2241 c
= tcg_unsigned_cond(c
);
2243 tcg_gen_brcond_i64(c
, o
->in1
, o
->in2
, lab
);
2252 static DisasJumpType
op_cuXX(DisasContext
*s
, DisasOps
*o
)
2254 int m3
= get_field(s
, m3
);
2255 int r1
= get_field(s
, r1
);
2256 int r2
= get_field(s
, r2
);
2257 TCGv_i32 tr1
, tr2
, chk
;
2259 /* R1 and R2 must both be even. */
2260 if ((r1
| r2
) & 1) {
2261 gen_program_exception(s
, PGM_SPECIFICATION
);
2262 return DISAS_NORETURN
;
2264 if (!s390_has_feat(S390_FEAT_ETF3_ENH
)) {
2268 tr1
= tcg_constant_i32(r1
);
2269 tr2
= tcg_constant_i32(r2
);
2270 chk
= tcg_constant_i32(m3
);
2272 switch (s
->insn
->data
) {
2274 gen_helper_cu12(cc_op
, cpu_env
, tr1
, tr2
, chk
);
2277 gen_helper_cu14(cc_op
, cpu_env
, tr1
, tr2
, chk
);
2280 gen_helper_cu21(cc_op
, cpu_env
, tr1
, tr2
, chk
);
2283 gen_helper_cu24(cc_op
, cpu_env
, tr1
, tr2
, chk
);
2286 gen_helper_cu41(cc_op
, cpu_env
, tr1
, tr2
, chk
);
2289 gen_helper_cu42(cc_op
, cpu_env
, tr1
, tr2
, chk
);
2292 g_assert_not_reached();
2299 #ifndef CONFIG_USER_ONLY
2300 static DisasJumpType
op_diag(DisasContext
*s
, DisasOps
*o
)
2302 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
2303 TCGv_i32 r3
= tcg_constant_i32(get_field(s
, r3
));
2304 TCGv_i32 func_code
= tcg_constant_i32(get_field(s
, i2
));
2306 gen_helper_diag(cpu_env
, r1
, r3
, func_code
);
2311 static DisasJumpType
op_divs32(DisasContext
*s
, DisasOps
*o
)
2313 gen_helper_divs32(o
->out
, cpu_env
, o
->in1
, o
->in2
);
2314 tcg_gen_extr32_i64(o
->out2
, o
->out
, o
->out
);
2318 static DisasJumpType
op_divu32(DisasContext
*s
, DisasOps
*o
)
2320 gen_helper_divu32(o
->out
, cpu_env
, o
->in1
, o
->in2
);
2321 tcg_gen_extr32_i64(o
->out2
, o
->out
, o
->out
);
2325 static DisasJumpType
op_divs64(DisasContext
*s
, DisasOps
*o
)
2327 TCGv_i128 t
= tcg_temp_new_i128();
2329 gen_helper_divs64(t
, cpu_env
, o
->in1
, o
->in2
);
2330 tcg_gen_extr_i128_i64(o
->out2
, o
->out
, t
);
2334 static DisasJumpType
op_divu64(DisasContext
*s
, DisasOps
*o
)
2336 TCGv_i128 t
= tcg_temp_new_i128();
2338 gen_helper_divu64(t
, cpu_env
, o
->out
, o
->out2
, o
->in2
);
2339 tcg_gen_extr_i128_i64(o
->out2
, o
->out
, t
);
2343 static DisasJumpType
op_deb(DisasContext
*s
, DisasOps
*o
)
2345 gen_helper_deb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
2349 static DisasJumpType
op_ddb(DisasContext
*s
, DisasOps
*o
)
2351 gen_helper_ddb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
2355 static DisasJumpType
op_dxb(DisasContext
*s
, DisasOps
*o
)
2357 gen_helper_dxb(o
->out_128
, cpu_env
, o
->in1_128
, o
->in2_128
);
2361 static DisasJumpType
op_ear(DisasContext
*s
, DisasOps
*o
)
2363 int r2
= get_field(s
, r2
);
2364 tcg_gen_ld32u_i64(o
->out
, cpu_env
, offsetof(CPUS390XState
, aregs
[r2
]));
2368 static DisasJumpType
op_ecag(DisasContext
*s
, DisasOps
*o
)
2370 /* No cache information provided. */
2371 tcg_gen_movi_i64(o
->out
, -1);
2375 static DisasJumpType
op_efpc(DisasContext
*s
, DisasOps
*o
)
2377 tcg_gen_ld32u_i64(o
->out
, cpu_env
, offsetof(CPUS390XState
, fpc
));
2381 static DisasJumpType
op_epsw(DisasContext
*s
, DisasOps
*o
)
2383 int r1
= get_field(s
, r1
);
2384 int r2
= get_field(s
, r2
);
2385 TCGv_i64 t
= tcg_temp_new_i64();
2386 TCGv_i64 t_cc
= tcg_temp_new_i64();
2388 /* Note the "subsequently" in the PoO, which implies a defined result
2389 if r1 == r2. Thus we cannot defer these writes to an output hook. */
2391 tcg_gen_extu_i32_i64(t_cc
, cc_op
);
2392 tcg_gen_shri_i64(t
, psw_mask
, 32);
2393 tcg_gen_deposit_i64(t
, t
, t_cc
, 12, 2);
2394 store_reg32_i64(r1
, t
);
2396 store_reg32_i64(r2
, psw_mask
);
2401 static DisasJumpType
op_ex(DisasContext
*s
, DisasOps
*o
)
2403 int r1
= get_field(s
, r1
);
2407 /* Nested EXECUTE is not allowed. */
2408 if (unlikely(s
->ex_value
)) {
2409 gen_program_exception(s
, PGM_EXECUTE
);
2410 return DISAS_NORETURN
;
2417 v1
= tcg_constant_i64(0);
2422 ilen
= tcg_constant_i32(s
->ilen
);
2423 gen_helper_ex(cpu_env
, ilen
, v1
, o
->in2
);
2425 return DISAS_PC_CC_UPDATED
;
2428 static DisasJumpType
op_fieb(DisasContext
*s
, DisasOps
*o
)
2430 TCGv_i32 m34
= fpinst_extract_m34(s
, false, true);
2433 return DISAS_NORETURN
;
2435 gen_helper_fieb(o
->out
, cpu_env
, o
->in2
, m34
);
2439 static DisasJumpType
op_fidb(DisasContext
*s
, DisasOps
*o
)
2441 TCGv_i32 m34
= fpinst_extract_m34(s
, false, true);
2444 return DISAS_NORETURN
;
2446 gen_helper_fidb(o
->out
, cpu_env
, o
->in2
, m34
);
2450 static DisasJumpType
op_fixb(DisasContext
*s
, DisasOps
*o
)
2452 TCGv_i32 m34
= fpinst_extract_m34(s
, false, true);
2455 return DISAS_NORETURN
;
2457 gen_helper_fixb(o
->out_128
, cpu_env
, o
->in2_128
, m34
);
2461 static DisasJumpType
op_flogr(DisasContext
*s
, DisasOps
*o
)
2463 /* We'll use the original input for cc computation, since we get to
2464 compare that against 0, which ought to be better than comparing
2465 the real output against 64. It also lets cc_dst be a convenient
2466 temporary during our computation. */
2467 gen_op_update1_cc_i64(s
, CC_OP_FLOGR
, o
->in2
);
2469 /* R1 = IN ? CLZ(IN) : 64. */
2470 tcg_gen_clzi_i64(o
->out
, o
->in2
, 64);
2472 /* R1+1 = IN & ~(found bit). Note that we may attempt to shift this
2473 value by 64, which is undefined. But since the shift is 64 iff the
2474 input is zero, we still get the correct result after and'ing. */
2475 tcg_gen_movi_i64(o
->out2
, 0x8000000000000000ull
);
2476 tcg_gen_shr_i64(o
->out2
, o
->out2
, o
->out
);
2477 tcg_gen_andc_i64(o
->out2
, cc_dst
, o
->out2
);
2481 static DisasJumpType
op_icm(DisasContext
*s
, DisasOps
*o
)
2483 int m3
= get_field(s
, m3
);
2484 int pos
, len
, base
= s
->insn
->data
;
2485 TCGv_i64 tmp
= tcg_temp_new_i64();
2490 /* Effectively a 32-bit load. */
2491 tcg_gen_qemu_ld_i64(tmp
, o
->in2
, get_mem_index(s
), MO_TEUL
);
2498 /* Effectively a 16-bit load. */
2499 tcg_gen_qemu_ld_i64(tmp
, o
->in2
, get_mem_index(s
), MO_TEUW
);
2507 /* Effectively an 8-bit load. */
2508 tcg_gen_qemu_ld_i64(tmp
, o
->in2
, get_mem_index(s
), MO_UB
);
2513 pos
= base
+ ctz32(m3
) * 8;
2514 tcg_gen_deposit_i64(o
->out
, o
->out
, tmp
, pos
, len
);
2515 ccm
= ((1ull << len
) - 1) << pos
;
2519 /* Recognize access exceptions for the first byte. */
2520 tcg_gen_qemu_ld_i64(tmp
, o
->in2
, get_mem_index(s
), MO_UB
);
2521 gen_op_movi_cc(s
, 0);
2525 /* This is going to be a sequence of loads and inserts. */
2526 pos
= base
+ 32 - 8;
2530 tcg_gen_qemu_ld_i64(tmp
, o
->in2
, get_mem_index(s
), MO_UB
);
2531 tcg_gen_addi_i64(o
->in2
, o
->in2
, 1);
2532 tcg_gen_deposit_i64(o
->out
, o
->out
, tmp
, pos
, 8);
2533 ccm
|= 0xffull
<< pos
;
2535 m3
= (m3
<< 1) & 0xf;
2541 tcg_gen_movi_i64(tmp
, ccm
);
2542 gen_op_update2_cc_i64(s
, CC_OP_ICM
, tmp
, o
->out
);
2546 static DisasJumpType
op_insi(DisasContext
*s
, DisasOps
*o
)
2548 int shift
= s
->insn
->data
& 0xff;
2549 int size
= s
->insn
->data
>> 8;
2550 tcg_gen_deposit_i64(o
->out
, o
->in1
, o
->in2
, shift
, size
);
2554 static DisasJumpType
op_ipm(DisasContext
*s
, DisasOps
*o
)
2559 t1
= tcg_temp_new_i64();
2560 tcg_gen_extract_i64(t1
, psw_mask
, 40, 4);
2561 t2
= tcg_temp_new_i64();
2562 tcg_gen_extu_i32_i64(t2
, cc_op
);
2563 tcg_gen_deposit_i64(t1
, t1
, t2
, 4, 60);
2564 tcg_gen_deposit_i64(o
->out
, o
->out
, t1
, 24, 8);
2568 #ifndef CONFIG_USER_ONLY
2569 static DisasJumpType
op_idte(DisasContext
*s
, DisasOps
*o
)
2573 if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING
)) {
2574 m4
= tcg_constant_i32(get_field(s
, m4
));
2576 m4
= tcg_constant_i32(0);
2578 gen_helper_idte(cpu_env
, o
->in1
, o
->in2
, m4
);
2582 static DisasJumpType
op_ipte(DisasContext
*s
, DisasOps
*o
)
2586 if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING
)) {
2587 m4
= tcg_constant_i32(get_field(s
, m4
));
2589 m4
= tcg_constant_i32(0);
2591 gen_helper_ipte(cpu_env
, o
->in1
, o
->in2
, m4
);
2595 static DisasJumpType
op_iske(DisasContext
*s
, DisasOps
*o
)
2597 gen_helper_iske(o
->out
, cpu_env
, o
->in2
);
2602 static DisasJumpType
op_msa(DisasContext
*s
, DisasOps
*o
)
2604 int r1
= have_field(s
, r1
) ? get_field(s
, r1
) : 0;
2605 int r2
= have_field(s
, r2
) ? get_field(s
, r2
) : 0;
2606 int r3
= have_field(s
, r3
) ? get_field(s
, r3
) : 0;
2607 TCGv_i32 t_r1
, t_r2
, t_r3
, type
;
2609 switch (s
->insn
->data
) {
2610 case S390_FEAT_TYPE_KMA
:
2611 if (r3
== r1
|| r3
== r2
) {
2612 gen_program_exception(s
, PGM_SPECIFICATION
);
2613 return DISAS_NORETURN
;
2616 case S390_FEAT_TYPE_KMCTR
:
2617 if (r3
& 1 || !r3
) {
2618 gen_program_exception(s
, PGM_SPECIFICATION
);
2619 return DISAS_NORETURN
;
2622 case S390_FEAT_TYPE_PPNO
:
2623 case S390_FEAT_TYPE_KMF
:
2624 case S390_FEAT_TYPE_KMC
:
2625 case S390_FEAT_TYPE_KMO
:
2626 case S390_FEAT_TYPE_KM
:
2627 if (r1
& 1 || !r1
) {
2628 gen_program_exception(s
, PGM_SPECIFICATION
);
2629 return DISAS_NORETURN
;
2632 case S390_FEAT_TYPE_KMAC
:
2633 case S390_FEAT_TYPE_KIMD
:
2634 case S390_FEAT_TYPE_KLMD
:
2635 if (r2
& 1 || !r2
) {
2636 gen_program_exception(s
, PGM_SPECIFICATION
);
2637 return DISAS_NORETURN
;
2640 case S390_FEAT_TYPE_PCKMO
:
2641 case S390_FEAT_TYPE_PCC
:
2644 g_assert_not_reached();
2647 t_r1
= tcg_constant_i32(r1
);
2648 t_r2
= tcg_constant_i32(r2
);
2649 t_r3
= tcg_constant_i32(r3
);
2650 type
= tcg_constant_i32(s
->insn
->data
);
2651 gen_helper_msa(cc_op
, cpu_env
, t_r1
, t_r2
, t_r3
, type
);
2656 static DisasJumpType
op_keb(DisasContext
*s
, DisasOps
*o
)
2658 gen_helper_keb(cc_op
, cpu_env
, o
->in1
, o
->in2
);
2663 static DisasJumpType
op_kdb(DisasContext
*s
, DisasOps
*o
)
2665 gen_helper_kdb(cc_op
, cpu_env
, o
->in1
, o
->in2
);
2670 static DisasJumpType
op_kxb(DisasContext
*s
, DisasOps
*o
)
2672 gen_helper_kxb(cc_op
, cpu_env
, o
->in1_128
, o
->in2_128
);
2677 static DisasJumpType
op_laa(DisasContext
*s
, DisasOps
*o
)
2679 /* The real output is indeed the original value in memory;
2680 recompute the addition for the computation of CC. */
2681 tcg_gen_atomic_fetch_add_i64(o
->in2
, o
->in2
, o
->in1
, get_mem_index(s
),
2682 s
->insn
->data
| MO_ALIGN
);
2683 /* However, we need to recompute the addition for setting CC. */
2684 tcg_gen_add_i64(o
->out
, o
->in1
, o
->in2
);
2688 static DisasJumpType
op_lan(DisasContext
*s
, DisasOps
*o
)
2690 /* The real output is indeed the original value in memory;
2691 recompute the addition for the computation of CC. */
2692 tcg_gen_atomic_fetch_and_i64(o
->in2
, o
->in2
, o
->in1
, get_mem_index(s
),
2693 s
->insn
->data
| MO_ALIGN
);
2694 /* However, we need to recompute the operation for setting CC. */
2695 tcg_gen_and_i64(o
->out
, o
->in1
, o
->in2
);
2699 static DisasJumpType
op_lao(DisasContext
*s
, DisasOps
*o
)
2701 /* The real output is indeed the original value in memory;
2702 recompute the addition for the computation of CC. */
2703 tcg_gen_atomic_fetch_or_i64(o
->in2
, o
->in2
, o
->in1
, get_mem_index(s
),
2704 s
->insn
->data
| MO_ALIGN
);
2705 /* However, we need to recompute the operation for setting CC. */
2706 tcg_gen_or_i64(o
->out
, o
->in1
, o
->in2
);
2710 static DisasJumpType
op_lax(DisasContext
*s
, DisasOps
*o
)
2712 /* The real output is indeed the original value in memory;
2713 recompute the addition for the computation of CC. */
2714 tcg_gen_atomic_fetch_xor_i64(o
->in2
, o
->in2
, o
->in1
, get_mem_index(s
),
2715 s
->insn
->data
| MO_ALIGN
);
2716 /* However, we need to recompute the operation for setting CC. */
2717 tcg_gen_xor_i64(o
->out
, o
->in1
, o
->in2
);
2721 static DisasJumpType
op_ldeb(DisasContext
*s
, DisasOps
*o
)
2723 gen_helper_ldeb(o
->out
, cpu_env
, o
->in2
);
2727 static DisasJumpType
op_ledb(DisasContext
*s
, DisasOps
*o
)
2729 TCGv_i32 m34
= fpinst_extract_m34(s
, true, true);
2732 return DISAS_NORETURN
;
2734 gen_helper_ledb(o
->out
, cpu_env
, o
->in2
, m34
);
2738 static DisasJumpType
op_ldxb(DisasContext
*s
, DisasOps
*o
)
2740 TCGv_i32 m34
= fpinst_extract_m34(s
, true, true);
2743 return DISAS_NORETURN
;
2745 gen_helper_ldxb(o
->out
, cpu_env
, o
->in2_128
, m34
);
2749 static DisasJumpType
op_lexb(DisasContext
*s
, DisasOps
*o
)
2751 TCGv_i32 m34
= fpinst_extract_m34(s
, true, true);
2754 return DISAS_NORETURN
;
2756 gen_helper_lexb(o
->out
, cpu_env
, o
->in2_128
, m34
);
2760 static DisasJumpType
op_lxdb(DisasContext
*s
, DisasOps
*o
)
2762 gen_helper_lxdb(o
->out_128
, cpu_env
, o
->in2
);
2766 static DisasJumpType
op_lxeb(DisasContext
*s
, DisasOps
*o
)
2768 gen_helper_lxeb(o
->out_128
, cpu_env
, o
->in2
);
2772 static DisasJumpType
op_lde(DisasContext
*s
, DisasOps
*o
)
2774 tcg_gen_shli_i64(o
->out
, o
->in2
, 32);
2778 static DisasJumpType
op_llgt(DisasContext
*s
, DisasOps
*o
)
2780 tcg_gen_andi_i64(o
->out
, o
->in2
, 0x7fffffff);
2784 static DisasJumpType
op_ld8s(DisasContext
*s
, DisasOps
*o
)
2786 tcg_gen_qemu_ld_i64(o
->out
, o
->in2
, get_mem_index(s
), MO_SB
);
2790 static DisasJumpType
op_ld8u(DisasContext
*s
, DisasOps
*o
)
2792 tcg_gen_qemu_ld_i64(o
->out
, o
->in2
, get_mem_index(s
), MO_UB
);
2796 static DisasJumpType
op_ld16s(DisasContext
*s
, DisasOps
*o
)
2798 tcg_gen_qemu_ld_i64(o
->out
, o
->in2
, get_mem_index(s
), MO_TESW
);
2802 static DisasJumpType
op_ld16u(DisasContext
*s
, DisasOps
*o
)
2804 tcg_gen_qemu_ld_i64(o
->out
, o
->in2
, get_mem_index(s
), MO_TEUW
);
2808 static DisasJumpType
op_ld32s(DisasContext
*s
, DisasOps
*o
)
2810 tcg_gen_qemu_ld_tl(o
->out
, o
->in2
, get_mem_index(s
),
2811 MO_TESL
| s
->insn
->data
);
2815 static DisasJumpType
op_ld32u(DisasContext
*s
, DisasOps
*o
)
2817 tcg_gen_qemu_ld_tl(o
->out
, o
->in2
, get_mem_index(s
),
2818 MO_TEUL
| s
->insn
->data
);
2822 static DisasJumpType
op_ld64(DisasContext
*s
, DisasOps
*o
)
2824 tcg_gen_qemu_ld_i64(o
->out
, o
->in2
, get_mem_index(s
),
2825 MO_TEUQ
| s
->insn
->data
);
2829 static DisasJumpType
op_lat(DisasContext
*s
, DisasOps
*o
)
2831 TCGLabel
*lab
= gen_new_label();
2832 store_reg32_i64(get_field(s
, r1
), o
->in2
);
2833 /* The value is stored even in case of trap. */
2834 tcg_gen_brcondi_i64(TCG_COND_NE
, o
->in2
, 0, lab
);
2840 static DisasJumpType
op_lgat(DisasContext
*s
, DisasOps
*o
)
2842 TCGLabel
*lab
= gen_new_label();
2843 tcg_gen_qemu_ld_i64(o
->out
, o
->in2
, get_mem_index(s
), MO_TEUQ
);
2844 /* The value is stored even in case of trap. */
2845 tcg_gen_brcondi_i64(TCG_COND_NE
, o
->out
, 0, lab
);
2851 static DisasJumpType
op_lfhat(DisasContext
*s
, DisasOps
*o
)
2853 TCGLabel
*lab
= gen_new_label();
2854 store_reg32h_i64(get_field(s
, r1
), o
->in2
);
2855 /* The value is stored even in case of trap. */
2856 tcg_gen_brcondi_i64(TCG_COND_NE
, o
->in2
, 0, lab
);
2862 static DisasJumpType
op_llgfat(DisasContext
*s
, DisasOps
*o
)
2864 TCGLabel
*lab
= gen_new_label();
2866 tcg_gen_qemu_ld_i64(o
->out
, o
->in2
, get_mem_index(s
), MO_TEUL
);
2867 /* The value is stored even in case of trap. */
2868 tcg_gen_brcondi_i64(TCG_COND_NE
, o
->out
, 0, lab
);
2874 static DisasJumpType
op_llgtat(DisasContext
*s
, DisasOps
*o
)
2876 TCGLabel
*lab
= gen_new_label();
2877 tcg_gen_andi_i64(o
->out
, o
->in2
, 0x7fffffff);
2878 /* The value is stored even in case of trap. */
2879 tcg_gen_brcondi_i64(TCG_COND_NE
, o
->out
, 0, lab
);
2885 static DisasJumpType
op_loc(DisasContext
*s
, DisasOps
*o
)
2889 if (have_field(s
, m3
)) {
2890 /* LOAD * ON CONDITION */
2891 disas_jcc(s
, &c
, get_field(s
, m3
));
2894 disas_jcc(s
, &c
, get_field(s
, m4
));
2898 tcg_gen_movcond_i64(c
.cond
, o
->out
, c
.u
.s64
.a
, c
.u
.s64
.b
,
2901 TCGv_i32 t32
= tcg_temp_new_i32();
2904 tcg_gen_setcond_i32(c
.cond
, t32
, c
.u
.s32
.a
, c
.u
.s32
.b
);
2906 t
= tcg_temp_new_i64();
2907 tcg_gen_extu_i32_i64(t
, t32
);
2909 z
= tcg_constant_i64(0);
2910 tcg_gen_movcond_i64(TCG_COND_NE
, o
->out
, t
, z
, o
->in2
, o
->in1
);
2916 #ifndef CONFIG_USER_ONLY
2917 static DisasJumpType
op_lctl(DisasContext
*s
, DisasOps
*o
)
2919 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
2920 TCGv_i32 r3
= tcg_constant_i32(get_field(s
, r3
));
2922 gen_helper_lctl(cpu_env
, r1
, o
->in2
, r3
);
2923 /* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */
2924 s
->exit_to_mainloop
= true;
2925 return DISAS_TOO_MANY
;
2928 static DisasJumpType
op_lctlg(DisasContext
*s
, DisasOps
*o
)
2930 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
2931 TCGv_i32 r3
= tcg_constant_i32(get_field(s
, r3
));
2933 gen_helper_lctlg(cpu_env
, r1
, o
->in2
, r3
);
2934 /* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */
2935 s
->exit_to_mainloop
= true;
2936 return DISAS_TOO_MANY
;
2939 static DisasJumpType
op_lra(DisasContext
*s
, DisasOps
*o
)
2941 gen_helper_lra(o
->out
, cpu_env
, o
->out
, o
->in2
);
2946 static DisasJumpType
op_lpp(DisasContext
*s
, DisasOps
*o
)
2948 tcg_gen_st_i64(o
->in2
, cpu_env
, offsetof(CPUS390XState
, pp
));
2952 static DisasJumpType
op_lpsw(DisasContext
*s
, DisasOps
*o
)
2954 TCGv_i64 mask
, addr
;
2956 per_breaking_event(s
);
2959 * Convert the short PSW into the normal PSW, similar to what
2960 * s390_cpu_load_normal() does.
2962 mask
= tcg_temp_new_i64();
2963 addr
= tcg_temp_new_i64();
2964 tcg_gen_qemu_ld_i64(mask
, o
->in2
, get_mem_index(s
), MO_TEUQ
| MO_ALIGN_8
);
2965 tcg_gen_andi_i64(addr
, mask
, PSW_MASK_SHORT_ADDR
);
2966 tcg_gen_andi_i64(mask
, mask
, PSW_MASK_SHORT_CTRL
);
2967 tcg_gen_xori_i64(mask
, mask
, PSW_MASK_SHORTPSW
);
2968 gen_helper_load_psw(cpu_env
, mask
, addr
);
2969 return DISAS_NORETURN
;
2972 static DisasJumpType
op_lpswe(DisasContext
*s
, DisasOps
*o
)
2976 per_breaking_event(s
);
2978 t1
= tcg_temp_new_i64();
2979 t2
= tcg_temp_new_i64();
2980 tcg_gen_qemu_ld_i64(t1
, o
->in2
, get_mem_index(s
),
2981 MO_TEUQ
| MO_ALIGN_8
);
2982 tcg_gen_addi_i64(o
->in2
, o
->in2
, 8);
2983 tcg_gen_qemu_ld_i64(t2
, o
->in2
, get_mem_index(s
), MO_TEUQ
);
2984 gen_helper_load_psw(cpu_env
, t1
, t2
);
2985 return DISAS_NORETURN
;
2989 static DisasJumpType
op_lam(DisasContext
*s
, DisasOps
*o
)
2991 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
2992 TCGv_i32 r3
= tcg_constant_i32(get_field(s
, r3
));
2994 gen_helper_lam(cpu_env
, r1
, o
->in2
, r3
);
2998 static DisasJumpType
op_lm32(DisasContext
*s
, DisasOps
*o
)
3000 int r1
= get_field(s
, r1
);
3001 int r3
= get_field(s
, r3
);
3004 /* Only one register to read. */
3005 t1
= tcg_temp_new_i64();
3006 if (unlikely(r1
== r3
)) {
3007 tcg_gen_qemu_ld_i64(t1
, o
->in2
, get_mem_index(s
), MO_TEUL
);
3008 store_reg32_i64(r1
, t1
);
3012 /* First load the values of the first and last registers to trigger
3013 possible page faults. */
3014 t2
= tcg_temp_new_i64();
3015 tcg_gen_qemu_ld_i64(t1
, o
->in2
, get_mem_index(s
), MO_TEUL
);
3016 tcg_gen_addi_i64(t2
, o
->in2
, 4 * ((r3
- r1
) & 15));
3017 tcg_gen_qemu_ld_i64(t2
, t2
, get_mem_index(s
), MO_TEUL
);
3018 store_reg32_i64(r1
, t1
);
3019 store_reg32_i64(r3
, t2
);
3021 /* Only two registers to read. */
3022 if (((r1
+ 1) & 15) == r3
) {
3026 /* Then load the remaining registers. Page fault can't occur. */
3028 tcg_gen_movi_i64(t2
, 4);
3031 tcg_gen_add_i64(o
->in2
, o
->in2
, t2
);
3032 tcg_gen_qemu_ld_i64(t1
, o
->in2
, get_mem_index(s
), MO_TEUL
);
3033 store_reg32_i64(r1
, t1
);
3038 static DisasJumpType
op_lmh(DisasContext
*s
, DisasOps
*o
)
3040 int r1
= get_field(s
, r1
);
3041 int r3
= get_field(s
, r3
);
3044 /* Only one register to read. */
3045 t1
= tcg_temp_new_i64();
3046 if (unlikely(r1
== r3
)) {
3047 tcg_gen_qemu_ld_i64(t1
, o
->in2
, get_mem_index(s
), MO_TEUL
);
3048 store_reg32h_i64(r1
, t1
);
3052 /* First load the values of the first and last registers to trigger
3053 possible page faults. */
3054 t2
= tcg_temp_new_i64();
3055 tcg_gen_qemu_ld_i64(t1
, o
->in2
, get_mem_index(s
), MO_TEUL
);
3056 tcg_gen_addi_i64(t2
, o
->in2
, 4 * ((r3
- r1
) & 15));
3057 tcg_gen_qemu_ld_i64(t2
, t2
, get_mem_index(s
), MO_TEUL
);
3058 store_reg32h_i64(r1
, t1
);
3059 store_reg32h_i64(r3
, t2
);
3061 /* Only two registers to read. */
3062 if (((r1
+ 1) & 15) == r3
) {
3066 /* Then load the remaining registers. Page fault can't occur. */
3068 tcg_gen_movi_i64(t2
, 4);
3071 tcg_gen_add_i64(o
->in2
, o
->in2
, t2
);
3072 tcg_gen_qemu_ld_i64(t1
, o
->in2
, get_mem_index(s
), MO_TEUL
);
3073 store_reg32h_i64(r1
, t1
);
3078 static DisasJumpType
op_lm64(DisasContext
*s
, DisasOps
*o
)
3080 int r1
= get_field(s
, r1
);
3081 int r3
= get_field(s
, r3
);
3084 /* Only one register to read. */
3085 if (unlikely(r1
== r3
)) {
3086 tcg_gen_qemu_ld_i64(regs
[r1
], o
->in2
, get_mem_index(s
), MO_TEUQ
);
3090 /* First load the values of the first and last registers to trigger
3091 possible page faults. */
3092 t1
= tcg_temp_new_i64();
3093 t2
= tcg_temp_new_i64();
3094 tcg_gen_qemu_ld_i64(t1
, o
->in2
, get_mem_index(s
), MO_TEUQ
);
3095 tcg_gen_addi_i64(t2
, o
->in2
, 8 * ((r3
- r1
) & 15));
3096 tcg_gen_qemu_ld_i64(regs
[r3
], t2
, get_mem_index(s
), MO_TEUQ
);
3097 tcg_gen_mov_i64(regs
[r1
], t1
);
3099 /* Only two registers to read. */
3100 if (((r1
+ 1) & 15) == r3
) {
3104 /* Then load the remaining registers. Page fault can't occur. */
3106 tcg_gen_movi_i64(t1
, 8);
3109 tcg_gen_add_i64(o
->in2
, o
->in2
, t1
);
3110 tcg_gen_qemu_ld_i64(regs
[r1
], o
->in2
, get_mem_index(s
), MO_TEUQ
);
3115 static DisasJumpType
op_lpd(DisasContext
*s
, DisasOps
*o
)
3118 MemOp mop
= s
->insn
->data
;
3120 /* In a parallel context, stop the world and single step. */
3121 if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
3124 gen_exception(EXCP_ATOMIC
);
3125 return DISAS_NORETURN
;
3128 /* In a serial context, perform the two loads ... */
3129 a1
= get_address(s
, 0, get_field(s
, b1
), get_field(s
, d1
));
3130 a2
= get_address(s
, 0, get_field(s
, b2
), get_field(s
, d2
));
3131 tcg_gen_qemu_ld_i64(o
->out
, a1
, get_mem_index(s
), mop
| MO_ALIGN
);
3132 tcg_gen_qemu_ld_i64(o
->out2
, a2
, get_mem_index(s
), mop
| MO_ALIGN
);
3134 /* ... and indicate that we performed them while interlocked. */
3135 gen_op_movi_cc(s
, 0);
3139 static DisasJumpType
op_lpq(DisasContext
*s
, DisasOps
*o
)
3141 o
->out_128
= tcg_temp_new_i128();
3142 tcg_gen_qemu_ld_i128(o
->out_128
, o
->in2
, get_mem_index(s
),
3143 MO_TE
| MO_128
| MO_ALIGN
);
3147 #ifndef CONFIG_USER_ONLY
3148 static DisasJumpType
op_lura(DisasContext
*s
, DisasOps
*o
)
3150 tcg_gen_qemu_ld_tl(o
->out
, o
->in2
, MMU_REAL_IDX
, s
->insn
->data
);
3155 static DisasJumpType
op_lzrb(DisasContext
*s
, DisasOps
*o
)
3157 tcg_gen_andi_i64(o
->out
, o
->in2
, -256);
3161 static DisasJumpType
op_lcbb(DisasContext
*s
, DisasOps
*o
)
3163 const int64_t block_size
= (1ull << (get_field(s
, m3
) + 6));
3165 if (get_field(s
, m3
) > 6) {
3166 gen_program_exception(s
, PGM_SPECIFICATION
);
3167 return DISAS_NORETURN
;
3170 tcg_gen_ori_i64(o
->addr1
, o
->addr1
, -block_size
);
3171 tcg_gen_neg_i64(o
->addr1
, o
->addr1
);
3172 tcg_gen_movi_i64(o
->out
, 16);
3173 tcg_gen_umin_i64(o
->out
, o
->out
, o
->addr1
);
3174 gen_op_update1_cc_i64(s
, CC_OP_LCBB
, o
->out
);
3178 static DisasJumpType
op_mc(DisasContext
*s
, DisasOps
*o
)
3180 const uint8_t monitor_class
= get_field(s
, i2
);
3182 if (monitor_class
& 0xf0) {
3183 gen_program_exception(s
, PGM_SPECIFICATION
);
3184 return DISAS_NORETURN
;
3187 #if !defined(CONFIG_USER_ONLY)
3188 gen_helper_monitor_call(cpu_env
, o
->addr1
,
3189 tcg_constant_i32(monitor_class
));
3191 /* Defaults to a NOP. */
3195 static DisasJumpType
op_mov2(DisasContext
*s
, DisasOps
*o
)
3202 static DisasJumpType
op_mov2e(DisasContext
*s
, DisasOps
*o
)
3204 int b2
= get_field(s
, b2
);
3205 TCGv ar1
= tcg_temp_new_i64();
3210 switch (s
->base
.tb
->flags
& FLAG_MASK_ASC
) {
3211 case PSW_ASC_PRIMARY
>> FLAG_MASK_PSW_SHIFT
:
3212 tcg_gen_movi_i64(ar1
, 0);
3214 case PSW_ASC_ACCREG
>> FLAG_MASK_PSW_SHIFT
:
3215 tcg_gen_movi_i64(ar1
, 1);
3217 case PSW_ASC_SECONDARY
>> FLAG_MASK_PSW_SHIFT
:
3219 tcg_gen_ld32u_i64(ar1
, cpu_env
, offsetof(CPUS390XState
, aregs
[b2
]));
3221 tcg_gen_movi_i64(ar1
, 0);
3224 case PSW_ASC_HOME
>> FLAG_MASK_PSW_SHIFT
:
3225 tcg_gen_movi_i64(ar1
, 2);
3229 tcg_gen_st32_i64(ar1
, cpu_env
, offsetof(CPUS390XState
, aregs
[1]));
3233 static DisasJumpType
op_movx(DisasContext
*s
, DisasOps
*o
)
3242 static DisasJumpType
op_mvc(DisasContext
*s
, DisasOps
*o
)
3244 TCGv_i32 l
= tcg_constant_i32(get_field(s
, l1
));
3246 gen_helper_mvc(cpu_env
, l
, o
->addr1
, o
->in2
);
3250 static DisasJumpType
op_mvcrl(DisasContext
*s
, DisasOps
*o
)
3252 gen_helper_mvcrl(cpu_env
, regs
[0], o
->addr1
, o
->in2
);
3256 static DisasJumpType
op_mvcin(DisasContext
*s
, DisasOps
*o
)
3258 TCGv_i32 l
= tcg_constant_i32(get_field(s
, l1
));
3260 gen_helper_mvcin(cpu_env
, l
, o
->addr1
, o
->in2
);
3264 static DisasJumpType
op_mvcl(DisasContext
*s
, DisasOps
*o
)
3266 int r1
= get_field(s
, r1
);
3267 int r2
= get_field(s
, r2
);
3270 /* r1 and r2 must be even. */
3271 if (r1
& 1 || r2
& 1) {
3272 gen_program_exception(s
, PGM_SPECIFICATION
);
3273 return DISAS_NORETURN
;
3276 t1
= tcg_constant_i32(r1
);
3277 t2
= tcg_constant_i32(r2
);
3278 gen_helper_mvcl(cc_op
, cpu_env
, t1
, t2
);
3283 static DisasJumpType
op_mvcle(DisasContext
*s
, DisasOps
*o
)
3285 int r1
= get_field(s
, r1
);
3286 int r3
= get_field(s
, r3
);
3289 /* r1 and r3 must be even. */
3290 if (r1
& 1 || r3
& 1) {
3291 gen_program_exception(s
, PGM_SPECIFICATION
);
3292 return DISAS_NORETURN
;
3295 t1
= tcg_constant_i32(r1
);
3296 t3
= tcg_constant_i32(r3
);
3297 gen_helper_mvcle(cc_op
, cpu_env
, t1
, o
->in2
, t3
);
3302 static DisasJumpType
op_mvclu(DisasContext
*s
, DisasOps
*o
)
3304 int r1
= get_field(s
, r1
);
3305 int r3
= get_field(s
, r3
);
3308 /* r1 and r3 must be even. */
3309 if (r1
& 1 || r3
& 1) {
3310 gen_program_exception(s
, PGM_SPECIFICATION
);
3311 return DISAS_NORETURN
;
3314 t1
= tcg_constant_i32(r1
);
3315 t3
= tcg_constant_i32(r3
);
3316 gen_helper_mvclu(cc_op
, cpu_env
, t1
, o
->in2
, t3
);
3321 static DisasJumpType
op_mvcos(DisasContext
*s
, DisasOps
*o
)
3323 int r3
= get_field(s
, r3
);
3324 gen_helper_mvcos(cc_op
, cpu_env
, o
->addr1
, o
->in2
, regs
[r3
]);
3329 #ifndef CONFIG_USER_ONLY
3330 static DisasJumpType
op_mvcp(DisasContext
*s
, DisasOps
*o
)
3332 int r1
= get_field(s
, l1
);
3333 int r3
= get_field(s
, r3
);
3334 gen_helper_mvcp(cc_op
, cpu_env
, regs
[r1
], o
->addr1
, o
->in2
, regs
[r3
]);
3339 static DisasJumpType
op_mvcs(DisasContext
*s
, DisasOps
*o
)
3341 int r1
= get_field(s
, l1
);
3342 int r3
= get_field(s
, r3
);
3343 gen_helper_mvcs(cc_op
, cpu_env
, regs
[r1
], o
->addr1
, o
->in2
, regs
[r3
]);
3349 static DisasJumpType
op_mvn(DisasContext
*s
, DisasOps
*o
)
3351 TCGv_i32 l
= tcg_constant_i32(get_field(s
, l1
));
3353 gen_helper_mvn(cpu_env
, l
, o
->addr1
, o
->in2
);
3357 static DisasJumpType
op_mvo(DisasContext
*s
, DisasOps
*o
)
3359 TCGv_i32 l
= tcg_constant_i32(get_field(s
, l1
));
3361 gen_helper_mvo(cpu_env
, l
, o
->addr1
, o
->in2
);
3365 static DisasJumpType
op_mvpg(DisasContext
*s
, DisasOps
*o
)
3367 TCGv_i32 t1
= tcg_constant_i32(get_field(s
, r1
));
3368 TCGv_i32 t2
= tcg_constant_i32(get_field(s
, r2
));
3370 gen_helper_mvpg(cc_op
, cpu_env
, regs
[0], t1
, t2
);
3375 static DisasJumpType
op_mvst(DisasContext
*s
, DisasOps
*o
)
3377 TCGv_i32 t1
= tcg_constant_i32(get_field(s
, r1
));
3378 TCGv_i32 t2
= tcg_constant_i32(get_field(s
, r2
));
3380 gen_helper_mvst(cc_op
, cpu_env
, t1
, t2
);
3385 static DisasJumpType
op_mvz(DisasContext
*s
, DisasOps
*o
)
3387 TCGv_i32 l
= tcg_constant_i32(get_field(s
, l1
));
3389 gen_helper_mvz(cpu_env
, l
, o
->addr1
, o
->in2
);
3393 static DisasJumpType
op_mul(DisasContext
*s
, DisasOps
*o
)
3395 tcg_gen_mul_i64(o
->out
, o
->in1
, o
->in2
);
3399 static DisasJumpType
op_mul128(DisasContext
*s
, DisasOps
*o
)
3401 tcg_gen_mulu2_i64(o
->out2
, o
->out
, o
->in1
, o
->in2
);
3405 static DisasJumpType
op_muls128(DisasContext
*s
, DisasOps
*o
)
3407 tcg_gen_muls2_i64(o
->out2
, o
->out
, o
->in1
, o
->in2
);
3411 static DisasJumpType
op_meeb(DisasContext
*s
, DisasOps
*o
)
3413 gen_helper_meeb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
3417 static DisasJumpType
op_mdeb(DisasContext
*s
, DisasOps
*o
)
3419 gen_helper_mdeb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
3423 static DisasJumpType
op_mdb(DisasContext
*s
, DisasOps
*o
)
3425 gen_helper_mdb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
3429 static DisasJumpType
op_mxb(DisasContext
*s
, DisasOps
*o
)
3431 gen_helper_mxb(o
->out_128
, cpu_env
, o
->in1_128
, o
->in2_128
);
3435 static DisasJumpType
op_mxdb(DisasContext
*s
, DisasOps
*o
)
3437 gen_helper_mxdb(o
->out_128
, cpu_env
, o
->in1
, o
->in2
);
3441 static DisasJumpType
op_maeb(DisasContext
*s
, DisasOps
*o
)
3443 TCGv_i64 r3
= load_freg32_i64(get_field(s
, r3
));
3444 gen_helper_maeb(o
->out
, cpu_env
, o
->in1
, o
->in2
, r3
);
3448 static DisasJumpType
op_madb(DisasContext
*s
, DisasOps
*o
)
3450 TCGv_i64 r3
= load_freg(get_field(s
, r3
));
3451 gen_helper_madb(o
->out
, cpu_env
, o
->in1
, o
->in2
, r3
);
3455 static DisasJumpType
op_mseb(DisasContext
*s
, DisasOps
*o
)
3457 TCGv_i64 r3
= load_freg32_i64(get_field(s
, r3
));
3458 gen_helper_mseb(o
->out
, cpu_env
, o
->in1
, o
->in2
, r3
);
3462 static DisasJumpType
op_msdb(DisasContext
*s
, DisasOps
*o
)
3464 TCGv_i64 r3
= load_freg(get_field(s
, r3
));
3465 gen_helper_msdb(o
->out
, cpu_env
, o
->in1
, o
->in2
, r3
);
3469 static DisasJumpType
op_nabs(DisasContext
*s
, DisasOps
*o
)
3471 TCGv_i64 z
= tcg_constant_i64(0);
3472 TCGv_i64 n
= tcg_temp_new_i64();
3474 tcg_gen_neg_i64(n
, o
->in2
);
3475 tcg_gen_movcond_i64(TCG_COND_GE
, o
->out
, o
->in2
, z
, n
, o
->in2
);
3479 static DisasJumpType
op_nabsf32(DisasContext
*s
, DisasOps
*o
)
3481 tcg_gen_ori_i64(o
->out
, o
->in2
, 0x80000000ull
);
3485 static DisasJumpType
op_nabsf64(DisasContext
*s
, DisasOps
*o
)
3487 tcg_gen_ori_i64(o
->out
, o
->in2
, 0x8000000000000000ull
);
3491 static DisasJumpType
op_nabsf128(DisasContext
*s
, DisasOps
*o
)
3493 tcg_gen_ori_i64(o
->out
, o
->in1
, 0x8000000000000000ull
);
3494 tcg_gen_mov_i64(o
->out2
, o
->in2
);
3498 static DisasJumpType
op_nc(DisasContext
*s
, DisasOps
*o
)
3500 TCGv_i32 l
= tcg_constant_i32(get_field(s
, l1
));
3502 gen_helper_nc(cc_op
, cpu_env
, l
, o
->addr1
, o
->in2
);
3507 static DisasJumpType
op_neg(DisasContext
*s
, DisasOps
*o
)
3509 tcg_gen_neg_i64(o
->out
, o
->in2
);
3513 static DisasJumpType
op_negf32(DisasContext
*s
, DisasOps
*o
)
3515 tcg_gen_xori_i64(o
->out
, o
->in2
, 0x80000000ull
);
3519 static DisasJumpType
op_negf64(DisasContext
*s
, DisasOps
*o
)
3521 tcg_gen_xori_i64(o
->out
, o
->in2
, 0x8000000000000000ull
);
3525 static DisasJumpType
op_negf128(DisasContext
*s
, DisasOps
*o
)
3527 tcg_gen_xori_i64(o
->out
, o
->in1
, 0x8000000000000000ull
);
3528 tcg_gen_mov_i64(o
->out2
, o
->in2
);
3532 static DisasJumpType
op_oc(DisasContext
*s
, DisasOps
*o
)
3534 TCGv_i32 l
= tcg_constant_i32(get_field(s
, l1
));
3536 gen_helper_oc(cc_op
, cpu_env
, l
, o
->addr1
, o
->in2
);
3541 static DisasJumpType
op_or(DisasContext
*s
, DisasOps
*o
)
3543 tcg_gen_or_i64(o
->out
, o
->in1
, o
->in2
);
3547 static DisasJumpType
op_ori(DisasContext
*s
, DisasOps
*o
)
3549 int shift
= s
->insn
->data
& 0xff;
3550 int size
= s
->insn
->data
>> 8;
3551 uint64_t mask
= ((1ull << size
) - 1) << shift
;
3552 TCGv_i64 t
= tcg_temp_new_i64();
3554 tcg_gen_shli_i64(t
, o
->in2
, shift
);
3555 tcg_gen_or_i64(o
->out
, o
->in1
, t
);
3557 /* Produce the CC from only the bits manipulated. */
3558 tcg_gen_andi_i64(cc_dst
, o
->out
, mask
);
3559 set_cc_nz_u64(s
, cc_dst
);
3563 static DisasJumpType
op_oi(DisasContext
*s
, DisasOps
*o
)
3565 o
->in1
= tcg_temp_new_i64();
3567 if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2
)) {
3568 tcg_gen_qemu_ld_tl(o
->in1
, o
->addr1
, get_mem_index(s
), s
->insn
->data
);
3570 /* Perform the atomic operation in memory. */
3571 tcg_gen_atomic_fetch_or_i64(o
->in1
, o
->addr1
, o
->in2
, get_mem_index(s
),
3575 /* Recompute also for atomic case: needed for setting CC. */
3576 tcg_gen_or_i64(o
->out
, o
->in1
, o
->in2
);
3578 if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2
)) {
3579 tcg_gen_qemu_st_tl(o
->out
, o
->addr1
, get_mem_index(s
), s
->insn
->data
);
3584 static DisasJumpType
op_pack(DisasContext
*s
, DisasOps
*o
)
3586 TCGv_i32 l
= tcg_constant_i32(get_field(s
, l1
));
3588 gen_helper_pack(cpu_env
, l
, o
->addr1
, o
->in2
);
3592 static DisasJumpType
op_pka(DisasContext
*s
, DisasOps
*o
)
3594 int l2
= get_field(s
, l2
) + 1;
3597 /* The length must not exceed 32 bytes. */
3599 gen_program_exception(s
, PGM_SPECIFICATION
);
3600 return DISAS_NORETURN
;
3602 l
= tcg_constant_i32(l2
);
3603 gen_helper_pka(cpu_env
, o
->addr1
, o
->in2
, l
);
3607 static DisasJumpType
op_pku(DisasContext
*s
, DisasOps
*o
)
3609 int l2
= get_field(s
, l2
) + 1;
3612 /* The length must be even and should not exceed 64 bytes. */
3613 if ((l2
& 1) || (l2
> 64)) {
3614 gen_program_exception(s
, PGM_SPECIFICATION
);
3615 return DISAS_NORETURN
;
3617 l
= tcg_constant_i32(l2
);
3618 gen_helper_pku(cpu_env
, o
->addr1
, o
->in2
, l
);
3622 static DisasJumpType
op_popcnt(DisasContext
*s
, DisasOps
*o
)
3624 const uint8_t m3
= get_field(s
, m3
);
3626 if ((m3
& 8) && s390_has_feat(S390_FEAT_MISC_INSTRUCTION_EXT3
)) {
3627 tcg_gen_ctpop_i64(o
->out
, o
->in2
);
3629 gen_helper_popcnt(o
->out
, o
->in2
);
3634 #ifndef CONFIG_USER_ONLY
3635 static DisasJumpType
op_ptlb(DisasContext
*s
, DisasOps
*o
)
3637 gen_helper_ptlb(cpu_env
);
3642 static DisasJumpType
op_risbg(DisasContext
*s
, DisasOps
*o
)
3644 int i3
= get_field(s
, i3
);
3645 int i4
= get_field(s
, i4
);
3646 int i5
= get_field(s
, i5
);
3647 int do_zero
= i4
& 0x80;
3648 uint64_t mask
, imask
, pmask
;
3651 /* Adjust the arguments for the specific insn. */
3652 switch (s
->fields
.op2
) {
3653 case 0x55: /* risbg */
3654 case 0x59: /* risbgn */
3659 case 0x5d: /* risbhg */
3662 pmask
= 0xffffffff00000000ull
;
3664 case 0x51: /* risblg */
3665 i3
= (i3
& 31) + 32;
3666 i4
= (i4
& 31) + 32;
3667 pmask
= 0x00000000ffffffffull
;
3670 g_assert_not_reached();
3673 /* MASK is the set of bits to be inserted from R2. */
3675 /* [0...i3---i4...63] */
3676 mask
= (-1ull >> i3
) & (-1ull << (63 - i4
));
3678 /* [0---i4...i3---63] */
3679 mask
= (-1ull >> i3
) | (-1ull << (63 - i4
));
3681 /* For RISBLG/RISBHG, the wrapping is limited to the high/low doubleword. */
3684 /* IMASK is the set of bits to be kept from R1. In the case of the high/low
3685 insns, we need to keep the other half of the register. */
3686 imask
= ~mask
| ~pmask
;
3695 /* In some cases we can implement this with extract. */
3696 if (imask
== 0 && pos
== 0 && len
> 0 && len
<= rot
) {
3697 tcg_gen_extract_i64(o
->out
, o
->in2
, 64 - rot
, len
);
3701 /* In some cases we can implement this with deposit. */
3702 if (len
> 0 && (imask
== 0 || ~mask
== imask
)) {
3703 /* Note that we rotate the bits to be inserted to the lsb, not to
3704 the position as described in the PoO. */
3705 rot
= (rot
- pos
) & 63;
3710 /* Rotate the input as necessary. */
3711 tcg_gen_rotli_i64(o
->in2
, o
->in2
, rot
);
3713 /* Insert the selected bits into the output. */
3716 tcg_gen_deposit_z_i64(o
->out
, o
->in2
, pos
, len
);
3718 tcg_gen_deposit_i64(o
->out
, o
->out
, o
->in2
, pos
, len
);
3720 } else if (imask
== 0) {
3721 tcg_gen_andi_i64(o
->out
, o
->in2
, mask
);
3723 tcg_gen_andi_i64(o
->in2
, o
->in2
, mask
);
3724 tcg_gen_andi_i64(o
->out
, o
->out
, imask
);
3725 tcg_gen_or_i64(o
->out
, o
->out
, o
->in2
);
3730 static DisasJumpType
op_rosbg(DisasContext
*s
, DisasOps
*o
)
3732 int i3
= get_field(s
, i3
);
3733 int i4
= get_field(s
, i4
);
3734 int i5
= get_field(s
, i5
);
3738 /* If this is a test-only form, arrange to discard the result. */
3740 tcg_debug_assert(o
->out
!= NULL
);
3742 o
->out
= tcg_temp_new_i64();
3743 tcg_gen_mov_i64(o
->out
, orig_out
);
3750 /* MASK is the set of bits to be operated on from R2.
3751 Take care for I3/I4 wraparound. */
3754 mask
^= ~0ull >> i4
>> 1;
3756 mask
|= ~(~0ull >> i4
>> 1);
3759 /* Rotate the input as necessary. */
3760 tcg_gen_rotli_i64(o
->in2
, o
->in2
, i5
);
3763 switch (s
->fields
.op2
) {
3764 case 0x54: /* AND */
3765 tcg_gen_ori_i64(o
->in2
, o
->in2
, ~mask
);
3766 tcg_gen_and_i64(o
->out
, o
->out
, o
->in2
);
3769 tcg_gen_andi_i64(o
->in2
, o
->in2
, mask
);
3770 tcg_gen_or_i64(o
->out
, o
->out
, o
->in2
);
3772 case 0x57: /* XOR */
3773 tcg_gen_andi_i64(o
->in2
, o
->in2
, mask
);
3774 tcg_gen_xor_i64(o
->out
, o
->out
, o
->in2
);
3781 tcg_gen_andi_i64(cc_dst
, o
->out
, mask
);
3782 set_cc_nz_u64(s
, cc_dst
);
3786 static DisasJumpType
op_rev16(DisasContext
*s
, DisasOps
*o
)
3788 tcg_gen_bswap16_i64(o
->out
, o
->in2
, TCG_BSWAP_IZ
| TCG_BSWAP_OZ
);
3792 static DisasJumpType
op_rev32(DisasContext
*s
, DisasOps
*o
)
3794 tcg_gen_bswap32_i64(o
->out
, o
->in2
, TCG_BSWAP_IZ
| TCG_BSWAP_OZ
);
3798 static DisasJumpType
op_rev64(DisasContext
*s
, DisasOps
*o
)
3800 tcg_gen_bswap64_i64(o
->out
, o
->in2
);
3804 static DisasJumpType
op_rll32(DisasContext
*s
, DisasOps
*o
)
3806 TCGv_i32 t1
= tcg_temp_new_i32();
3807 TCGv_i32 t2
= tcg_temp_new_i32();
3808 TCGv_i32 to
= tcg_temp_new_i32();
3809 tcg_gen_extrl_i64_i32(t1
, o
->in1
);
3810 tcg_gen_extrl_i64_i32(t2
, o
->in2
);
3811 tcg_gen_rotl_i32(to
, t1
, t2
);
3812 tcg_gen_extu_i32_i64(o
->out
, to
);
3816 static DisasJumpType
op_rll64(DisasContext
*s
, DisasOps
*o
)
3818 tcg_gen_rotl_i64(o
->out
, o
->in1
, o
->in2
);
3822 #ifndef CONFIG_USER_ONLY
3823 static DisasJumpType
op_rrbe(DisasContext
*s
, DisasOps
*o
)
3825 gen_helper_rrbe(cc_op
, cpu_env
, o
->in2
);
3830 static DisasJumpType
op_sacf(DisasContext
*s
, DisasOps
*o
)
3832 gen_helper_sacf(cpu_env
, o
->in2
);
3833 /* Addressing mode has changed, so end the block. */
3834 return DISAS_TOO_MANY
;
3838 static DisasJumpType
op_sam(DisasContext
*s
, DisasOps
*o
)
3840 int sam
= s
->insn
->data
;
3856 /* Bizarre but true, we check the address of the current insn for the
3857 specification exception, not the next to be executed. Thus the PoO
3858 documents that Bad Things Happen two bytes before the end. */
3859 if (s
->base
.pc_next
& ~mask
) {
3860 gen_program_exception(s
, PGM_SPECIFICATION
);
3861 return DISAS_NORETURN
;
3865 tsam
= tcg_constant_i64(sam
);
3866 tcg_gen_deposit_i64(psw_mask
, psw_mask
, tsam
, 31, 2);
3868 /* Always exit the TB, since we (may have) changed execution mode. */
3869 return DISAS_TOO_MANY
;
3872 static DisasJumpType
op_sar(DisasContext
*s
, DisasOps
*o
)
3874 int r1
= get_field(s
, r1
);
3875 tcg_gen_st32_i64(o
->in2
, cpu_env
, offsetof(CPUS390XState
, aregs
[r1
]));
3879 static DisasJumpType
op_seb(DisasContext
*s
, DisasOps
*o
)
3881 gen_helper_seb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
3885 static DisasJumpType
op_sdb(DisasContext
*s
, DisasOps
*o
)
3887 gen_helper_sdb(o
->out
, cpu_env
, o
->in1
, o
->in2
);
3891 static DisasJumpType
op_sxb(DisasContext
*s
, DisasOps
*o
)
3893 gen_helper_sxb(o
->out_128
, cpu_env
, o
->in1_128
, o
->in2_128
);
3897 static DisasJumpType
op_sqeb(DisasContext
*s
, DisasOps
*o
)
3899 gen_helper_sqeb(o
->out
, cpu_env
, o
->in2
);
3903 static DisasJumpType
op_sqdb(DisasContext
*s
, DisasOps
*o
)
3905 gen_helper_sqdb(o
->out
, cpu_env
, o
->in2
);
3909 static DisasJumpType
op_sqxb(DisasContext
*s
, DisasOps
*o
)
3911 gen_helper_sqxb(o
->out_128
, cpu_env
, o
->in2_128
);
3915 #ifndef CONFIG_USER_ONLY
3916 static DisasJumpType
op_servc(DisasContext
*s
, DisasOps
*o
)
3918 gen_helper_servc(cc_op
, cpu_env
, o
->in2
, o
->in1
);
3923 static DisasJumpType
op_sigp(DisasContext
*s
, DisasOps
*o
)
3925 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
3926 TCGv_i32 r3
= tcg_constant_i32(get_field(s
, r3
));
3928 gen_helper_sigp(cc_op
, cpu_env
, o
->in2
, r1
, r3
);
3934 static DisasJumpType
op_soc(DisasContext
*s
, DisasOps
*o
)
3941 disas_jcc(s
, &c
, get_field(s
, m3
));
3943 /* We want to store when the condition is fulfilled, so branch
3944 out when it's not */
3945 c
.cond
= tcg_invert_cond(c
.cond
);
3947 lab
= gen_new_label();
3949 tcg_gen_brcond_i64(c
.cond
, c
.u
.s64
.a
, c
.u
.s64
.b
, lab
);
3951 tcg_gen_brcond_i32(c
.cond
, c
.u
.s32
.a
, c
.u
.s32
.b
, lab
);
3954 r1
= get_field(s
, r1
);
3955 a
= get_address(s
, 0, get_field(s
, b2
), get_field(s
, d2
));
3956 switch (s
->insn
->data
) {
3958 tcg_gen_qemu_st_i64(regs
[r1
], a
, get_mem_index(s
), MO_TEUQ
);
3961 tcg_gen_qemu_st_i64(regs
[r1
], a
, get_mem_index(s
), MO_TEUL
);
3963 case 2: /* STOCFH */
3964 h
= tcg_temp_new_i64();
3965 tcg_gen_shri_i64(h
, regs
[r1
], 32);
3966 tcg_gen_qemu_st_i64(h
, a
, get_mem_index(s
), MO_TEUL
);
3969 g_assert_not_reached();
3976 static DisasJumpType
op_sla(DisasContext
*s
, DisasOps
*o
)
3979 uint64_t sign
= 1ull << s
->insn
->data
;
3980 if (s
->insn
->data
== 31) {
3981 t
= tcg_temp_new_i64();
3982 tcg_gen_shli_i64(t
, o
->in1
, 32);
3986 gen_op_update2_cc_i64(s
, CC_OP_SLA
, t
, o
->in2
);
3987 tcg_gen_shl_i64(o
->out
, o
->in1
, o
->in2
);
3988 /* The arithmetic left shift is curious in that it does not affect
3989 the sign bit. Copy that over from the source unchanged. */
3990 tcg_gen_andi_i64(o
->out
, o
->out
, ~sign
);
3991 tcg_gen_andi_i64(o
->in1
, o
->in1
, sign
);
3992 tcg_gen_or_i64(o
->out
, o
->out
, o
->in1
);
3996 static DisasJumpType
op_sll(DisasContext
*s
, DisasOps
*o
)
3998 tcg_gen_shl_i64(o
->out
, o
->in1
, o
->in2
);
4002 static DisasJumpType
op_sra(DisasContext
*s
, DisasOps
*o
)
4004 tcg_gen_sar_i64(o
->out
, o
->in1
, o
->in2
);
4008 static DisasJumpType
op_srl(DisasContext
*s
, DisasOps
*o
)
4010 tcg_gen_shr_i64(o
->out
, o
->in1
, o
->in2
);
4014 static DisasJumpType
op_sfpc(DisasContext
*s
, DisasOps
*o
)
4016 gen_helper_sfpc(cpu_env
, o
->in2
);
4020 static DisasJumpType
op_sfas(DisasContext
*s
, DisasOps
*o
)
4022 gen_helper_sfas(cpu_env
, o
->in2
);
4026 static DisasJumpType
op_srnm(DisasContext
*s
, DisasOps
*o
)
4028 /* Bits other than 62 and 63 are ignored. Bit 29 is set to zero. */
4029 tcg_gen_andi_i64(o
->addr1
, o
->addr1
, 0x3ull
);
4030 gen_helper_srnm(cpu_env
, o
->addr1
);
4034 static DisasJumpType
op_srnmb(DisasContext
*s
, DisasOps
*o
)
4036 /* Bits 0-55 are are ignored. */
4037 tcg_gen_andi_i64(o
->addr1
, o
->addr1
, 0xffull
);
4038 gen_helper_srnm(cpu_env
, o
->addr1
);
4042 static DisasJumpType
op_srnmt(DisasContext
*s
, DisasOps
*o
)
4044 TCGv_i64 tmp
= tcg_temp_new_i64();
4046 /* Bits other than 61-63 are ignored. */
4047 tcg_gen_andi_i64(o
->addr1
, o
->addr1
, 0x7ull
);
4049 /* No need to call a helper, we don't implement dfp */
4050 tcg_gen_ld32u_i64(tmp
, cpu_env
, offsetof(CPUS390XState
, fpc
));
4051 tcg_gen_deposit_i64(tmp
, tmp
, o
->addr1
, 4, 3);
4052 tcg_gen_st32_i64(tmp
, cpu_env
, offsetof(CPUS390XState
, fpc
));
4056 static DisasJumpType
op_spm(DisasContext
*s
, DisasOps
*o
)
4058 tcg_gen_extrl_i64_i32(cc_op
, o
->in1
);
4059 tcg_gen_extract_i32(cc_op
, cc_op
, 28, 2);
4062 tcg_gen_shri_i64(o
->in1
, o
->in1
, 24);
4063 tcg_gen_deposit_i64(psw_mask
, psw_mask
, o
->in1
, PSW_SHIFT_MASK_PM
, 4);
4067 static DisasJumpType
op_ectg(DisasContext
*s
, DisasOps
*o
)
4069 int b1
= get_field(s
, b1
);
4070 int d1
= get_field(s
, d1
);
4071 int b2
= get_field(s
, b2
);
4072 int d2
= get_field(s
, d2
);
4073 int r3
= get_field(s
, r3
);
4074 TCGv_i64 tmp
= tcg_temp_new_i64();
4076 /* fetch all operands first */
4077 o
->in1
= tcg_temp_new_i64();
4078 tcg_gen_addi_i64(o
->in1
, regs
[b1
], d1
);
4079 o
->in2
= tcg_temp_new_i64();
4080 tcg_gen_addi_i64(o
->in2
, regs
[b2
], d2
);
4081 o
->addr1
= tcg_temp_new_i64();
4082 gen_addi_and_wrap_i64(s
, o
->addr1
, regs
[r3
], 0);
4084 /* load the third operand into r3 before modifying anything */
4085 tcg_gen_qemu_ld_i64(regs
[r3
], o
->addr1
, get_mem_index(s
), MO_TEUQ
);
4087 /* subtract CPU timer from first operand and store in GR0 */
4088 gen_helper_stpt(tmp
, cpu_env
);
4089 tcg_gen_sub_i64(regs
[0], o
->in1
, tmp
);
4091 /* store second operand in GR1 */
4092 tcg_gen_mov_i64(regs
[1], o
->in2
);
4096 #ifndef CONFIG_USER_ONLY
4097 static DisasJumpType
op_spka(DisasContext
*s
, DisasOps
*o
)
4099 tcg_gen_shri_i64(o
->in2
, o
->in2
, 4);
4100 tcg_gen_deposit_i64(psw_mask
, psw_mask
, o
->in2
, PSW_SHIFT_KEY
, 4);
4104 static DisasJumpType
op_sske(DisasContext
*s
, DisasOps
*o
)
4106 gen_helper_sske(cpu_env
, o
->in1
, o
->in2
);
4110 static void gen_check_psw_mask(DisasContext
*s
)
4112 TCGv_i64 reserved
= tcg_temp_new_i64();
4113 TCGLabel
*ok
= gen_new_label();
4115 tcg_gen_andi_i64(reserved
, psw_mask
, PSW_MASK_RESERVED
);
4116 tcg_gen_brcondi_i64(TCG_COND_EQ
, reserved
, 0, ok
);
4117 gen_program_exception(s
, PGM_SPECIFICATION
);
4121 static DisasJumpType
op_ssm(DisasContext
*s
, DisasOps
*o
)
4123 tcg_gen_deposit_i64(psw_mask
, psw_mask
, o
->in2
, 56, 8);
4125 gen_check_psw_mask(s
);
4127 /* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */
4128 s
->exit_to_mainloop
= true;
4129 return DISAS_TOO_MANY
;
4132 static DisasJumpType
op_stap(DisasContext
*s
, DisasOps
*o
)
4134 tcg_gen_ld32u_i64(o
->out
, cpu_env
, offsetof(CPUS390XState
, core_id
));
4139 static DisasJumpType
op_stck(DisasContext
*s
, DisasOps
*o
)
4141 gen_helper_stck(o
->out
, cpu_env
);
4142 /* ??? We don't implement clock states. */
4143 gen_op_movi_cc(s
, 0);
4147 static DisasJumpType
op_stcke(DisasContext
*s
, DisasOps
*o
)
4149 TCGv_i64 c1
= tcg_temp_new_i64();
4150 TCGv_i64 c2
= tcg_temp_new_i64();
4151 TCGv_i64 todpr
= tcg_temp_new_i64();
4152 gen_helper_stck(c1
, cpu_env
);
4153 /* 16 bit value store in an uint32_t (only valid bits set) */
4154 tcg_gen_ld32u_i64(todpr
, cpu_env
, offsetof(CPUS390XState
, todpr
));
4155 /* Shift the 64-bit value into its place as a zero-extended
4156 104-bit value. Note that "bit positions 64-103 are always
4157 non-zero so that they compare differently to STCK"; we set
4158 the least significant bit to 1. */
4159 tcg_gen_shli_i64(c2
, c1
, 56);
4160 tcg_gen_shri_i64(c1
, c1
, 8);
4161 tcg_gen_ori_i64(c2
, c2
, 0x10000);
4162 tcg_gen_or_i64(c2
, c2
, todpr
);
4163 tcg_gen_qemu_st_i64(c1
, o
->in2
, get_mem_index(s
), MO_TEUQ
);
4164 tcg_gen_addi_i64(o
->in2
, o
->in2
, 8);
4165 tcg_gen_qemu_st_i64(c2
, o
->in2
, get_mem_index(s
), MO_TEUQ
);
4166 /* ??? We don't implement clock states. */
4167 gen_op_movi_cc(s
, 0);
4171 #ifndef CONFIG_USER_ONLY
4172 static DisasJumpType
op_sck(DisasContext
*s
, DisasOps
*o
)
4174 gen_helper_sck(cc_op
, cpu_env
, o
->in2
);
4179 static DisasJumpType
op_sckc(DisasContext
*s
, DisasOps
*o
)
4181 gen_helper_sckc(cpu_env
, o
->in2
);
4185 static DisasJumpType
op_sckpf(DisasContext
*s
, DisasOps
*o
)
4187 gen_helper_sckpf(cpu_env
, regs
[0]);
4191 static DisasJumpType
op_stckc(DisasContext
*s
, DisasOps
*o
)
4193 gen_helper_stckc(o
->out
, cpu_env
);
4197 static DisasJumpType
op_stctg(DisasContext
*s
, DisasOps
*o
)
4199 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
4200 TCGv_i32 r3
= tcg_constant_i32(get_field(s
, r3
));
4202 gen_helper_stctg(cpu_env
, r1
, o
->in2
, r3
);
4206 static DisasJumpType
op_stctl(DisasContext
*s
, DisasOps
*o
)
4208 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
4209 TCGv_i32 r3
= tcg_constant_i32(get_field(s
, r3
));
4211 gen_helper_stctl(cpu_env
, r1
, o
->in2
, r3
);
4215 static DisasJumpType
op_stidp(DisasContext
*s
, DisasOps
*o
)
4217 tcg_gen_ld_i64(o
->out
, cpu_env
, offsetof(CPUS390XState
, cpuid
));
4221 static DisasJumpType
op_spt(DisasContext
*s
, DisasOps
*o
)
4223 gen_helper_spt(cpu_env
, o
->in2
);
4227 static DisasJumpType
op_stfl(DisasContext
*s
, DisasOps
*o
)
4229 gen_helper_stfl(cpu_env
);
4233 static DisasJumpType
op_stpt(DisasContext
*s
, DisasOps
*o
)
4235 gen_helper_stpt(o
->out
, cpu_env
);
4239 static DisasJumpType
op_stsi(DisasContext
*s
, DisasOps
*o
)
4241 gen_helper_stsi(cc_op
, cpu_env
, o
->in2
, regs
[0], regs
[1]);
4246 static DisasJumpType
op_spx(DisasContext
*s
, DisasOps
*o
)
4248 gen_helper_spx(cpu_env
, o
->in2
);
4252 static DisasJumpType
op_xsch(DisasContext
*s
, DisasOps
*o
)
4254 gen_helper_xsch(cpu_env
, regs
[1]);
4259 static DisasJumpType
op_csch(DisasContext
*s
, DisasOps
*o
)
4261 gen_helper_csch(cpu_env
, regs
[1]);
4266 static DisasJumpType
op_hsch(DisasContext
*s
, DisasOps
*o
)
4268 gen_helper_hsch(cpu_env
, regs
[1]);
4273 static DisasJumpType
op_msch(DisasContext
*s
, DisasOps
*o
)
4275 gen_helper_msch(cpu_env
, regs
[1], o
->in2
);
4280 static DisasJumpType
op_rchp(DisasContext
*s
, DisasOps
*o
)
4282 gen_helper_rchp(cpu_env
, regs
[1]);
4287 static DisasJumpType
op_rsch(DisasContext
*s
, DisasOps
*o
)
4289 gen_helper_rsch(cpu_env
, regs
[1]);
4294 static DisasJumpType
op_sal(DisasContext
*s
, DisasOps
*o
)
4296 gen_helper_sal(cpu_env
, regs
[1]);
4300 static DisasJumpType
op_schm(DisasContext
*s
, DisasOps
*o
)
4302 gen_helper_schm(cpu_env
, regs
[1], regs
[2], o
->in2
);
4306 static DisasJumpType
op_siga(DisasContext
*s
, DisasOps
*o
)
4308 /* From KVM code: Not provided, set CC = 3 for subchannel not operational */
4309 gen_op_movi_cc(s
, 3);
4313 static DisasJumpType
op_stcps(DisasContext
*s
, DisasOps
*o
)
4315 /* The instruction is suppressed if not provided. */
4319 static DisasJumpType
op_ssch(DisasContext
*s
, DisasOps
*o
)
4321 gen_helper_ssch(cpu_env
, regs
[1], o
->in2
);
4326 static DisasJumpType
op_stsch(DisasContext
*s
, DisasOps
*o
)
4328 gen_helper_stsch(cpu_env
, regs
[1], o
->in2
);
4333 static DisasJumpType
op_stcrw(DisasContext
*s
, DisasOps
*o
)
4335 gen_helper_stcrw(cpu_env
, o
->in2
);
4340 static DisasJumpType
op_tpi(DisasContext
*s
, DisasOps
*o
)
4342 gen_helper_tpi(cc_op
, cpu_env
, o
->addr1
);
4347 static DisasJumpType
op_tsch(DisasContext
*s
, DisasOps
*o
)
4349 gen_helper_tsch(cpu_env
, regs
[1], o
->in2
);
4354 static DisasJumpType
op_chsc(DisasContext
*s
, DisasOps
*o
)
4356 gen_helper_chsc(cpu_env
, o
->in2
);
4361 static DisasJumpType
op_stpx(DisasContext
*s
, DisasOps
*o
)
4363 tcg_gen_ld_i64(o
->out
, cpu_env
, offsetof(CPUS390XState
, psa
));
4364 tcg_gen_andi_i64(o
->out
, o
->out
, 0x7fffe000);
4368 static DisasJumpType
op_stnosm(DisasContext
*s
, DisasOps
*o
)
4370 uint64_t i2
= get_field(s
, i2
);
4373 /* It is important to do what the instruction name says: STORE THEN.
4374 If we let the output hook perform the store then if we fault and
4375 restart, we'll have the wrong SYSTEM MASK in place. */
4376 t
= tcg_temp_new_i64();
4377 tcg_gen_shri_i64(t
, psw_mask
, 56);
4378 tcg_gen_qemu_st_i64(t
, o
->addr1
, get_mem_index(s
), MO_UB
);
4380 if (s
->fields
.op
== 0xac) {
4381 tcg_gen_andi_i64(psw_mask
, psw_mask
,
4382 (i2
<< 56) | 0x00ffffffffffffffull
);
4384 tcg_gen_ori_i64(psw_mask
, psw_mask
, i2
<< 56);
4387 gen_check_psw_mask(s
);
4389 /* Exit to main loop to reevaluate s390_cpu_exec_interrupt. */
4390 s
->exit_to_mainloop
= true;
4391 return DISAS_TOO_MANY
;
4394 static DisasJumpType
op_stura(DisasContext
*s
, DisasOps
*o
)
4396 tcg_gen_qemu_st_tl(o
->in1
, o
->in2
, MMU_REAL_IDX
, s
->insn
->data
);
4398 if (s
->base
.tb
->flags
& FLAG_MASK_PER
) {
4400 gen_helper_per_store_real(cpu_env
);
4406 static DisasJumpType
op_stfle(DisasContext
*s
, DisasOps
*o
)
4408 gen_helper_stfle(cc_op
, cpu_env
, o
->in2
);
4413 static DisasJumpType
op_st8(DisasContext
*s
, DisasOps
*o
)
4415 tcg_gen_qemu_st_i64(o
->in1
, o
->in2
, get_mem_index(s
), MO_UB
);
4419 static DisasJumpType
op_st16(DisasContext
*s
, DisasOps
*o
)
4421 tcg_gen_qemu_st_i64(o
->in1
, o
->in2
, get_mem_index(s
), MO_TEUW
);
4425 static DisasJumpType
op_st32(DisasContext
*s
, DisasOps
*o
)
4427 tcg_gen_qemu_st_tl(o
->in1
, o
->in2
, get_mem_index(s
),
4428 MO_TEUL
| s
->insn
->data
);
4432 static DisasJumpType
op_st64(DisasContext
*s
, DisasOps
*o
)
4434 tcg_gen_qemu_st_i64(o
->in1
, o
->in2
, get_mem_index(s
),
4435 MO_TEUQ
| s
->insn
->data
);
4439 static DisasJumpType
op_stam(DisasContext
*s
, DisasOps
*o
)
4441 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
4442 TCGv_i32 r3
= tcg_constant_i32(get_field(s
, r3
));
4444 gen_helper_stam(cpu_env
, r1
, o
->in2
, r3
);
4448 static DisasJumpType
op_stcm(DisasContext
*s
, DisasOps
*o
)
4450 int m3
= get_field(s
, m3
);
4451 int pos
, base
= s
->insn
->data
;
4452 TCGv_i64 tmp
= tcg_temp_new_i64();
4454 pos
= base
+ ctz32(m3
) * 8;
4457 /* Effectively a 32-bit store. */
4458 tcg_gen_shri_i64(tmp
, o
->in1
, pos
);
4459 tcg_gen_qemu_st_i64(tmp
, o
->in2
, get_mem_index(s
), MO_TEUL
);
4465 /* Effectively a 16-bit store. */
4466 tcg_gen_shri_i64(tmp
, o
->in1
, pos
);
4467 tcg_gen_qemu_st_i64(tmp
, o
->in2
, get_mem_index(s
), MO_TEUW
);
4474 /* Effectively an 8-bit store. */
4475 tcg_gen_shri_i64(tmp
, o
->in1
, pos
);
4476 tcg_gen_qemu_st_i64(tmp
, o
->in2
, get_mem_index(s
), MO_UB
);
4480 /* This is going to be a sequence of shifts and stores. */
4481 pos
= base
+ 32 - 8;
4484 tcg_gen_shri_i64(tmp
, o
->in1
, pos
);
4485 tcg_gen_qemu_st_i64(tmp
, o
->in2
, get_mem_index(s
), MO_UB
);
4486 tcg_gen_addi_i64(o
->in2
, o
->in2
, 1);
4488 m3
= (m3
<< 1) & 0xf;
4496 static DisasJumpType
op_stm(DisasContext
*s
, DisasOps
*o
)
4498 int r1
= get_field(s
, r1
);
4499 int r3
= get_field(s
, r3
);
4500 int size
= s
->insn
->data
;
4501 TCGv_i64 tsize
= tcg_constant_i64(size
);
4504 tcg_gen_qemu_st_i64(regs
[r1
], o
->in2
, get_mem_index(s
),
4505 size
== 8 ? MO_TEUQ
: MO_TEUL
);
4509 tcg_gen_add_i64(o
->in2
, o
->in2
, tsize
);
4516 static DisasJumpType
op_stmh(DisasContext
*s
, DisasOps
*o
)
4518 int r1
= get_field(s
, r1
);
4519 int r3
= get_field(s
, r3
);
4520 TCGv_i64 t
= tcg_temp_new_i64();
4521 TCGv_i64 t4
= tcg_constant_i64(4);
4522 TCGv_i64 t32
= tcg_constant_i64(32);
4525 tcg_gen_shl_i64(t
, regs
[r1
], t32
);
4526 tcg_gen_qemu_st_i64(t
, o
->in2
, get_mem_index(s
), MO_TEUL
);
4530 tcg_gen_add_i64(o
->in2
, o
->in2
, t4
);
4536 static DisasJumpType
op_stpq(DisasContext
*s
, DisasOps
*o
)
4538 TCGv_i128 t16
= tcg_temp_new_i128();
4540 tcg_gen_concat_i64_i128(t16
, o
->out2
, o
->out
);
4541 tcg_gen_qemu_st_i128(t16
, o
->in2
, get_mem_index(s
),
4542 MO_TE
| MO_128
| MO_ALIGN
);
4546 static DisasJumpType
op_srst(DisasContext
*s
, DisasOps
*o
)
4548 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
4549 TCGv_i32 r2
= tcg_constant_i32(get_field(s
, r2
));
4551 gen_helper_srst(cpu_env
, r1
, r2
);
4556 static DisasJumpType
op_srstu(DisasContext
*s
, DisasOps
*o
)
4558 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
4559 TCGv_i32 r2
= tcg_constant_i32(get_field(s
, r2
));
4561 gen_helper_srstu(cpu_env
, r1
, r2
);
4566 static DisasJumpType
op_sub(DisasContext
*s
, DisasOps
*o
)
4568 tcg_gen_sub_i64(o
->out
, o
->in1
, o
->in2
);
4572 static DisasJumpType
op_subu64(DisasContext
*s
, DisasOps
*o
)
4574 tcg_gen_movi_i64(cc_src
, 0);
4575 tcg_gen_sub2_i64(o
->out
, cc_src
, o
->in1
, cc_src
, o
->in2
, cc_src
);
4579 /* Compute borrow (0, -1) into cc_src. */
4580 static void compute_borrow(DisasContext
*s
)
4584 /* The borrow value is already in cc_src (0,-1). */
4590 /* The carry flag is the msb of CC; compute into cc_src. */
4591 tcg_gen_extu_i32_i64(cc_src
, cc_op
);
4592 tcg_gen_shri_i64(cc_src
, cc_src
, 1);
4595 /* Convert carry (1,0) to borrow (0,-1). */
4596 tcg_gen_subi_i64(cc_src
, cc_src
, 1);
4601 static DisasJumpType
op_subb32(DisasContext
*s
, DisasOps
*o
)
4605 /* Borrow is {0, -1}, so add to subtract. */
4606 tcg_gen_add_i64(o
->out
, o
->in1
, cc_src
);
4607 tcg_gen_sub_i64(o
->out
, o
->out
, o
->in2
);
4611 static DisasJumpType
op_subb64(DisasContext
*s
, DisasOps
*o
)
4616 * Borrow is {0, -1}, so add to subtract; replicate the
4617 * borrow input to produce 128-bit -1 for the addition.
4619 TCGv_i64 zero
= tcg_constant_i64(0);
4620 tcg_gen_add2_i64(o
->out
, cc_src
, o
->in1
, zero
, cc_src
, cc_src
);
4621 tcg_gen_sub2_i64(o
->out
, cc_src
, o
->out
, cc_src
, o
->in2
, zero
);
4626 static DisasJumpType
op_svc(DisasContext
*s
, DisasOps
*o
)
4633 t
= tcg_constant_i32(get_field(s
, i1
) & 0xff);
4634 tcg_gen_st_i32(t
, cpu_env
, offsetof(CPUS390XState
, int_svc_code
));
4636 t
= tcg_constant_i32(s
->ilen
);
4637 tcg_gen_st_i32(t
, cpu_env
, offsetof(CPUS390XState
, int_svc_ilen
));
4639 gen_exception(EXCP_SVC
);
4640 return DISAS_NORETURN
;
4643 static DisasJumpType
op_tam(DisasContext
*s
, DisasOps
*o
)
4647 cc
|= (s
->base
.tb
->flags
& FLAG_MASK_64
) ? 2 : 0;
4648 cc
|= (s
->base
.tb
->flags
& FLAG_MASK_32
) ? 1 : 0;
4649 gen_op_movi_cc(s
, cc
);
4653 static DisasJumpType
op_tceb(DisasContext
*s
, DisasOps
*o
)
4655 gen_helper_tceb(cc_op
, cpu_env
, o
->in1
, o
->in2
);
4660 static DisasJumpType
op_tcdb(DisasContext
*s
, DisasOps
*o
)
4662 gen_helper_tcdb(cc_op
, cpu_env
, o
->in1
, o
->in2
);
4667 static DisasJumpType
op_tcxb(DisasContext
*s
, DisasOps
*o
)
4669 gen_helper_tcxb(cc_op
, cpu_env
, o
->in1_128
, o
->in2
);
4674 #ifndef CONFIG_USER_ONLY
4676 static DisasJumpType
op_testblock(DisasContext
*s
, DisasOps
*o
)
4678 gen_helper_testblock(cc_op
, cpu_env
, o
->in2
);
4683 static DisasJumpType
op_tprot(DisasContext
*s
, DisasOps
*o
)
4685 gen_helper_tprot(cc_op
, cpu_env
, o
->addr1
, o
->in2
);
4692 static DisasJumpType
op_tp(DisasContext
*s
, DisasOps
*o
)
4694 TCGv_i32 l1
= tcg_constant_i32(get_field(s
, l1
) + 1);
4696 gen_helper_tp(cc_op
, cpu_env
, o
->addr1
, l1
);
4701 static DisasJumpType
op_tr(DisasContext
*s
, DisasOps
*o
)
4703 TCGv_i32 l
= tcg_constant_i32(get_field(s
, l1
));
4705 gen_helper_tr(cpu_env
, l
, o
->addr1
, o
->in2
);
4710 static DisasJumpType
op_tre(DisasContext
*s
, DisasOps
*o
)
4712 TCGv_i128 pair
= tcg_temp_new_i128();
4714 gen_helper_tre(pair
, cpu_env
, o
->out
, o
->out2
, o
->in2
);
4715 tcg_gen_extr_i128_i64(o
->out2
, o
->out
, pair
);
4720 static DisasJumpType
op_trt(DisasContext
*s
, DisasOps
*o
)
4722 TCGv_i32 l
= tcg_constant_i32(get_field(s
, l1
));
4724 gen_helper_trt(cc_op
, cpu_env
, l
, o
->addr1
, o
->in2
);
4729 static DisasJumpType
op_trtr(DisasContext
*s
, DisasOps
*o
)
4731 TCGv_i32 l
= tcg_constant_i32(get_field(s
, l1
));
4733 gen_helper_trtr(cc_op
, cpu_env
, l
, o
->addr1
, o
->in2
);
4738 static DisasJumpType
op_trXX(DisasContext
*s
, DisasOps
*o
)
4740 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
4741 TCGv_i32 r2
= tcg_constant_i32(get_field(s
, r2
));
4742 TCGv_i32 sizes
= tcg_constant_i32(s
->insn
->opc
& 3);
4743 TCGv_i32 tst
= tcg_temp_new_i32();
4744 int m3
= get_field(s
, m3
);
4746 if (!s390_has_feat(S390_FEAT_ETF2_ENH
)) {
4750 tcg_gen_movi_i32(tst
, -1);
4752 tcg_gen_extrl_i64_i32(tst
, regs
[0]);
4753 if (s
->insn
->opc
& 3) {
4754 tcg_gen_ext8u_i32(tst
, tst
);
4756 tcg_gen_ext16u_i32(tst
, tst
);
4759 gen_helper_trXX(cc_op
, cpu_env
, r1
, r2
, tst
, sizes
);
4765 static DisasJumpType
op_ts(DisasContext
*s
, DisasOps
*o
)
4767 TCGv_i32 t1
= tcg_constant_i32(0xff);
4769 tcg_gen_atomic_xchg_i32(t1
, o
->in2
, t1
, get_mem_index(s
), MO_UB
);
4770 tcg_gen_extract_i32(cc_op
, t1
, 7, 1);
4775 static DisasJumpType
op_unpk(DisasContext
*s
, DisasOps
*o
)
4777 TCGv_i32 l
= tcg_constant_i32(get_field(s
, l1
));
4779 gen_helper_unpk(cpu_env
, l
, o
->addr1
, o
->in2
);
4783 static DisasJumpType
op_unpka(DisasContext
*s
, DisasOps
*o
)
4785 int l1
= get_field(s
, l1
) + 1;
4788 /* The length must not exceed 32 bytes. */
4790 gen_program_exception(s
, PGM_SPECIFICATION
);
4791 return DISAS_NORETURN
;
4793 l
= tcg_constant_i32(l1
);
4794 gen_helper_unpka(cc_op
, cpu_env
, o
->addr1
, l
, o
->in2
);
4799 static DisasJumpType
op_unpku(DisasContext
*s
, DisasOps
*o
)
4801 int l1
= get_field(s
, l1
) + 1;
4804 /* The length must be even and should not exceed 64 bytes. */
4805 if ((l1
& 1) || (l1
> 64)) {
4806 gen_program_exception(s
, PGM_SPECIFICATION
);
4807 return DISAS_NORETURN
;
4809 l
= tcg_constant_i32(l1
);
4810 gen_helper_unpku(cc_op
, cpu_env
, o
->addr1
, l
, o
->in2
);
4816 static DisasJumpType
op_xc(DisasContext
*s
, DisasOps
*o
)
4818 int d1
= get_field(s
, d1
);
4819 int d2
= get_field(s
, d2
);
4820 int b1
= get_field(s
, b1
);
4821 int b2
= get_field(s
, b2
);
4822 int l
= get_field(s
, l1
);
4825 o
->addr1
= get_address(s
, 0, b1
, d1
);
4827 /* If the addresses are identical, this is a store/memset of zero. */
4828 if (b1
== b2
&& d1
== d2
&& (l
+ 1) <= 32) {
4829 o
->in2
= tcg_constant_i64(0);
4833 tcg_gen_qemu_st_i64(o
->in2
, o
->addr1
, get_mem_index(s
), MO_UQ
);
4836 tcg_gen_addi_i64(o
->addr1
, o
->addr1
, 8);
4840 tcg_gen_qemu_st_i64(o
->in2
, o
->addr1
, get_mem_index(s
), MO_UL
);
4843 tcg_gen_addi_i64(o
->addr1
, o
->addr1
, 4);
4847 tcg_gen_qemu_st_i64(o
->in2
, o
->addr1
, get_mem_index(s
), MO_UW
);
4850 tcg_gen_addi_i64(o
->addr1
, o
->addr1
, 2);
4854 tcg_gen_qemu_st_i64(o
->in2
, o
->addr1
, get_mem_index(s
), MO_UB
);
4856 gen_op_movi_cc(s
, 0);
4860 /* But in general we'll defer to a helper. */
4861 o
->in2
= get_address(s
, 0, b2
, d2
);
4862 t32
= tcg_constant_i32(l
);
4863 gen_helper_xc(cc_op
, cpu_env
, t32
, o
->addr1
, o
->in2
);
4868 static DisasJumpType
op_xor(DisasContext
*s
, DisasOps
*o
)
4870 tcg_gen_xor_i64(o
->out
, o
->in1
, o
->in2
);
4874 static DisasJumpType
op_xori(DisasContext
*s
, DisasOps
*o
)
4876 int shift
= s
->insn
->data
& 0xff;
4877 int size
= s
->insn
->data
>> 8;
4878 uint64_t mask
= ((1ull << size
) - 1) << shift
;
4879 TCGv_i64 t
= tcg_temp_new_i64();
4881 tcg_gen_shli_i64(t
, o
->in2
, shift
);
4882 tcg_gen_xor_i64(o
->out
, o
->in1
, t
);
4884 /* Produce the CC from only the bits manipulated. */
4885 tcg_gen_andi_i64(cc_dst
, o
->out
, mask
);
4886 set_cc_nz_u64(s
, cc_dst
);
4890 static DisasJumpType
op_xi(DisasContext
*s
, DisasOps
*o
)
4892 o
->in1
= tcg_temp_new_i64();
4894 if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2
)) {
4895 tcg_gen_qemu_ld_tl(o
->in1
, o
->addr1
, get_mem_index(s
), s
->insn
->data
);
4897 /* Perform the atomic operation in memory. */
4898 tcg_gen_atomic_fetch_xor_i64(o
->in1
, o
->addr1
, o
->in2
, get_mem_index(s
),
4902 /* Recompute also for atomic case: needed for setting CC. */
4903 tcg_gen_xor_i64(o
->out
, o
->in1
, o
->in2
);
4905 if (!s390_has_feat(S390_FEAT_INTERLOCKED_ACCESS_2
)) {
4906 tcg_gen_qemu_st_tl(o
->out
, o
->addr1
, get_mem_index(s
), s
->insn
->data
);
4911 static DisasJumpType
op_zero(DisasContext
*s
, DisasOps
*o
)
4913 o
->out
= tcg_constant_i64(0);
4917 static DisasJumpType
op_zero2(DisasContext
*s
, DisasOps
*o
)
4919 o
->out
= tcg_constant_i64(0);
4924 #ifndef CONFIG_USER_ONLY
4925 static DisasJumpType
op_clp(DisasContext
*s
, DisasOps
*o
)
4927 TCGv_i32 r2
= tcg_constant_i32(get_field(s
, r2
));
4929 gen_helper_clp(cpu_env
, r2
);
4934 static DisasJumpType
op_pcilg(DisasContext
*s
, DisasOps
*o
)
4936 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
4937 TCGv_i32 r2
= tcg_constant_i32(get_field(s
, r2
));
4939 gen_helper_pcilg(cpu_env
, r1
, r2
);
4944 static DisasJumpType
op_pcistg(DisasContext
*s
, DisasOps
*o
)
4946 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
4947 TCGv_i32 r2
= tcg_constant_i32(get_field(s
, r2
));
4949 gen_helper_pcistg(cpu_env
, r1
, r2
);
4954 static DisasJumpType
op_stpcifc(DisasContext
*s
, DisasOps
*o
)
4956 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
4957 TCGv_i32 ar
= tcg_constant_i32(get_field(s
, b2
));
4959 gen_helper_stpcifc(cpu_env
, r1
, o
->addr1
, ar
);
4964 static DisasJumpType
op_sic(DisasContext
*s
, DisasOps
*o
)
4966 gen_helper_sic(cpu_env
, o
->in1
, o
->in2
);
4970 static DisasJumpType
op_rpcit(DisasContext
*s
, DisasOps
*o
)
4972 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
4973 TCGv_i32 r2
= tcg_constant_i32(get_field(s
, r2
));
4975 gen_helper_rpcit(cpu_env
, r1
, r2
);
4980 static DisasJumpType
op_pcistb(DisasContext
*s
, DisasOps
*o
)
4982 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
4983 TCGv_i32 r3
= tcg_constant_i32(get_field(s
, r3
));
4984 TCGv_i32 ar
= tcg_constant_i32(get_field(s
, b2
));
4986 gen_helper_pcistb(cpu_env
, r1
, r3
, o
->addr1
, ar
);
4991 static DisasJumpType
op_mpcifc(DisasContext
*s
, DisasOps
*o
)
4993 TCGv_i32 r1
= tcg_constant_i32(get_field(s
, r1
));
4994 TCGv_i32 ar
= tcg_constant_i32(get_field(s
, b2
));
4996 gen_helper_mpcifc(cpu_env
, r1
, o
->addr1
, ar
);
5002 #include "translate_vx.c.inc"
5004 /* ====================================================================== */
5005 /* The "Cc OUTput" generators. Given the generated output (and in some cases
5006 the original inputs), update the various cc data structures in order to
5007 be able to compute the new condition code. */
5009 static void cout_abs32(DisasContext
*s
, DisasOps
*o
)
5011 gen_op_update1_cc_i64(s
, CC_OP_ABS_32
, o
->out
);
5014 static void cout_abs64(DisasContext
*s
, DisasOps
*o
)
5016 gen_op_update1_cc_i64(s
, CC_OP_ABS_64
, o
->out
);
5019 static void cout_adds32(DisasContext
*s
, DisasOps
*o
)
5021 gen_op_update3_cc_i64(s
, CC_OP_ADD_32
, o
->in1
, o
->in2
, o
->out
);
5024 static void cout_adds64(DisasContext
*s
, DisasOps
*o
)
5026 gen_op_update3_cc_i64(s
, CC_OP_ADD_64
, o
->in1
, o
->in2
, o
->out
);
5029 static void cout_addu32(DisasContext
*s
, DisasOps
*o
)
5031 tcg_gen_shri_i64(cc_src
, o
->out
, 32);
5032 tcg_gen_ext32u_i64(cc_dst
, o
->out
);
5033 gen_op_update2_cc_i64(s
, CC_OP_ADDU
, cc_src
, cc_dst
);
5036 static void cout_addu64(DisasContext
*s
, DisasOps
*o
)
5038 gen_op_update2_cc_i64(s
, CC_OP_ADDU
, cc_src
, o
->out
);
5041 static void cout_cmps32(DisasContext
*s
, DisasOps
*o
)
5043 gen_op_update2_cc_i64(s
, CC_OP_LTGT_32
, o
->in1
, o
->in2
);
5046 static void cout_cmps64(DisasContext
*s
, DisasOps
*o
)
5048 gen_op_update2_cc_i64(s
, CC_OP_LTGT_64
, o
->in1
, o
->in2
);
5051 static void cout_cmpu32(DisasContext
*s
, DisasOps
*o
)
5053 gen_op_update2_cc_i64(s
, CC_OP_LTUGTU_32
, o
->in1
, o
->in2
);
5056 static void cout_cmpu64(DisasContext
*s
, DisasOps
*o
)
5058 gen_op_update2_cc_i64(s
, CC_OP_LTUGTU_64
, o
->in1
, o
->in2
);
5061 static void cout_f32(DisasContext
*s
, DisasOps
*o
)
5063 gen_op_update1_cc_i64(s
, CC_OP_NZ_F32
, o
->out
);
5066 static void cout_f64(DisasContext
*s
, DisasOps
*o
)
5068 gen_op_update1_cc_i64(s
, CC_OP_NZ_F64
, o
->out
);
5071 static void cout_f128(DisasContext
*s
, DisasOps
*o
)
5073 gen_op_update2_cc_i64(s
, CC_OP_NZ_F128
, o
->out
, o
->out2
);
5076 static void cout_nabs32(DisasContext
*s
, DisasOps
*o
)
5078 gen_op_update1_cc_i64(s
, CC_OP_NABS_32
, o
->out
);
5081 static void cout_nabs64(DisasContext
*s
, DisasOps
*o
)
5083 gen_op_update1_cc_i64(s
, CC_OP_NABS_64
, o
->out
);
5086 static void cout_neg32(DisasContext
*s
, DisasOps
*o
)
5088 gen_op_update1_cc_i64(s
, CC_OP_COMP_32
, o
->out
);
5091 static void cout_neg64(DisasContext
*s
, DisasOps
*o
)
5093 gen_op_update1_cc_i64(s
, CC_OP_COMP_64
, o
->out
);
5096 static void cout_nz32(DisasContext
*s
, DisasOps
*o
)
5098 tcg_gen_ext32u_i64(cc_dst
, o
->out
);
5099 gen_op_update1_cc_i64(s
, CC_OP_NZ
, cc_dst
);
5102 static void cout_nz64(DisasContext
*s
, DisasOps
*o
)
5104 gen_op_update1_cc_i64(s
, CC_OP_NZ
, o
->out
);
5107 static void cout_s32(DisasContext
*s
, DisasOps
*o
)
5109 gen_op_update1_cc_i64(s
, CC_OP_LTGT0_32
, o
->out
);
5112 static void cout_s64(DisasContext
*s
, DisasOps
*o
)
5114 gen_op_update1_cc_i64(s
, CC_OP_LTGT0_64
, o
->out
);
5117 static void cout_subs32(DisasContext
*s
, DisasOps
*o
)
5119 gen_op_update3_cc_i64(s
, CC_OP_SUB_32
, o
->in1
, o
->in2
, o
->out
);
5122 static void cout_subs64(DisasContext
*s
, DisasOps
*o
)
5124 gen_op_update3_cc_i64(s
, CC_OP_SUB_64
, o
->in1
, o
->in2
, o
->out
);
5127 static void cout_subu32(DisasContext
*s
, DisasOps
*o
)
5129 tcg_gen_sari_i64(cc_src
, o
->out
, 32);
5130 tcg_gen_ext32u_i64(cc_dst
, o
->out
);
5131 gen_op_update2_cc_i64(s
, CC_OP_SUBU
, cc_src
, cc_dst
);
5134 static void cout_subu64(DisasContext
*s
, DisasOps
*o
)
5136 gen_op_update2_cc_i64(s
, CC_OP_SUBU
, cc_src
, o
->out
);
5139 static void cout_tm32(DisasContext
*s
, DisasOps
*o
)
5141 gen_op_update2_cc_i64(s
, CC_OP_TM_32
, o
->in1
, o
->in2
);
5144 static void cout_tm64(DisasContext
*s
, DisasOps
*o
)
5146 gen_op_update2_cc_i64(s
, CC_OP_TM_64
, o
->in1
, o
->in2
);
5149 static void cout_muls32(DisasContext
*s
, DisasOps
*o
)
5151 gen_op_update1_cc_i64(s
, CC_OP_MULS_32
, o
->out
);
5154 static void cout_muls64(DisasContext
*s
, DisasOps
*o
)
5156 /* out contains "high" part, out2 contains "low" part of 128 bit result */
5157 gen_op_update2_cc_i64(s
, CC_OP_MULS_64
, o
->out
, o
->out2
);
5160 /* ====================================================================== */
5161 /* The "PREParation" generators. These initialize the DisasOps.OUT fields
5162 with the TCG register to which we will write. Used in combination with
5163 the "wout" generators, in some cases we need a new temporary, and in
5164 some cases we can write to a TCG global. */
5166 static void prep_new(DisasContext
*s
, DisasOps
*o
)
5168 o
->out
= tcg_temp_new_i64();
5170 #define SPEC_prep_new 0
5172 static void prep_new_P(DisasContext
*s
, DisasOps
*o
)
5174 o
->out
= tcg_temp_new_i64();
5175 o
->out2
= tcg_temp_new_i64();
5177 #define SPEC_prep_new_P 0
5179 static void prep_new_x(DisasContext
*s
, DisasOps
*o
)
5181 o
->out_128
= tcg_temp_new_i128();
5183 #define SPEC_prep_new_x 0
5185 static void prep_r1(DisasContext
*s
, DisasOps
*o
)
5187 o
->out
= regs
[get_field(s
, r1
)];
5189 #define SPEC_prep_r1 0
5191 static void prep_r1_P(DisasContext
*s
, DisasOps
*o
)
5193 int r1
= get_field(s
, r1
);
5195 o
->out2
= regs
[r1
+ 1];
5197 #define SPEC_prep_r1_P SPEC_r1_even
5199 /* ====================================================================== */
5200 /* The "Write OUTput" generators. These generally perform some non-trivial
5201 copy of data to TCG globals, or to main memory. The trivial cases are
5202 generally handled by having a "prep" generator install the TCG global
5203 as the destination of the operation. */
5205 static void wout_r1(DisasContext
*s
, DisasOps
*o
)
5207 store_reg(get_field(s
, r1
), o
->out
);
5209 #define SPEC_wout_r1 0
5211 static void wout_out2_r1(DisasContext
*s
, DisasOps
*o
)
5213 store_reg(get_field(s
, r1
), o
->out2
);
5215 #define SPEC_wout_out2_r1 0
5217 static void wout_r1_8(DisasContext
*s
, DisasOps
*o
)
5219 int r1
= get_field(s
, r1
);
5220 tcg_gen_deposit_i64(regs
[r1
], regs
[r1
], o
->out
, 0, 8);
5222 #define SPEC_wout_r1_8 0
5224 static void wout_r1_16(DisasContext
*s
, DisasOps
*o
)
5226 int r1
= get_field(s
, r1
);
5227 tcg_gen_deposit_i64(regs
[r1
], regs
[r1
], o
->out
, 0, 16);
5229 #define SPEC_wout_r1_16 0
5231 static void wout_r1_32(DisasContext
*s
, DisasOps
*o
)
5233 store_reg32_i64(get_field(s
, r1
), o
->out
);
5235 #define SPEC_wout_r1_32 0
5237 static void wout_r1_32h(DisasContext
*s
, DisasOps
*o
)
5239 store_reg32h_i64(get_field(s
, r1
), o
->out
);
5241 #define SPEC_wout_r1_32h 0
5243 static void wout_r1_P32(DisasContext
*s
, DisasOps
*o
)
5245 int r1
= get_field(s
, r1
);
5246 store_reg32_i64(r1
, o
->out
);
5247 store_reg32_i64(r1
+ 1, o
->out2
);
5249 #define SPEC_wout_r1_P32 SPEC_r1_even
5251 static void wout_r1_D32(DisasContext
*s
, DisasOps
*o
)
5253 int r1
= get_field(s
, r1
);
5254 TCGv_i64 t
= tcg_temp_new_i64();
5255 store_reg32_i64(r1
+ 1, o
->out
);
5256 tcg_gen_shri_i64(t
, o
->out
, 32);
5257 store_reg32_i64(r1
, t
);
5259 #define SPEC_wout_r1_D32 SPEC_r1_even
5261 static void wout_r1_D64(DisasContext
*s
, DisasOps
*o
)
5263 int r1
= get_field(s
, r1
);
5264 tcg_gen_extr_i128_i64(regs
[r1
+ 1], regs
[r1
], o
->out_128
);
5266 #define SPEC_wout_r1_D64 SPEC_r1_even
5268 static void wout_r3_P32(DisasContext
*s
, DisasOps
*o
)
5270 int r3
= get_field(s
, r3
);
5271 store_reg32_i64(r3
, o
->out
);
5272 store_reg32_i64(r3
+ 1, o
->out2
);
5274 #define SPEC_wout_r3_P32 SPEC_r3_even
5276 static void wout_r3_P64(DisasContext
*s
, DisasOps
*o
)
5278 int r3
= get_field(s
, r3
);
5279 store_reg(r3
, o
->out
);
5280 store_reg(r3
+ 1, o
->out2
);
5282 #define SPEC_wout_r3_P64 SPEC_r3_even
5284 static void wout_e1(DisasContext
*s
, DisasOps
*o
)
5286 store_freg32_i64(get_field(s
, r1
), o
->out
);
5288 #define SPEC_wout_e1 0
5290 static void wout_f1(DisasContext
*s
, DisasOps
*o
)
5292 store_freg(get_field(s
, r1
), o
->out
);
5294 #define SPEC_wout_f1 0
5296 static void wout_x1(DisasContext
*s
, DisasOps
*o
)
5298 int f1
= get_field(s
, r1
);
5300 /* Split out_128 into out+out2 for cout_f128. */
5301 tcg_debug_assert(o
->out
== NULL
);
5302 o
->out
= tcg_temp_new_i64();
5303 o
->out2
= tcg_temp_new_i64();
5305 tcg_gen_extr_i128_i64(o
->out2
, o
->out
, o
->out_128
);
5306 store_freg(f1
, o
->out
);
5307 store_freg(f1
+ 2, o
->out2
);
5309 #define SPEC_wout_x1 SPEC_r1_f128
5311 static void wout_x1_P(DisasContext
*s
, DisasOps
*o
)
5313 int f1
= get_field(s
, r1
);
5314 store_freg(f1
, o
->out
);
5315 store_freg(f1
+ 2, o
->out2
);
5317 #define SPEC_wout_x1_P SPEC_r1_f128
5319 static void wout_cond_r1r2_32(DisasContext
*s
, DisasOps
*o
)
5321 if (get_field(s
, r1
) != get_field(s
, r2
)) {
5322 store_reg32_i64(get_field(s
, r1
), o
->out
);
5325 #define SPEC_wout_cond_r1r2_32 0
5327 static void wout_cond_e1e2(DisasContext
*s
, DisasOps
*o
)
5329 if (get_field(s
, r1
) != get_field(s
, r2
)) {
5330 store_freg32_i64(get_field(s
, r1
), o
->out
);
5333 #define SPEC_wout_cond_e1e2 0
5335 static void wout_m1_8(DisasContext
*s
, DisasOps
*o
)
5337 tcg_gen_qemu_st_i64(o
->out
, o
->addr1
, get_mem_index(s
), MO_UB
);
5339 #define SPEC_wout_m1_8 0
5341 static void wout_m1_16(DisasContext
*s
, DisasOps
*o
)
5343 tcg_gen_qemu_st_i64(o
->out
, o
->addr1
, get_mem_index(s
), MO_TEUW
);
5345 #define SPEC_wout_m1_16 0
5347 #ifndef CONFIG_USER_ONLY
5348 static void wout_m1_16a(DisasContext
*s
, DisasOps
*o
)
5350 tcg_gen_qemu_st_tl(o
->out
, o
->addr1
, get_mem_index(s
), MO_TEUW
| MO_ALIGN
);
5352 #define SPEC_wout_m1_16a 0
5355 static void wout_m1_32(DisasContext
*s
, DisasOps
*o
)
5357 tcg_gen_qemu_st_i64(o
->out
, o
->addr1
, get_mem_index(s
), MO_TEUL
);
5359 #define SPEC_wout_m1_32 0
5361 #ifndef CONFIG_USER_ONLY
5362 static void wout_m1_32a(DisasContext
*s
, DisasOps
*o
)
5364 tcg_gen_qemu_st_tl(o
->out
, o
->addr1
, get_mem_index(s
), MO_TEUL
| MO_ALIGN
);
5366 #define SPEC_wout_m1_32a 0
5369 static void wout_m1_64(DisasContext
*s
, DisasOps
*o
)
5371 tcg_gen_qemu_st_i64(o
->out
, o
->addr1
, get_mem_index(s
), MO_TEUQ
);
5373 #define SPEC_wout_m1_64 0
5375 #ifndef CONFIG_USER_ONLY
5376 static void wout_m1_64a(DisasContext
*s
, DisasOps
*o
)
5378 tcg_gen_qemu_st_i64(o
->out
, o
->addr1
, get_mem_index(s
), MO_TEUQ
| MO_ALIGN
);
5380 #define SPEC_wout_m1_64a 0
5383 static void wout_m2_32(DisasContext
*s
, DisasOps
*o
)
5385 tcg_gen_qemu_st_i64(o
->out
, o
->in2
, get_mem_index(s
), MO_TEUL
);
5387 #define SPEC_wout_m2_32 0
5389 static void wout_in2_r1(DisasContext
*s
, DisasOps
*o
)
5391 store_reg(get_field(s
, r1
), o
->in2
);
5393 #define SPEC_wout_in2_r1 0
5395 static void wout_in2_r1_32(DisasContext
*s
, DisasOps
*o
)
5397 store_reg32_i64(get_field(s
, r1
), o
->in2
);
5399 #define SPEC_wout_in2_r1_32 0
5401 /* ====================================================================== */
5402 /* The "INput 1" generators. These load the first operand to an insn. */
5404 static void in1_r1(DisasContext
*s
, DisasOps
*o
)
5406 o
->in1
= load_reg(get_field(s
, r1
));
5408 #define SPEC_in1_r1 0
5410 static void in1_r1_o(DisasContext
*s
, DisasOps
*o
)
5412 o
->in1
= regs
[get_field(s
, r1
)];
5414 #define SPEC_in1_r1_o 0
5416 static void in1_r1_32s(DisasContext
*s
, DisasOps
*o
)
5418 o
->in1
= tcg_temp_new_i64();
5419 tcg_gen_ext32s_i64(o
->in1
, regs
[get_field(s
, r1
)]);
5421 #define SPEC_in1_r1_32s 0
5423 static void in1_r1_32u(DisasContext
*s
, DisasOps
*o
)
5425 o
->in1
= tcg_temp_new_i64();
5426 tcg_gen_ext32u_i64(o
->in1
, regs
[get_field(s
, r1
)]);
5428 #define SPEC_in1_r1_32u 0
5430 static void in1_r1_sr32(DisasContext
*s
, DisasOps
*o
)
5432 o
->in1
= tcg_temp_new_i64();
5433 tcg_gen_shri_i64(o
->in1
, regs
[get_field(s
, r1
)], 32);
5435 #define SPEC_in1_r1_sr32 0
5437 static void in1_r1p1(DisasContext
*s
, DisasOps
*o
)
5439 o
->in1
= load_reg(get_field(s
, r1
) + 1);
5441 #define SPEC_in1_r1p1 SPEC_r1_even
5443 static void in1_r1p1_o(DisasContext
*s
, DisasOps
*o
)
5445 o
->in1
= regs
[get_field(s
, r1
) + 1];
5447 #define SPEC_in1_r1p1_o SPEC_r1_even
5449 static void in1_r1p1_32s(DisasContext
*s
, DisasOps
*o
)
5451 o
->in1
= tcg_temp_new_i64();
5452 tcg_gen_ext32s_i64(o
->in1
, regs
[get_field(s
, r1
) + 1]);
5454 #define SPEC_in1_r1p1_32s SPEC_r1_even
5456 static void in1_r1p1_32u(DisasContext
*s
, DisasOps
*o
)
5458 o
->in1
= tcg_temp_new_i64();
5459 tcg_gen_ext32u_i64(o
->in1
, regs
[get_field(s
, r1
) + 1]);
5461 #define SPEC_in1_r1p1_32u SPEC_r1_even
5463 static void in1_r1_D32(DisasContext
*s
, DisasOps
*o
)
5465 int r1
= get_field(s
, r1
);
5466 o
->in1
= tcg_temp_new_i64();
5467 tcg_gen_concat32_i64(o
->in1
, regs
[r1
+ 1], regs
[r1
]);
5469 #define SPEC_in1_r1_D32 SPEC_r1_even
5471 static void in1_r2(DisasContext
*s
, DisasOps
*o
)
5473 o
->in1
= load_reg(get_field(s
, r2
));
5475 #define SPEC_in1_r2 0
5477 static void in1_r2_sr32(DisasContext
*s
, DisasOps
*o
)
5479 o
->in1
= tcg_temp_new_i64();
5480 tcg_gen_shri_i64(o
->in1
, regs
[get_field(s
, r2
)], 32);
5482 #define SPEC_in1_r2_sr32 0
5484 static void in1_r2_32u(DisasContext
*s
, DisasOps
*o
)
5486 o
->in1
= tcg_temp_new_i64();
5487 tcg_gen_ext32u_i64(o
->in1
, regs
[get_field(s
, r2
)]);
5489 #define SPEC_in1_r2_32u 0
5491 static void in1_r3(DisasContext
*s
, DisasOps
*o
)
5493 o
->in1
= load_reg(get_field(s
, r3
));
5495 #define SPEC_in1_r3 0
5497 static void in1_r3_o(DisasContext
*s
, DisasOps
*o
)
5499 o
->in1
= regs
[get_field(s
, r3
)];
5501 #define SPEC_in1_r3_o 0
5503 static void in1_r3_32s(DisasContext
*s
, DisasOps
*o
)
5505 o
->in1
= tcg_temp_new_i64();
5506 tcg_gen_ext32s_i64(o
->in1
, regs
[get_field(s
, r3
)]);
5508 #define SPEC_in1_r3_32s 0
5510 static void in1_r3_32u(DisasContext
*s
, DisasOps
*o
)
5512 o
->in1
= tcg_temp_new_i64();
5513 tcg_gen_ext32u_i64(o
->in1
, regs
[get_field(s
, r3
)]);
5515 #define SPEC_in1_r3_32u 0
5517 static void in1_r3_D32(DisasContext
*s
, DisasOps
*o
)
5519 int r3
= get_field(s
, r3
);
5520 o
->in1
= tcg_temp_new_i64();
5521 tcg_gen_concat32_i64(o
->in1
, regs
[r3
+ 1], regs
[r3
]);
5523 #define SPEC_in1_r3_D32 SPEC_r3_even
5525 static void in1_r3_sr32(DisasContext
*s
, DisasOps
*o
)
5527 o
->in1
= tcg_temp_new_i64();
5528 tcg_gen_shri_i64(o
->in1
, regs
[get_field(s
, r3
)], 32);
5530 #define SPEC_in1_r3_sr32 0
5532 static void in1_e1(DisasContext
*s
, DisasOps
*o
)
5534 o
->in1
= load_freg32_i64(get_field(s
, r1
));
5536 #define SPEC_in1_e1 0
5538 static void in1_f1(DisasContext
*s
, DisasOps
*o
)
5540 o
->in1
= load_freg(get_field(s
, r1
));
5542 #define SPEC_in1_f1 0
5544 static void in1_x1(DisasContext
*s
, DisasOps
*o
)
5546 o
->in1_128
= load_freg_128(get_field(s
, r1
));
5548 #define SPEC_in1_x1 SPEC_r1_f128
5550 /* Load the high double word of an extended (128-bit) format FP number */
5551 static void in1_x2h(DisasContext
*s
, DisasOps
*o
)
5553 o
->in1
= load_freg(get_field(s
, r2
));
5555 #define SPEC_in1_x2h SPEC_r2_f128
5557 static void in1_f3(DisasContext
*s
, DisasOps
*o
)
5559 o
->in1
= load_freg(get_field(s
, r3
));
5561 #define SPEC_in1_f3 0
5563 static void in1_la1(DisasContext
*s
, DisasOps
*o
)
5565 o
->addr1
= get_address(s
, 0, get_field(s
, b1
), get_field(s
, d1
));
5567 #define SPEC_in1_la1 0
5569 static void in1_la2(DisasContext
*s
, DisasOps
*o
)
5571 int x2
= have_field(s
, x2
) ? get_field(s
, x2
) : 0;
5572 o
->addr1
= get_address(s
, x2
, get_field(s
, b2
), get_field(s
, d2
));
5574 #define SPEC_in1_la2 0
5576 static void in1_m1_8u(DisasContext
*s
, DisasOps
*o
)
5579 o
->in1
= tcg_temp_new_i64();
5580 tcg_gen_qemu_ld_i64(o
->in1
, o
->addr1
, get_mem_index(s
), MO_UB
);
5582 #define SPEC_in1_m1_8u 0
5584 static void in1_m1_16s(DisasContext
*s
, DisasOps
*o
)
5587 o
->in1
= tcg_temp_new_i64();
5588 tcg_gen_qemu_ld_i64(o
->in1
, o
->addr1
, get_mem_index(s
), MO_TESW
);
5590 #define SPEC_in1_m1_16s 0
5592 static void in1_m1_16u(DisasContext
*s
, DisasOps
*o
)
5595 o
->in1
= tcg_temp_new_i64();
5596 tcg_gen_qemu_ld_i64(o
->in1
, o
->addr1
, get_mem_index(s
), MO_TEUW
);
5598 #define SPEC_in1_m1_16u 0
5600 static void in1_m1_32s(DisasContext
*s
, DisasOps
*o
)
5603 o
->in1
= tcg_temp_new_i64();
5604 tcg_gen_qemu_ld_i64(o
->in1
, o
->addr1
, get_mem_index(s
), MO_TESL
);
5606 #define SPEC_in1_m1_32s 0
5608 static void in1_m1_32u(DisasContext
*s
, DisasOps
*o
)
5611 o
->in1
= tcg_temp_new_i64();
5612 tcg_gen_qemu_ld_i64(o
->in1
, o
->addr1
, get_mem_index(s
), MO_TEUL
);
5614 #define SPEC_in1_m1_32u 0
5616 static void in1_m1_64(DisasContext
*s
, DisasOps
*o
)
5619 o
->in1
= tcg_temp_new_i64();
5620 tcg_gen_qemu_ld_i64(o
->in1
, o
->addr1
, get_mem_index(s
), MO_TEUQ
);
5622 #define SPEC_in1_m1_64 0
5624 /* ====================================================================== */
5625 /* The "INput 2" generators. These load the second operand to an insn. */
5627 static void in2_r1_o(DisasContext
*s
, DisasOps
*o
)
5629 o
->in2
= regs
[get_field(s
, r1
)];
5631 #define SPEC_in2_r1_o 0
5633 static void in2_r1_16u(DisasContext
*s
, DisasOps
*o
)
5635 o
->in2
= tcg_temp_new_i64();
5636 tcg_gen_ext16u_i64(o
->in2
, regs
[get_field(s
, r1
)]);
5638 #define SPEC_in2_r1_16u 0
5640 static void in2_r1_32u(DisasContext
*s
, DisasOps
*o
)
5642 o
->in2
= tcg_temp_new_i64();
5643 tcg_gen_ext32u_i64(o
->in2
, regs
[get_field(s
, r1
)]);
5645 #define SPEC_in2_r1_32u 0
5647 static void in2_r1_D32(DisasContext
*s
, DisasOps
*o
)
5649 int r1
= get_field(s
, r1
);
5650 o
->in2
= tcg_temp_new_i64();
5651 tcg_gen_concat32_i64(o
->in2
, regs
[r1
+ 1], regs
[r1
]);
5653 #define SPEC_in2_r1_D32 SPEC_r1_even
5655 static void in2_r2(DisasContext
*s
, DisasOps
*o
)
5657 o
->in2
= load_reg(get_field(s
, r2
));
5659 #define SPEC_in2_r2 0
5661 static void in2_r2_o(DisasContext
*s
, DisasOps
*o
)
5663 o
->in2
= regs
[get_field(s
, r2
)];
5665 #define SPEC_in2_r2_o 0
5667 static void in2_r2_nz(DisasContext
*s
, DisasOps
*o
)
5669 int r2
= get_field(s
, r2
);
5671 o
->in2
= load_reg(r2
);
5674 #define SPEC_in2_r2_nz 0
5676 static void in2_r2_8s(DisasContext
*s
, DisasOps
*o
)
5678 o
->in2
= tcg_temp_new_i64();
5679 tcg_gen_ext8s_i64(o
->in2
, regs
[get_field(s
, r2
)]);
5681 #define SPEC_in2_r2_8s 0
5683 static void in2_r2_8u(DisasContext
*s
, DisasOps
*o
)
5685 o
->in2
= tcg_temp_new_i64();
5686 tcg_gen_ext8u_i64(o
->in2
, regs
[get_field(s
, r2
)]);
5688 #define SPEC_in2_r2_8u 0
5690 static void in2_r2_16s(DisasContext
*s
, DisasOps
*o
)
5692 o
->in2
= tcg_temp_new_i64();
5693 tcg_gen_ext16s_i64(o
->in2
, regs
[get_field(s
, r2
)]);
5695 #define SPEC_in2_r2_16s 0
5697 static void in2_r2_16u(DisasContext
*s
, DisasOps
*o
)
5699 o
->in2
= tcg_temp_new_i64();
5700 tcg_gen_ext16u_i64(o
->in2
, regs
[get_field(s
, r2
)]);
5702 #define SPEC_in2_r2_16u 0
5704 static void in2_r3(DisasContext
*s
, DisasOps
*o
)
5706 o
->in2
= load_reg(get_field(s
, r3
));
5708 #define SPEC_in2_r3 0
5710 static void in2_r3_D64(DisasContext
*s
, DisasOps
*o
)
5712 int r3
= get_field(s
, r3
);
5713 o
->in2_128
= tcg_temp_new_i128();
5714 tcg_gen_concat_i64_i128(o
->in2_128
, regs
[r3
+ 1], regs
[r3
]);
5716 #define SPEC_in2_r3_D64 SPEC_r3_even
5718 static void in2_r3_sr32(DisasContext
*s
, DisasOps
*o
)
5720 o
->in2
= tcg_temp_new_i64();
5721 tcg_gen_shri_i64(o
->in2
, regs
[get_field(s
, r3
)], 32);
5723 #define SPEC_in2_r3_sr32 0
5725 static void in2_r3_32u(DisasContext
*s
, DisasOps
*o
)
5727 o
->in2
= tcg_temp_new_i64();
5728 tcg_gen_ext32u_i64(o
->in2
, regs
[get_field(s
, r3
)]);
5730 #define SPEC_in2_r3_32u 0
5732 static void in2_r2_32s(DisasContext
*s
, DisasOps
*o
)
5734 o
->in2
= tcg_temp_new_i64();
5735 tcg_gen_ext32s_i64(o
->in2
, regs
[get_field(s
, r2
)]);
5737 #define SPEC_in2_r2_32s 0
5739 static void in2_r2_32u(DisasContext
*s
, DisasOps
*o
)
5741 o
->in2
= tcg_temp_new_i64();
5742 tcg_gen_ext32u_i64(o
->in2
, regs
[get_field(s
, r2
)]);
5744 #define SPEC_in2_r2_32u 0
5746 static void in2_r2_sr32(DisasContext
*s
, DisasOps
*o
)
5748 o
->in2
= tcg_temp_new_i64();
5749 tcg_gen_shri_i64(o
->in2
, regs
[get_field(s
, r2
)], 32);
5751 #define SPEC_in2_r2_sr32 0
5753 static void in2_e2(DisasContext
*s
, DisasOps
*o
)
5755 o
->in2
= load_freg32_i64(get_field(s
, r2
));
5757 #define SPEC_in2_e2 0
5759 static void in2_f2(DisasContext
*s
, DisasOps
*o
)
5761 o
->in2
= load_freg(get_field(s
, r2
));
5763 #define SPEC_in2_f2 0
5765 static void in2_x2(DisasContext
*s
, DisasOps
*o
)
5767 o
->in2_128
= load_freg_128(get_field(s
, r2
));
5769 #define SPEC_in2_x2 SPEC_r2_f128
5771 /* Load the low double word of an extended (128-bit) format FP number */
5772 static void in2_x2l(DisasContext
*s
, DisasOps
*o
)
5774 o
->in2
= load_freg(get_field(s
, r2
) + 2);
5776 #define SPEC_in2_x2l SPEC_r2_f128
5778 static void in2_ra2(DisasContext
*s
, DisasOps
*o
)
5780 int r2
= get_field(s
, r2
);
5782 /* Note: *don't* treat !r2 as 0, use the reg value. */
5783 o
->in2
= tcg_temp_new_i64();
5784 gen_addi_and_wrap_i64(s
, o
->in2
, regs
[r2
], 0);
5786 #define SPEC_in2_ra2 0
5788 static void in2_ra2_E(DisasContext
*s
, DisasOps
*o
)
5790 return in2_ra2(s
, o
);
5792 #define SPEC_in2_ra2_E SPEC_r2_even
5794 static void in2_a2(DisasContext
*s
, DisasOps
*o
)
5796 int x2
= have_field(s
, x2
) ? get_field(s
, x2
) : 0;
5797 o
->in2
= get_address(s
, x2
, get_field(s
, b2
), get_field(s
, d2
));
5799 #define SPEC_in2_a2 0
5801 static TCGv
gen_ri2(DisasContext
*s
)
5807 disas_jdest(s
, i2
, is_imm
, imm
, ri2
);
5809 ri2
= tcg_constant_i64(s
->base
.pc_next
+ (int64_t)imm
* 2);
5815 static void in2_ri2(DisasContext
*s
, DisasOps
*o
)
5817 o
->in2
= gen_ri2(s
);
5819 #define SPEC_in2_ri2 0
5821 static void in2_sh(DisasContext
*s
, DisasOps
*o
)
5823 int b2
= get_field(s
, b2
);
5824 int d2
= get_field(s
, d2
);
5827 o
->in2
= tcg_constant_i64(d2
& 0x3f);
5829 o
->in2
= get_address(s
, 0, b2
, d2
);
5830 tcg_gen_andi_i64(o
->in2
, o
->in2
, 0x3f);
5833 #define SPEC_in2_sh 0
5835 static void in2_m2_8u(DisasContext
*s
, DisasOps
*o
)
5838 tcg_gen_qemu_ld_i64(o
->in2
, o
->in2
, get_mem_index(s
), MO_UB
);
5840 #define SPEC_in2_m2_8u 0
5842 static void in2_m2_16s(DisasContext
*s
, DisasOps
*o
)
5845 tcg_gen_qemu_ld_i64(o
->in2
, o
->in2
, get_mem_index(s
), MO_TESW
);
5847 #define SPEC_in2_m2_16s 0
5849 static void in2_m2_16u(DisasContext
*s
, DisasOps
*o
)
5852 tcg_gen_qemu_ld_i64(o
->in2
, o
->in2
, get_mem_index(s
), MO_TEUW
);
5854 #define SPEC_in2_m2_16u 0
5856 static void in2_m2_32s(DisasContext
*s
, DisasOps
*o
)
5859 tcg_gen_qemu_ld_i64(o
->in2
, o
->in2
, get_mem_index(s
), MO_TESL
);
5861 #define SPEC_in2_m2_32s 0
5863 static void in2_m2_32u(DisasContext
*s
, DisasOps
*o
)
5866 tcg_gen_qemu_ld_i64(o
->in2
, o
->in2
, get_mem_index(s
), MO_TEUL
);
5868 #define SPEC_in2_m2_32u 0
5870 #ifndef CONFIG_USER_ONLY
5871 static void in2_m2_32ua(DisasContext
*s
, DisasOps
*o
)
5874 tcg_gen_qemu_ld_tl(o
->in2
, o
->in2
, get_mem_index(s
), MO_TEUL
| MO_ALIGN
);
5876 #define SPEC_in2_m2_32ua 0
5879 static void in2_m2_64(DisasContext
*s
, DisasOps
*o
)
5882 tcg_gen_qemu_ld_i64(o
->in2
, o
->in2
, get_mem_index(s
), MO_TEUQ
);
5884 #define SPEC_in2_m2_64 0
5886 static void in2_m2_64w(DisasContext
*s
, DisasOps
*o
)
5889 tcg_gen_qemu_ld_i64(o
->in2
, o
->in2
, get_mem_index(s
), MO_TEUQ
);
5890 gen_addi_and_wrap_i64(s
, o
->in2
, o
->in2
, 0);
5892 #define SPEC_in2_m2_64w 0
5894 #ifndef CONFIG_USER_ONLY
5895 static void in2_m2_64a(DisasContext
*s
, DisasOps
*o
)
5898 tcg_gen_qemu_ld_i64(o
->in2
, o
->in2
, get_mem_index(s
), MO_TEUQ
| MO_ALIGN
);
5900 #define SPEC_in2_m2_64a 0
5903 static void in2_mri2_16s(DisasContext
*s
, DisasOps
*o
)
5905 o
->in2
= tcg_temp_new_i64();
5906 tcg_gen_qemu_ld_i64(o
->in2
, gen_ri2(s
), get_mem_index(s
), MO_TESW
);
5908 #define SPEC_in2_mri2_16s 0
5910 static void in2_mri2_16u(DisasContext
*s
, DisasOps
*o
)
5912 o
->in2
= tcg_temp_new_i64();
5913 tcg_gen_qemu_ld_i64(o
->in2
, gen_ri2(s
), get_mem_index(s
), MO_TEUW
);
5915 #define SPEC_in2_mri2_16u 0
5917 static void in2_mri2_32s(DisasContext
*s
, DisasOps
*o
)
5919 o
->in2
= tcg_temp_new_i64();
5920 tcg_gen_qemu_ld_tl(o
->in2
, gen_ri2(s
), get_mem_index(s
),
5921 MO_TESL
| MO_ALIGN
);
5923 #define SPEC_in2_mri2_32s 0
5925 static void in2_mri2_32u(DisasContext
*s
, DisasOps
*o
)
5927 o
->in2
= tcg_temp_new_i64();
5928 tcg_gen_qemu_ld_tl(o
->in2
, gen_ri2(s
), get_mem_index(s
),
5929 MO_TEUL
| MO_ALIGN
);
5931 #define SPEC_in2_mri2_32u 0
5933 static void in2_mri2_64(DisasContext
*s
, DisasOps
*o
)
5935 o
->in2
= tcg_temp_new_i64();
5936 tcg_gen_qemu_ld_i64(o
->in2
, gen_ri2(s
), get_mem_index(s
),
5937 MO_TEUQ
| MO_ALIGN
);
5939 #define SPEC_in2_mri2_64 0
5941 static void in2_i2(DisasContext
*s
, DisasOps
*o
)
5943 o
->in2
= tcg_constant_i64(get_field(s
, i2
));
5945 #define SPEC_in2_i2 0
5947 static void in2_i2_8u(DisasContext
*s
, DisasOps
*o
)
5949 o
->in2
= tcg_constant_i64((uint8_t)get_field(s
, i2
));
5951 #define SPEC_in2_i2_8u 0
5953 static void in2_i2_16u(DisasContext
*s
, DisasOps
*o
)
5955 o
->in2
= tcg_constant_i64((uint16_t)get_field(s
, i2
));
5957 #define SPEC_in2_i2_16u 0
5959 static void in2_i2_32u(DisasContext
*s
, DisasOps
*o
)
5961 o
->in2
= tcg_constant_i64((uint32_t)get_field(s
, i2
));
5963 #define SPEC_in2_i2_32u 0
5965 static void in2_i2_16u_shl(DisasContext
*s
, DisasOps
*o
)
5967 uint64_t i2
= (uint16_t)get_field(s
, i2
);
5968 o
->in2
= tcg_constant_i64(i2
<< s
->insn
->data
);
5970 #define SPEC_in2_i2_16u_shl 0
5972 static void in2_i2_32u_shl(DisasContext
*s
, DisasOps
*o
)
5974 uint64_t i2
= (uint32_t)get_field(s
, i2
);
5975 o
->in2
= tcg_constant_i64(i2
<< s
->insn
->data
);
5977 #define SPEC_in2_i2_32u_shl 0
5979 #ifndef CONFIG_USER_ONLY
5980 static void in2_insn(DisasContext
*s
, DisasOps
*o
)
5982 o
->in2
= tcg_constant_i64(s
->fields
.raw_insn
);
5984 #define SPEC_in2_insn 0
5987 /* ====================================================================== */
5989 /* Find opc within the table of insns. This is formulated as a switch
5990 statement so that (1) we get compile-time notice of cut-paste errors
5991 for duplicated opcodes, and (2) the compiler generates the binary
5992 search tree, rather than us having to post-process the table. */
5994 #define C(OPC, NM, FT, FC, I1, I2, P, W, OP, CC) \
5995 E(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, 0, 0)
5997 #define D(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D) \
5998 E(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D, 0)
6000 #define F(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, FL) \
6001 E(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, 0, FL)
6003 #define E(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D, FL) insn_ ## NM,
6005 enum DisasInsnEnum
{
6006 #include "insn-data.h.inc"
6010 #define E(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D, FL) { \
6015 .spec = SPEC_in1_##I1 | SPEC_in2_##I2 | SPEC_prep_##P | SPEC_wout_##W, \
6017 .help_in1 = in1_##I1, \
6018 .help_in2 = in2_##I2, \
6019 .help_prep = prep_##P, \
6020 .help_wout = wout_##W, \
6021 .help_cout = cout_##CC, \
6022 .help_op = op_##OP, \
6026 /* Allow 0 to be used for NULL in the table below. */
6034 #define SPEC_in1_0 0
6035 #define SPEC_in2_0 0
6036 #define SPEC_prep_0 0
6037 #define SPEC_wout_0 0
6039 /* Give smaller names to the various facilities. */
6040 #define FAC_Z S390_FEAT_ZARCH
6041 #define FAC_CASS S390_FEAT_COMPARE_AND_SWAP_AND_STORE
6042 #define FAC_DFP S390_FEAT_DFP
6043 #define FAC_DFPR S390_FEAT_FLOATING_POINT_SUPPORT_ENH /* DFP-rounding */
6044 #define FAC_DO S390_FEAT_STFLE_45 /* distinct-operands */
6045 #define FAC_EE S390_FEAT_EXECUTE_EXT
6046 #define FAC_EI S390_FEAT_EXTENDED_IMMEDIATE
6047 #define FAC_FPE S390_FEAT_FLOATING_POINT_EXT
6048 #define FAC_FPSSH S390_FEAT_FLOATING_POINT_SUPPORT_ENH /* FPS-sign-handling */
6049 #define FAC_FPRGR S390_FEAT_FLOATING_POINT_SUPPORT_ENH /* FPR-GR-transfer */
6050 #define FAC_GIE S390_FEAT_GENERAL_INSTRUCTIONS_EXT
6051 #define FAC_HFP_MA S390_FEAT_HFP_MADDSUB
6052 #define FAC_HW S390_FEAT_STFLE_45 /* high-word */
6053 #define FAC_IEEEE_SIM S390_FEAT_FLOATING_POINT_SUPPORT_ENH /* IEEE-exception-simulation */
6054 #define FAC_MIE S390_FEAT_STFLE_49 /* misc-instruction-extensions */
6055 #define FAC_LAT S390_FEAT_STFLE_49 /* load-and-trap */
6056 #define FAC_LOC S390_FEAT_STFLE_45 /* load/store on condition 1 */
6057 #define FAC_LOC2 S390_FEAT_STFLE_53 /* load/store on condition 2 */
6058 #define FAC_LD S390_FEAT_LONG_DISPLACEMENT
6059 #define FAC_PC S390_FEAT_STFLE_45 /* population count */
6060 #define FAC_SCF S390_FEAT_STORE_CLOCK_FAST
6061 #define FAC_SFLE S390_FEAT_STFLE
6062 #define FAC_ILA S390_FEAT_STFLE_45 /* interlocked-access-facility 1 */
6063 #define FAC_MVCOS S390_FEAT_MOVE_WITH_OPTIONAL_SPEC
6064 #define FAC_LPP S390_FEAT_SET_PROGRAM_PARAMETERS /* load-program-parameter */
6065 #define FAC_DAT_ENH S390_FEAT_DAT_ENH
6066 #define FAC_E2 S390_FEAT_EXTENDED_TRANSLATION_2
6067 #define FAC_EH S390_FEAT_STFLE_49 /* execution-hint */
6068 #define FAC_PPA S390_FEAT_STFLE_49 /* processor-assist */
6069 #define FAC_LZRB S390_FEAT_STFLE_53 /* load-and-zero-rightmost-byte */
6070 #define FAC_ETF3 S390_FEAT_EXTENDED_TRANSLATION_3
6071 #define FAC_MSA S390_FEAT_MSA /* message-security-assist facility */
6072 #define FAC_MSA3 S390_FEAT_MSA_EXT_3 /* msa-extension-3 facility */
6073 #define FAC_MSA4 S390_FEAT_MSA_EXT_4 /* msa-extension-4 facility */
6074 #define FAC_MSA5 S390_FEAT_MSA_EXT_5 /* msa-extension-5 facility */
6075 #define FAC_MSA8 S390_FEAT_MSA_EXT_8 /* msa-extension-8 facility */
6076 #define FAC_ECT S390_FEAT_EXTRACT_CPU_TIME
6077 #define FAC_PCI S390_FEAT_ZPCI /* z/PCI facility */
6078 #define FAC_AIS S390_FEAT_ADAPTER_INT_SUPPRESSION
6079 #define FAC_V S390_FEAT_VECTOR /* vector facility */
6080 #define FAC_VE S390_FEAT_VECTOR_ENH /* vector enhancements facility 1 */
6081 #define FAC_VE2 S390_FEAT_VECTOR_ENH2 /* vector enhancements facility 2 */
6082 #define FAC_MIE2 S390_FEAT_MISC_INSTRUCTION_EXT2 /* miscellaneous-instruction-extensions facility 2 */
6083 #define FAC_MIE3 S390_FEAT_MISC_INSTRUCTION_EXT3 /* miscellaneous-instruction-extensions facility 3 */
6085 static const DisasInsn insn_info
[] = {
6086 #include "insn-data.h.inc"
6090 #define E(OPC, NM, FT, FC, I1, I2, P, W, OP, CC, D, FL) \
6091 case OPC: return &insn_info[insn_ ## NM];
6093 static const DisasInsn
*lookup_opc(uint16_t opc
)
6096 #include "insn-data.h.inc"
6107 /* Extract a field from the insn. The INSN should be left-aligned in
6108 the uint64_t so that we can more easily utilize the big-bit-endian
6109 definitions we extract from the Principals of Operation. */
6111 static void extract_field(DisasFields
*o
, const DisasField
*f
, uint64_t insn
)
6119 /* Zero extract the field from the insn. */
6120 r
= (insn
<< f
->beg
) >> (64 - f
->size
);
6122 /* Sign-extend, or un-swap the field as necessary. */
6124 case 0: /* unsigned */
6126 case 1: /* signed */
6127 assert(f
->size
<= 32);
6128 m
= 1u << (f
->size
- 1);
6131 case 2: /* dl+dh split, signed 20 bit. */
6132 r
= ((int8_t)r
<< 12) | (r
>> 8);
6134 case 3: /* MSB stored in RXB */
6135 g_assert(f
->size
== 4);
6138 r
|= extract64(insn
, 63 - 36, 1) << 4;
6141 r
|= extract64(insn
, 63 - 37, 1) << 4;
6144 r
|= extract64(insn
, 63 - 38, 1) << 4;
6147 r
|= extract64(insn
, 63 - 39, 1) << 4;
6150 g_assert_not_reached();
6158 * Validate that the "compressed" encoding we selected above is valid.
6159 * I.e. we haven't made two different original fields overlap.
6161 assert(((o
->presentC
>> f
->indexC
) & 1) == 0);
6162 o
->presentC
|= 1 << f
->indexC
;
6163 o
->presentO
|= 1 << f
->indexO
;
6165 o
->c
[f
->indexC
] = r
;
6168 /* Lookup the insn at the current PC, extracting the operands into O and
6169 returning the info struct for the insn. Returns NULL for invalid insn. */
6171 static const DisasInsn
*extract_insn(CPUS390XState
*env
, DisasContext
*s
)
6173 uint64_t insn
, pc
= s
->base
.pc_next
;
6175 const DisasInsn
*info
;
6177 if (unlikely(s
->ex_value
)) {
6178 /* Drop the EX data now, so that it's clear on exception paths. */
6179 tcg_gen_st_i64(tcg_constant_i64(0), cpu_env
,
6180 offsetof(CPUS390XState
, ex_value
));
6182 /* Extract the values saved by EXECUTE. */
6183 insn
= s
->ex_value
& 0xffffffffffff0000ull
;
6184 ilen
= s
->ex_value
& 0xf;
6186 /* Register insn bytes with translator so plugins work. */
6187 for (int i
= 0; i
< ilen
; i
++) {
6188 uint8_t byte
= extract64(insn
, 56 - (i
* 8), 8);
6189 translator_fake_ldb(byte
, pc
+ i
);
6193 insn
= ld_code2(env
, s
, pc
);
6194 op
= (insn
>> 8) & 0xff;
6195 ilen
= get_ilen(op
);
6201 insn
= ld_code4(env
, s
, pc
) << 32;
6204 insn
= (insn
<< 48) | (ld_code4(env
, s
, pc
+ 2) << 16);
6207 g_assert_not_reached();
6210 s
->pc_tmp
= s
->base
.pc_next
+ ilen
;
6213 /* We can't actually determine the insn format until we've looked up
6214 the full insn opcode. Which we can't do without locating the
6215 secondary opcode. Assume by default that OP2 is at bit 40; for
6216 those smaller insns that don't actually have a secondary opcode
6217 this will correctly result in OP2 = 0. */
6223 case 0xb2: /* S, RRF, RRE, IE */
6224 case 0xb3: /* RRE, RRD, RRF */
6225 case 0xb9: /* RRE, RRF */
6226 case 0xe5: /* SSE, SIL */
6227 op2
= (insn
<< 8) >> 56;
6231 case 0xc0: /* RIL */
6232 case 0xc2: /* RIL */
6233 case 0xc4: /* RIL */
6234 case 0xc6: /* RIL */
6235 case 0xc8: /* SSF */
6236 case 0xcc: /* RIL */
6237 op2
= (insn
<< 12) >> 60;
6239 case 0xc5: /* MII */
6240 case 0xc7: /* SMI */
6241 case 0xd0 ... 0xdf: /* SS */
6247 case 0xee ... 0xf3: /* SS */
6248 case 0xf8 ... 0xfd: /* SS */
6252 op2
= (insn
<< 40) >> 56;
6256 memset(&s
->fields
, 0, sizeof(s
->fields
));
6257 s
->fields
.raw_insn
= insn
;
6259 s
->fields
.op2
= op2
;
6261 /* Lookup the instruction. */
6262 info
= lookup_opc(op
<< 8 | op2
);
6265 /* If we found it, extract the operands. */
6267 DisasFormat fmt
= info
->fmt
;
6270 for (i
= 0; i
< NUM_C_FIELD
; ++i
) {
6271 extract_field(&s
->fields
, &format_info
[fmt
].op
[i
], insn
);
6277 static bool is_afp_reg(int reg
)
6279 return reg
% 2 || reg
> 6;
6282 static bool is_fp_pair(int reg
)
6284 /* 0,1,4,5,8,9,12,13: to exclude the others, check for single bit */
6285 return !(reg
& 0x2);
6288 static DisasJumpType
translate_one(CPUS390XState
*env
, DisasContext
*s
)
6290 const DisasInsn
*insn
;
6291 DisasJumpType ret
= DISAS_NEXT
;
6293 bool icount
= false;
6295 /* Search for the insn in the table. */
6296 insn
= extract_insn(env
, s
);
6298 /* Update insn_start now that we know the ILEN. */
6299 tcg_set_insn_start_param(s
->insn_start
, 2, s
->ilen
);
6301 /* Not found means unimplemented/illegal opcode. */
6303 qemu_log_mask(LOG_UNIMP
, "unimplemented opcode 0x%02x%02x\n",
6304 s
->fields
.op
, s
->fields
.op2
);
6305 gen_illegal_opcode(s
);
6306 ret
= DISAS_NORETURN
;
6310 #ifndef CONFIG_USER_ONLY
6311 if (s
->base
.tb
->flags
& FLAG_MASK_PER
) {
6312 TCGv_i64 addr
= tcg_constant_i64(s
->base
.pc_next
);
6313 gen_helper_per_ifetch(cpu_env
, addr
);
6319 /* privileged instruction */
6320 if ((s
->base
.tb
->flags
& FLAG_MASK_PSTATE
) && (insn
->flags
& IF_PRIV
)) {
6321 gen_program_exception(s
, PGM_PRIVILEGED
);
6322 ret
= DISAS_NORETURN
;
6326 /* if AFP is not enabled, instructions and registers are forbidden */
6327 if (!(s
->base
.tb
->flags
& FLAG_MASK_AFP
)) {
6330 if ((insn
->flags
& IF_AFP1
) && is_afp_reg(get_field(s
, r1
))) {
6333 if ((insn
->flags
& IF_AFP2
) && is_afp_reg(get_field(s
, r2
))) {
6336 if ((insn
->flags
& IF_AFP3
) && is_afp_reg(get_field(s
, r3
))) {
6339 if (insn
->flags
& IF_BFP
) {
6342 if (insn
->flags
& IF_DFP
) {
6345 if (insn
->flags
& IF_VEC
) {
6349 gen_data_exception(dxc
);
6350 ret
= DISAS_NORETURN
;
6355 /* if vector instructions not enabled, executing them is forbidden */
6356 if (insn
->flags
& IF_VEC
) {
6357 if (!((s
->base
.tb
->flags
& FLAG_MASK_VECTOR
))) {
6358 gen_data_exception(0xfe);
6359 ret
= DISAS_NORETURN
;
6364 /* input/output is the special case for icount mode */
6365 if (unlikely(insn
->flags
& IF_IO
)) {
6366 icount
= translator_io_start(&s
->base
);
6370 /* Check for insn specification exceptions. */
6372 if ((insn
->spec
& SPEC_r1_even
&& get_field(s
, r1
) & 1) ||
6373 (insn
->spec
& SPEC_r2_even
&& get_field(s
, r2
) & 1) ||
6374 (insn
->spec
& SPEC_r3_even
&& get_field(s
, r3
) & 1) ||
6375 (insn
->spec
& SPEC_r1_f128
&& !is_fp_pair(get_field(s
, r1
))) ||
6376 (insn
->spec
& SPEC_r2_f128
&& !is_fp_pair(get_field(s
, r2
)))) {
6377 gen_program_exception(s
, PGM_SPECIFICATION
);
6378 ret
= DISAS_NORETURN
;
6383 /* Implement the instruction. */
6384 if (insn
->help_in1
) {
6385 insn
->help_in1(s
, &o
);
6387 if (insn
->help_in2
) {
6388 insn
->help_in2(s
, &o
);
6390 if (insn
->help_prep
) {
6391 insn
->help_prep(s
, &o
);
6393 if (insn
->help_op
) {
6394 ret
= insn
->help_op(s
, &o
);
6396 if (ret
!= DISAS_NORETURN
) {
6397 if (insn
->help_wout
) {
6398 insn
->help_wout(s
, &o
);
6400 if (insn
->help_cout
) {
6401 insn
->help_cout(s
, &o
);
6405 /* io should be the last instruction in tb when icount is enabled */
6406 if (unlikely(icount
&& ret
== DISAS_NEXT
)) {
6407 ret
= DISAS_TOO_MANY
;
6410 #ifndef CONFIG_USER_ONLY
6411 if (s
->base
.tb
->flags
& FLAG_MASK_PER
) {
6412 /* An exception might be triggered, save PSW if not already done. */
6413 if (ret
== DISAS_NEXT
|| ret
== DISAS_TOO_MANY
) {
6414 tcg_gen_movi_i64(psw_addr
, s
->pc_tmp
);
6417 /* Call the helper to check for a possible PER exception. */
6418 gen_helper_per_check_exception(cpu_env
);
6423 /* Advance to the next instruction. */
6424 s
->base
.pc_next
= s
->pc_tmp
;
6428 static void s390x_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
6430 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6433 if (!(dc
->base
.tb
->flags
& FLAG_MASK_64
)) {
6434 dc
->base
.pc_first
&= 0x7fffffff;
6435 dc
->base
.pc_next
= dc
->base
.pc_first
;
6438 dc
->cc_op
= CC_OP_DYNAMIC
;
6439 dc
->ex_value
= dc
->base
.tb
->cs_base
;
6440 dc
->exit_to_mainloop
= (dc
->base
.tb
->flags
& FLAG_MASK_PER
) || dc
->ex_value
;
6443 static void s390x_tr_tb_start(DisasContextBase
*db
, CPUState
*cs
)
6447 static void s390x_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cs
)
6449 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6451 /* Delay the set of ilen until we've read the insn. */
6452 tcg_gen_insn_start(dc
->base
.pc_next
, dc
->cc_op
, 0);
6453 dc
->insn_start
= tcg_last_op();
6456 static target_ulong
get_next_pc(CPUS390XState
*env
, DisasContext
*s
,
6459 uint64_t insn
= cpu_lduw_code(env
, pc
);
6461 return pc
+ get_ilen((insn
>> 8) & 0xff);
6464 static void s390x_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cs
)
6466 CPUS390XState
*env
= cs
->env_ptr
;
6467 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6469 dc
->base
.is_jmp
= translate_one(env
, dc
);
6470 if (dc
->base
.is_jmp
== DISAS_NEXT
) {
6472 !is_same_page(dcbase
, dc
->base
.pc_next
) ||
6473 !is_same_page(dcbase
, get_next_pc(env
, dc
, dc
->base
.pc_next
))) {
6474 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
6479 static void s390x_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cs
)
6481 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6483 switch (dc
->base
.is_jmp
) {
6484 case DISAS_NORETURN
:
6486 case DISAS_TOO_MANY
:
6487 update_psw_addr(dc
);
6489 case DISAS_PC_UPDATED
:
6490 /* Next TB starts off with CC_OP_DYNAMIC, so make sure the
6491 cc op type is in env */
6494 case DISAS_PC_CC_UPDATED
:
6495 /* Exit the TB, either by raising a debug exception or by return. */
6496 if (dc
->exit_to_mainloop
) {
6497 tcg_gen_exit_tb(NULL
, 0);
6499 tcg_gen_lookup_and_goto_ptr();
6503 g_assert_not_reached();
6507 static void s390x_tr_disas_log(const DisasContextBase
*dcbase
,
6508 CPUState
*cs
, FILE *logfile
)
6510 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
6512 if (unlikely(dc
->ex_value
)) {
6513 /* ??? Unfortunately target_disas can't use host memory. */
6514 fprintf(logfile
, "IN: EXECUTE %016" PRIx64
, dc
->ex_value
);
6516 fprintf(logfile
, "IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
6517 target_disas(logfile
, cs
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
6521 static const TranslatorOps s390x_tr_ops
= {
6522 .init_disas_context
= s390x_tr_init_disas_context
,
6523 .tb_start
= s390x_tr_tb_start
,
6524 .insn_start
= s390x_tr_insn_start
,
6525 .translate_insn
= s390x_tr_translate_insn
,
6526 .tb_stop
= s390x_tr_tb_stop
,
6527 .disas_log
= s390x_tr_disas_log
,
6530 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int *max_insns
,
6531 target_ulong pc
, void *host_pc
)
6535 translator_loop(cs
, tb
, max_insns
, pc
, host_pc
, &s390x_tr_ops
, &dc
.base
);
6538 void s390x_restore_state_to_opc(CPUState
*cs
,
6539 const TranslationBlock
*tb
,
6540 const uint64_t *data
)
6542 S390CPU
*cpu
= S390_CPU(cs
);
6543 CPUS390XState
*env
= &cpu
->env
;
6544 int cc_op
= data
[1];
6546 env
->psw
.addr
= data
[0];
6548 /* Update the CC opcode if it is not already up-to-date. */
6549 if ((cc_op
!= CC_OP_DYNAMIC
) && (cc_op
!= CC_OP_STATIC
)) {
6554 env
->int_pgm_ilen
= data
[2];