hw/block/pflash_cfi: Fix code style for checkpatch.pl
[qemu/ar7.git] / hw / block / pflash_cfi02.c
blobfa981465e127feaab2af594119b758c641babd29
1 /*
2 * CFI parallel flash with AMD command set emulation
4 * Copyright (c) 2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
22 * Supported commands/modes are:
23 * - flash read
24 * - flash write
25 * - flash ID read
26 * - sector erase
27 * - chip erase
28 * - unlock bypass command
29 * - CFI queries
31 * It does not support flash interleaving.
32 * It does not implement software data protection as found in many real chips
35 #include "qemu/osdep.h"
36 #include "hw/block/block.h"
37 #include "hw/block/flash.h"
38 #include "hw/qdev-properties.h"
39 #include "hw/qdev-properties-system.h"
40 #include "qapi/error.h"
41 #include "qemu/error-report.h"
42 #include "qemu/bitmap.h"
43 #include "qemu/timer.h"
44 #include "sysemu/block-backend.h"
45 #include "qemu/host-utils.h"
46 #include "qemu/module.h"
47 #include "hw/sysbus.h"
48 #include "migration/vmstate.h"
49 #include "trace.h"
51 #define PFLASH_DEBUG false
52 #define DPRINTF(fmt, ...) \
53 do { \
54 if (PFLASH_DEBUG) { \
55 fprintf(stderr, "PFLASH: " fmt, ## __VA_ARGS__); \
56 } \
57 } while (0)
59 #define PFLASH_LAZY_ROMD_THRESHOLD 42
62 * The size of the cfi_table indirectly depends on this and the start of the
63 * PRI table directly depends on it. 4 is the maximum size (and also what
64 * seems common) without changing the PRT table address.
66 #define PFLASH_MAX_ERASE_REGIONS 4
68 /* Special write cycles for CFI queries. */
69 enum {
70 WCYCLE_CFI = 7,
71 WCYCLE_AUTOSELECT_CFI = 8,
74 struct PFlashCFI02 {
75 /*< private >*/
76 SysBusDevice parent_obj;
77 /*< public >*/
79 BlockBackend *blk;
80 uint32_t uniform_nb_blocs;
81 uint32_t uniform_sector_len;
82 uint32_t total_sectors;
83 uint32_t nb_blocs[PFLASH_MAX_ERASE_REGIONS];
84 uint32_t sector_len[PFLASH_MAX_ERASE_REGIONS];
85 uint32_t chip_len;
86 uint8_t mappings;
87 uint8_t width;
88 uint8_t be;
89 int wcycle; /* if 0, the flash is read normally */
90 int bypass;
91 int ro;
92 uint8_t cmd;
93 uint8_t status;
94 /* FIXME: implement array device properties */
95 uint16_t ident0;
96 uint16_t ident1;
97 uint16_t ident2;
98 uint16_t ident3;
99 uint16_t unlock_addr0;
100 uint16_t unlock_addr1;
101 uint8_t cfi_table[0x4d];
102 QEMUTimer timer;
104 * The device replicates the flash memory across its memory space. Emulate
105 * that by having a container (.mem) filled with an array of aliases
106 * (.mem_mappings) pointing to the flash memory (.orig_mem).
108 MemoryRegion mem;
109 MemoryRegion *mem_mappings; /* array; one per mapping */
110 MemoryRegion orig_mem;
111 int rom_mode;
112 int read_counter; /* used for lazy switch-back to rom mode */
113 int sectors_to_erase;
114 uint64_t erase_time_remaining;
115 unsigned long *sector_erase_map;
116 char *name;
117 void *storage;
121 * Toggle status bit DQ7.
123 static inline void toggle_dq7(PFlashCFI02 *pfl)
125 pfl->status ^= 0x80;
129 * Set status bit DQ7 to bit 7 of value.
131 static inline void set_dq7(PFlashCFI02 *pfl, uint8_t value)
133 pfl->status &= 0x7F;
134 pfl->status |= value & 0x80;
138 * Toggle status bit DQ6.
140 static inline void toggle_dq6(PFlashCFI02 *pfl)
142 pfl->status ^= 0x40;
146 * Turn on DQ3.
148 static inline void assert_dq3(PFlashCFI02 *pfl)
150 pfl->status |= 0x08;
154 * Turn off DQ3.
156 static inline void reset_dq3(PFlashCFI02 *pfl)
158 pfl->status &= ~0x08;
162 * Toggle status bit DQ2.
164 static inline void toggle_dq2(PFlashCFI02 *pfl)
166 pfl->status ^= 0x04;
170 * Set up replicated mappings of the same region.
172 static void pflash_setup_mappings(PFlashCFI02 *pfl)
174 unsigned i;
175 hwaddr size = memory_region_size(&pfl->orig_mem);
177 memory_region_init(&pfl->mem, OBJECT(pfl), "pflash", pfl->mappings * size);
178 pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings);
179 for (i = 0; i < pfl->mappings; ++i) {
180 memory_region_init_alias(&pfl->mem_mappings[i], OBJECT(pfl),
181 "pflash-alias", &pfl->orig_mem, 0, size);
182 memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]);
186 static void pflash_register_memory(PFlashCFI02 *pfl, int rom_mode)
188 memory_region_rom_device_set_romd(&pfl->orig_mem, rom_mode);
189 pfl->rom_mode = rom_mode;
192 static size_t pflash_regions_count(PFlashCFI02 *pfl)
194 return pfl->cfi_table[0x2c];
198 * Returns the time it takes to erase the number of sectors scheduled for
199 * erasure based on CFI address 0x21 which is "Typical timeout per individual
200 * block erase 2^N ms."
202 static uint64_t pflash_erase_time(PFlashCFI02 *pfl)
205 * If there are no sectors to erase (which can happen if all of the sectors
206 * to be erased are protected), then erase takes 100 us. Protected sectors
207 * aren't supported so this should never happen.
209 return ((1ULL << pfl->cfi_table[0x21]) * pfl->sectors_to_erase) * SCALE_US;
213 * Returns true if the device is currently in erase suspend mode.
215 static inline bool pflash_erase_suspend_mode(PFlashCFI02 *pfl)
217 return pfl->erase_time_remaining > 0;
220 static void pflash_timer(void *opaque)
222 PFlashCFI02 *pfl = opaque;
224 trace_pflash_timer_expired(pfl->cmd);
225 if (pfl->cmd == 0x30) {
227 * Sector erase. If DQ3 is 0 when the timer expires, then the 50
228 * us erase timeout has expired so we need to start the timer for the
229 * sector erase algorithm. Otherwise, the erase completed and we should
230 * go back to read array mode.
232 if ((pfl->status & 0x08) == 0) {
233 assert_dq3(pfl);
234 uint64_t timeout = pflash_erase_time(pfl);
235 timer_mod(&pfl->timer,
236 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout);
237 DPRINTF("%s: erase timeout fired; erasing %d sectors\n",
238 __func__, pfl->sectors_to_erase);
239 return;
241 DPRINTF("%s: sector erase complete\n", __func__);
242 bitmap_zero(pfl->sector_erase_map, pfl->total_sectors);
243 pfl->sectors_to_erase = 0;
244 reset_dq3(pfl);
247 /* Reset flash */
248 toggle_dq7(pfl);
249 if (pfl->bypass) {
250 pfl->wcycle = 2;
251 } else {
252 pflash_register_memory(pfl, 1);
253 pfl->wcycle = 0;
255 pfl->cmd = 0;
259 * Read data from flash.
261 static uint64_t pflash_data_read(PFlashCFI02 *pfl, hwaddr offset,
262 unsigned int width)
264 uint8_t *p = (uint8_t *)pfl->storage + offset;
265 uint64_t ret = pfl->be ? ldn_be_p(p, width) : ldn_le_p(p, width);
266 trace_pflash_data_read(offset, width, ret);
267 return ret;
270 typedef struct {
271 uint32_t len;
272 uint32_t num;
273 } SectorInfo;
276 * offset should be a byte offset of the QEMU device and _not_ a device
277 * offset.
279 static SectorInfo pflash_sector_info(PFlashCFI02 *pfl, hwaddr offset)
281 assert(offset < pfl->chip_len);
282 hwaddr addr = 0;
283 uint32_t sector_num = 0;
284 for (int i = 0; i < pflash_regions_count(pfl); ++i) {
285 uint64_t region_size = (uint64_t)pfl->nb_blocs[i] * pfl->sector_len[i];
286 if (addr <= offset && offset < addr + region_size) {
287 return (SectorInfo) {
288 .len = pfl->sector_len[i],
289 .num = sector_num + (offset - addr) / pfl->sector_len[i],
292 sector_num += pfl->nb_blocs[i];
293 addr += region_size;
295 abort();
299 * Returns true if the offset refers to a flash sector that is currently being
300 * erased.
302 static bool pflash_sector_is_erasing(PFlashCFI02 *pfl, hwaddr offset)
304 long sector_num = pflash_sector_info(pfl, offset).num;
305 return test_bit(sector_num, pfl->sector_erase_map);
308 static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int width)
310 PFlashCFI02 *pfl = opaque;
311 hwaddr boff;
312 uint64_t ret;
314 /* Lazy reset to ROMD mode after a certain amount of read accesses */
315 if (!pfl->rom_mode && pfl->wcycle == 0 &&
316 ++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) {
317 pflash_register_memory(pfl, 1);
319 offset &= pfl->chip_len - 1;
320 boff = offset & 0xFF;
321 if (pfl->width == 2) {
322 boff = boff >> 1;
323 } else if (pfl->width == 4) {
324 boff = boff >> 2;
326 switch (pfl->cmd) {
327 default:
328 /* This should never happen : reset state & treat it as a read*/
329 DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
330 pfl->wcycle = 0;
331 pfl->cmd = 0;
332 /* fall through to the read code */
333 case 0x80: /* Erase (unlock) */
334 /* We accept reads during second unlock sequence... */
335 case 0x00:
336 if (pflash_erase_suspend_mode(pfl) &&
337 pflash_sector_is_erasing(pfl, offset)) {
338 /* Toggle bit 2, but not 6. */
339 toggle_dq2(pfl);
340 /* Status register read */
341 ret = pfl->status;
342 DPRINTF("%s: status %" PRIx64 "\n", __func__, ret);
343 break;
345 /* Flash area read */
346 ret = pflash_data_read(pfl, offset, width);
347 break;
348 case 0x90: /* flash ID read */
349 switch (boff) {
350 case 0x00:
351 case 0x01:
352 ret = boff & 0x01 ? pfl->ident1 : pfl->ident0;
353 break;
354 case 0x02:
355 ret = 0x00; /* Pretend all sectors are unprotected */
356 break;
357 case 0x0E:
358 case 0x0F:
359 ret = boff & 0x01 ? pfl->ident3 : pfl->ident2;
360 if (ret != (uint8_t)-1) {
361 break;
363 /* Fall through to data read. */
364 default:
365 ret = pflash_data_read(pfl, offset, width);
367 DPRINTF("%s: ID " TARGET_FMT_plx " %" PRIx64 "\n", __func__, boff, ret);
368 break;
369 case 0x10: /* Chip Erase */
370 case 0x30: /* Sector Erase */
371 /* Toggle bit 2 during erase, but not program. */
372 toggle_dq2(pfl);
373 /* fall through */
374 case 0xA0: /* Program */
375 /* Toggle bit 6 */
376 toggle_dq6(pfl);
377 /* Status register read */
378 ret = pfl->status;
379 DPRINTF("%s: status %" PRIx64 "\n", __func__, ret);
380 break;
381 case 0x98:
382 /* CFI query mode */
383 if (boff < sizeof(pfl->cfi_table)) {
384 ret = pfl->cfi_table[boff];
385 } else {
386 ret = 0;
388 break;
390 trace_pflash_io_read(offset, width, ret, pfl->cmd, pfl->wcycle);
392 return ret;
395 /* update flash content on disk */
396 static void pflash_update(PFlashCFI02 *pfl, int offset, int size)
398 int offset_end;
399 int ret;
400 if (pfl->blk) {
401 offset_end = offset + size;
402 /* widen to sector boundaries */
403 offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE);
404 offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE);
405 ret = blk_pwrite(pfl->blk, offset, pfl->storage + offset,
406 offset_end - offset, 0);
407 if (ret < 0) {
408 /* TODO set error bit in status */
409 error_report("Could not update PFLASH: %s", strerror(-ret));
414 static void pflash_sector_erase(PFlashCFI02 *pfl, hwaddr offset)
416 SectorInfo sector_info = pflash_sector_info(pfl, offset);
417 uint64_t sector_len = sector_info.len;
418 offset &= ~(sector_len - 1);
419 DPRINTF("%s: start sector erase at %0*" PRIx64 "-%0*" PRIx64 "\n",
420 __func__, pfl->width * 2, offset,
421 pfl->width * 2, offset + sector_len - 1);
422 if (!pfl->ro) {
423 uint8_t *p = pfl->storage;
424 memset(p + offset, 0xff, sector_len);
425 pflash_update(pfl, offset, sector_len);
427 set_dq7(pfl, 0x00);
428 ++pfl->sectors_to_erase;
429 set_bit(sector_info.num, pfl->sector_erase_map);
430 /* Set (or reset) the 50 us timer for additional erase commands. */
431 timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 50000);
434 static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
435 unsigned int width)
437 PFlashCFI02 *pfl = opaque;
438 hwaddr boff;
439 uint8_t *p;
440 uint8_t cmd;
442 trace_pflash_io_write(offset, width, value, pfl->wcycle);
443 cmd = value;
444 if (pfl->cmd != 0xA0) {
445 /* Reset does nothing during chip erase and sector erase. */
446 if (cmd == 0xF0 && pfl->cmd != 0x10 && pfl->cmd != 0x30) {
447 if (pfl->wcycle == WCYCLE_AUTOSELECT_CFI) {
448 /* Return to autoselect mode. */
449 pfl->wcycle = 3;
450 pfl->cmd = 0x90;
451 return;
453 goto reset_flash;
456 offset &= pfl->chip_len - 1;
458 boff = offset;
459 if (pfl->width == 2) {
460 boff = boff >> 1;
461 } else if (pfl->width == 4) {
462 boff = boff >> 2;
464 /* Only the least-significant 11 bits are used in most cases. */
465 boff &= 0x7FF;
466 switch (pfl->wcycle) {
467 case 0:
468 /* Set the device in I/O access mode if required */
469 if (pfl->rom_mode)
470 pflash_register_memory(pfl, 0);
471 pfl->read_counter = 0;
472 /* We're in read mode */
473 check_unlock0:
474 if (boff == 0x55 && cmd == 0x98) {
475 /* Enter CFI query mode */
476 pfl->wcycle = WCYCLE_CFI;
477 pfl->cmd = 0x98;
478 return;
480 /* Handle erase resume in erase suspend mode, otherwise reset. */
481 if (cmd == 0x30) { /* Erase Resume */
482 if (pflash_erase_suspend_mode(pfl)) {
483 /* Resume the erase. */
484 timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
485 pfl->erase_time_remaining);
486 pfl->erase_time_remaining = 0;
487 pfl->wcycle = 6;
488 pfl->cmd = 0x30;
489 set_dq7(pfl, 0x00);
490 assert_dq3(pfl);
491 return;
493 goto reset_flash;
495 /* Ignore erase suspend. */
496 if (cmd == 0xB0) { /* Erase Suspend */
497 return;
499 if (boff != pfl->unlock_addr0 || cmd != 0xAA) {
500 DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n",
501 __func__, boff, cmd, pfl->unlock_addr0);
502 goto reset_flash;
504 DPRINTF("%s: unlock sequence started\n", __func__);
505 break;
506 case 1:
507 /* We started an unlock sequence */
508 check_unlock1:
509 if (boff != pfl->unlock_addr1 || cmd != 0x55) {
510 DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__,
511 boff, cmd);
512 goto reset_flash;
514 DPRINTF("%s: unlock sequence done\n", __func__);
515 break;
516 case 2:
517 /* We finished an unlock sequence */
518 if (!pfl->bypass && boff != pfl->unlock_addr0) {
519 DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__,
520 boff, cmd);
521 goto reset_flash;
523 switch (cmd) {
524 case 0x20:
525 pfl->bypass = 1;
526 goto do_bypass;
527 case 0x80: /* Erase */
528 case 0x90: /* Autoselect */
529 case 0xA0: /* Program */
530 pfl->cmd = cmd;
531 DPRINTF("%s: starting command %02x\n", __func__, cmd);
532 break;
533 default:
534 DPRINTF("%s: unknown command %02x\n", __func__, cmd);
535 goto reset_flash;
537 break;
538 case 3:
539 switch (pfl->cmd) {
540 case 0x80: /* Erase */
541 /* We need another unlock sequence */
542 goto check_unlock0;
543 case 0xA0: /* Program */
544 if (pflash_erase_suspend_mode(pfl) &&
545 pflash_sector_is_erasing(pfl, offset)) {
546 /* Ignore writes to erasing sectors. */
547 if (pfl->bypass) {
548 goto do_bypass;
550 goto reset_flash;
552 trace_pflash_data_write(offset, width, value, 0);
553 if (!pfl->ro) {
554 p = (uint8_t *)pfl->storage + offset;
555 if (pfl->be) {
556 uint64_t current = ldn_be_p(p, width);
557 stn_be_p(p, width, current & value);
558 } else {
559 uint64_t current = ldn_le_p(p, width);
560 stn_le_p(p, width, current & value);
562 pflash_update(pfl, offset, width);
565 * While programming, status bit DQ7 should hold the opposite
566 * value from how it was programmed.
568 set_dq7(pfl, ~value);
569 /* Let's pretend write is immediate */
570 if (pfl->bypass)
571 goto do_bypass;
572 goto reset_flash;
573 case 0x90: /* Autoselect */
574 if (pfl->bypass && cmd == 0x00) {
575 /* Unlock bypass reset */
576 goto reset_flash;
579 * We can enter CFI query mode from autoselect mode, but we must
580 * return to autoselect mode after a reset.
582 if (boff == 0x55 && cmd == 0x98) {
583 /* Enter autoselect CFI query mode */
584 pfl->wcycle = WCYCLE_AUTOSELECT_CFI;
585 pfl->cmd = 0x98;
586 return;
588 /* fall through */
589 default:
590 DPRINTF("%s: invalid write for command %02x\n",
591 __func__, pfl->cmd);
592 goto reset_flash;
594 case 4:
595 switch (pfl->cmd) {
596 case 0xA0: /* Program */
597 /* Ignore writes while flash data write is occurring */
598 /* As we suppose write is immediate, this should never happen */
599 return;
600 case 0x80: /* Erase */
601 goto check_unlock1;
602 default:
603 /* Should never happen */
604 DPRINTF("%s: invalid command state %02x (wc 4)\n",
605 __func__, pfl->cmd);
606 goto reset_flash;
608 break;
609 case 5:
610 if (pflash_erase_suspend_mode(pfl)) {
611 /* Erasing is not supported in erase suspend mode. */
612 goto reset_flash;
614 switch (cmd) {
615 case 0x10: /* Chip Erase */
616 if (boff != pfl->unlock_addr0) {
617 DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n",
618 __func__, offset);
619 goto reset_flash;
621 /* Chip erase */
622 DPRINTF("%s: start chip erase\n", __func__);
623 if (!pfl->ro) {
624 memset(pfl->storage, 0xff, pfl->chip_len);
625 pflash_update(pfl, 0, pfl->chip_len);
627 set_dq7(pfl, 0x00);
628 /* Wait the time specified at CFI address 0x22. */
629 timer_mod(&pfl->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
630 (1ULL << pfl->cfi_table[0x22]) * SCALE_MS);
631 break;
632 case 0x30: /* Sector erase */
633 pflash_sector_erase(pfl, offset);
634 break;
635 default:
636 DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
637 goto reset_flash;
639 pfl->cmd = cmd;
640 break;
641 case 6:
642 switch (pfl->cmd) {
643 case 0x10: /* Chip Erase */
644 /* Ignore writes during chip erase */
645 return;
646 case 0x30: /* Sector erase */
647 if (cmd == 0xB0) {
649 * If erase suspend happens during the erase timeout (so DQ3 is
650 * 0), then the device suspends erasing immediately. Set the
651 * remaining time to be the total time to erase. Otherwise,
652 * there is a maximum amount of time it can take to enter
653 * suspend mode. Let's ignore that and suspend immediately and
654 * set the remaining time to the actual time remaining on the
655 * timer.
657 if ((pfl->status & 0x08) == 0) {
658 pfl->erase_time_remaining = pflash_erase_time(pfl);
659 } else {
660 int64_t delta = timer_expire_time_ns(&pfl->timer) -
661 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
662 /* Make sure we have a positive time remaining. */
663 pfl->erase_time_remaining = delta <= 0 ? 1 : delta;
665 reset_dq3(pfl);
666 timer_del(&pfl->timer);
667 pfl->wcycle = 0;
668 pfl->cmd = 0;
669 return;
672 * If DQ3 is 0, additional sector erase commands can be
673 * written and anything else (other than an erase suspend) resets
674 * the device.
676 if ((pfl->status & 0x08) == 0) {
677 if (cmd == 0x30) {
678 pflash_sector_erase(pfl, offset);
679 } else {
680 goto reset_flash;
683 /* Ignore writes during the actual erase. */
684 return;
685 default:
686 /* Should never happen */
687 DPRINTF("%s: invalid command state %02x (wc 6)\n",
688 __func__, pfl->cmd);
689 goto reset_flash;
691 break;
692 /* Special values for CFI queries */
693 case WCYCLE_CFI:
694 case WCYCLE_AUTOSELECT_CFI:
695 DPRINTF("%s: invalid write in CFI query mode\n", __func__);
696 goto reset_flash;
697 default:
698 /* Should never happen */
699 DPRINTF("%s: invalid write state (wc 7)\n", __func__);
700 goto reset_flash;
702 pfl->wcycle++;
704 return;
706 /* Reset flash */
707 reset_flash:
708 trace_pflash_reset();
709 pfl->bypass = 0;
710 pfl->wcycle = 0;
711 pfl->cmd = 0;
712 return;
714 do_bypass:
715 pfl->wcycle = 2;
716 pfl->cmd = 0;
719 static const MemoryRegionOps pflash_cfi02_ops = {
720 .read = pflash_read,
721 .write = pflash_write,
722 .valid.min_access_size = 1,
723 .valid.max_access_size = 4,
724 .endianness = DEVICE_NATIVE_ENDIAN,
727 static void pflash_cfi02_realize(DeviceState *dev, Error **errp)
729 ERRP_GUARD();
730 PFlashCFI02 *pfl = PFLASH_CFI02(dev);
731 int ret;
733 if (pfl->uniform_sector_len == 0 && pfl->sector_len[0] == 0) {
734 error_setg(errp, "attribute \"sector-length\" not specified or zero.");
735 return;
737 if (pfl->uniform_nb_blocs == 0 && pfl->nb_blocs[0] == 0) {
738 error_setg(errp, "attribute \"num-blocks\" not specified or zero.");
739 return;
741 if (pfl->name == NULL) {
742 error_setg(errp, "attribute \"name\" not specified.");
743 return;
746 int nb_regions;
747 pfl->chip_len = 0;
748 pfl->total_sectors = 0;
749 for (nb_regions = 0; nb_regions < PFLASH_MAX_ERASE_REGIONS; ++nb_regions) {
750 if (pfl->nb_blocs[nb_regions] == 0) {
751 break;
753 pfl->total_sectors += pfl->nb_blocs[nb_regions];
754 uint64_t sector_len_per_device = pfl->sector_len[nb_regions];
757 * The size of each flash sector must be a power of 2 and it must be
758 * aligned at the same power of 2.
760 if (sector_len_per_device & 0xff ||
761 sector_len_per_device >= (1 << 24) ||
762 !is_power_of_2(sector_len_per_device))
764 error_setg(errp, "unsupported configuration: "
765 "sector length[%d] per device = %" PRIx64 ".",
766 nb_regions, sector_len_per_device);
767 return;
769 if (pfl->chip_len & (sector_len_per_device - 1)) {
770 error_setg(errp, "unsupported configuration: "
771 "flash region %d not correctly aligned.",
772 nb_regions);
773 return;
776 pfl->chip_len += (uint64_t)pfl->sector_len[nb_regions] *
777 pfl->nb_blocs[nb_regions];
780 uint64_t uniform_len = (uint64_t)pfl->uniform_nb_blocs *
781 pfl->uniform_sector_len;
782 if (nb_regions == 0) {
783 nb_regions = 1;
784 pfl->nb_blocs[0] = pfl->uniform_nb_blocs;
785 pfl->sector_len[0] = pfl->uniform_sector_len;
786 pfl->chip_len = uniform_len;
787 pfl->total_sectors = pfl->uniform_nb_blocs;
788 } else if (uniform_len != 0 && uniform_len != pfl->chip_len) {
789 error_setg(errp, "\"num-blocks\"*\"sector-length\" "
790 "different from \"num-blocks0\"*\'sector-length0\" + ... + "
791 "\"num-blocks3\"*\"sector-length3\"");
792 return;
795 memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl),
796 &pflash_cfi02_ops, pfl, pfl->name,
797 pfl->chip_len, errp);
798 if (*errp) {
799 return;
802 pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem);
804 if (pfl->blk) {
805 uint64_t perm;
806 pfl->ro = !blk_supports_write_perm(pfl->blk);
807 perm = BLK_PERM_CONSISTENT_READ | (pfl->ro ? 0 : BLK_PERM_WRITE);
808 ret = blk_set_perm(pfl->blk, perm, BLK_PERM_ALL, errp);
809 if (ret < 0) {
810 return;
812 } else {
813 pfl->ro = 0;
816 if (pfl->blk) {
817 if (!blk_check_size_and_read_all(pfl->blk, pfl->storage,
818 pfl->chip_len, errp)) {
819 vmstate_unregister_ram(&pfl->orig_mem, DEVICE(pfl));
820 return;
824 /* Only 11 bits are used in the comparison. */
825 pfl->unlock_addr0 &= 0x7FF;
826 pfl->unlock_addr1 &= 0x7FF;
828 /* Allocate memory for a bitmap for sectors being erased. */
829 pfl->sector_erase_map = bitmap_new(pfl->total_sectors);
831 pflash_setup_mappings(pfl);
832 pfl->rom_mode = 1;
833 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem);
835 timer_init_ns(&pfl->timer, QEMU_CLOCK_VIRTUAL, pflash_timer, pfl);
836 pfl->wcycle = 0;
837 pfl->cmd = 0;
838 pfl->status = 0;
840 /* Hardcoded CFI table (mostly from SG29 Spansion flash) */
841 const uint16_t pri_ofs = 0x40;
842 /* Standard "QRY" string */
843 pfl->cfi_table[0x10] = 'Q';
844 pfl->cfi_table[0x11] = 'R';
845 pfl->cfi_table[0x12] = 'Y';
846 /* Command set (AMD/Fujitsu) */
847 pfl->cfi_table[0x13] = 0x02;
848 pfl->cfi_table[0x14] = 0x00;
849 /* Primary extended table address */
850 pfl->cfi_table[0x15] = pri_ofs;
851 pfl->cfi_table[0x16] = pri_ofs >> 8;
852 /* Alternate command set (none) */
853 pfl->cfi_table[0x17] = 0x00;
854 pfl->cfi_table[0x18] = 0x00;
855 /* Alternate extended table (none) */
856 pfl->cfi_table[0x19] = 0x00;
857 pfl->cfi_table[0x1A] = 0x00;
858 /* Vcc min */
859 pfl->cfi_table[0x1B] = 0x27;
860 /* Vcc max */
861 pfl->cfi_table[0x1C] = 0x36;
862 /* Vpp min (no Vpp pin) */
863 pfl->cfi_table[0x1D] = 0x00;
864 /* Vpp max (no Vpp pin) */
865 pfl->cfi_table[0x1E] = 0x00;
866 /* Timeout per single byte/word write (128 ms) */
867 pfl->cfi_table[0x1F] = 0x07;
868 /* Timeout for min size buffer write (NA) */
869 pfl->cfi_table[0x20] = 0x00;
870 /* Typical timeout for block erase (512 ms) */
871 pfl->cfi_table[0x21] = 0x09;
872 /* Typical timeout for full chip erase (4096 ms) */
873 pfl->cfi_table[0x22] = 0x0C;
874 /* Reserved */
875 pfl->cfi_table[0x23] = 0x01;
876 /* Max timeout for buffer write (NA) */
877 pfl->cfi_table[0x24] = 0x00;
878 /* Max timeout for block erase */
879 pfl->cfi_table[0x25] = 0x0A;
880 /* Max timeout for chip erase */
881 pfl->cfi_table[0x26] = 0x0D;
882 /* Device size */
883 pfl->cfi_table[0x27] = ctz32(pfl->chip_len);
884 /* Flash device interface (8 & 16 bits) */
885 pfl->cfi_table[0x28] = 0x02;
886 pfl->cfi_table[0x29] = 0x00;
887 /* Max number of bytes in multi-bytes write */
889 * XXX: disable buffered write as it's not supported
890 * pfl->cfi_table[0x2A] = 0x05;
892 pfl->cfi_table[0x2A] = 0x00;
893 pfl->cfi_table[0x2B] = 0x00;
894 /* Number of erase block regions */
895 pfl->cfi_table[0x2c] = nb_regions;
896 /* Erase block regions */
897 for (int i = 0; i < nb_regions; ++i) {
898 uint32_t sector_len_per_device = pfl->sector_len[i];
899 pfl->cfi_table[0x2d + 4 * i] = pfl->nb_blocs[i] - 1;
900 pfl->cfi_table[0x2e + 4 * i] = (pfl->nb_blocs[i] - 1) >> 8;
901 pfl->cfi_table[0x2f + 4 * i] = sector_len_per_device >> 8;
902 pfl->cfi_table[0x30 + 4 * i] = sector_len_per_device >> 16;
904 assert(0x2c + 4 * nb_regions < pri_ofs);
906 /* Extended */
907 pfl->cfi_table[0x00 + pri_ofs] = 'P';
908 pfl->cfi_table[0x01 + pri_ofs] = 'R';
909 pfl->cfi_table[0x02 + pri_ofs] = 'I';
911 /* Extended version 1.0 */
912 pfl->cfi_table[0x03 + pri_ofs] = '1';
913 pfl->cfi_table[0x04 + pri_ofs] = '0';
915 /* Address sensitive unlock required. */
916 pfl->cfi_table[0x05 + pri_ofs] = 0x00;
917 /* Erase suspend to read/write. */
918 pfl->cfi_table[0x06 + pri_ofs] = 0x02;
919 /* Sector protect not supported. */
920 pfl->cfi_table[0x07 + pri_ofs] = 0x00;
921 /* Temporary sector unprotect not supported. */
922 pfl->cfi_table[0x08 + pri_ofs] = 0x00;
924 /* Sector protect/unprotect scheme. */
925 pfl->cfi_table[0x09 + pri_ofs] = 0x00;
927 /* Simultaneous operation not supported. */
928 pfl->cfi_table[0x0a + pri_ofs] = 0x00;
929 /* Burst mode not supported. */
930 pfl->cfi_table[0x0b + pri_ofs] = 0x00;
931 /* Page mode not supported. */
932 pfl->cfi_table[0x0c + pri_ofs] = 0x00;
933 assert(0x0c + pri_ofs < ARRAY_SIZE(pfl->cfi_table));
936 static Property pflash_cfi02_properties[] = {
937 DEFINE_PROP_DRIVE("drive", PFlashCFI02, blk),
938 DEFINE_PROP_UINT32("num-blocks", PFlashCFI02, uniform_nb_blocs, 0),
939 DEFINE_PROP_UINT32("sector-length", PFlashCFI02, uniform_sector_len, 0),
940 DEFINE_PROP_UINT32("num-blocks0", PFlashCFI02, nb_blocs[0], 0),
941 DEFINE_PROP_UINT32("sector-length0", PFlashCFI02, sector_len[0], 0),
942 DEFINE_PROP_UINT32("num-blocks1", PFlashCFI02, nb_blocs[1], 0),
943 DEFINE_PROP_UINT32("sector-length1", PFlashCFI02, sector_len[1], 0),
944 DEFINE_PROP_UINT32("num-blocks2", PFlashCFI02, nb_blocs[2], 0),
945 DEFINE_PROP_UINT32("sector-length2", PFlashCFI02, sector_len[2], 0),
946 DEFINE_PROP_UINT32("num-blocks3", PFlashCFI02, nb_blocs[3], 0),
947 DEFINE_PROP_UINT32("sector-length3", PFlashCFI02, sector_len[3], 0),
948 DEFINE_PROP_UINT8("width", PFlashCFI02, width, 0),
949 DEFINE_PROP_UINT8("mappings", PFlashCFI02, mappings, 0),
950 DEFINE_PROP_UINT8("big-endian", PFlashCFI02, be, 0),
951 DEFINE_PROP_UINT16("id0", PFlashCFI02, ident0, 0),
952 DEFINE_PROP_UINT16("id1", PFlashCFI02, ident1, 0),
953 DEFINE_PROP_UINT16("id2", PFlashCFI02, ident2, 0),
954 DEFINE_PROP_UINT16("id3", PFlashCFI02, ident3, 0),
955 DEFINE_PROP_UINT16("unlock-addr0", PFlashCFI02, unlock_addr0, 0),
956 DEFINE_PROP_UINT16("unlock-addr1", PFlashCFI02, unlock_addr1, 0),
957 DEFINE_PROP_STRING("name", PFlashCFI02, name),
958 DEFINE_PROP_END_OF_LIST(),
961 static void pflash_cfi02_unrealize(DeviceState *dev)
963 PFlashCFI02 *pfl = PFLASH_CFI02(dev);
964 timer_del(&pfl->timer);
965 g_free(pfl->sector_erase_map);
968 static void pflash_cfi02_class_init(ObjectClass *klass, void *data)
970 DeviceClass *dc = DEVICE_CLASS(klass);
972 dc->realize = pflash_cfi02_realize;
973 dc->unrealize = pflash_cfi02_unrealize;
974 device_class_set_props(dc, pflash_cfi02_properties);
975 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
978 static const TypeInfo pflash_cfi02_info = {
979 .name = TYPE_PFLASH_CFI02,
980 .parent = TYPE_SYS_BUS_DEVICE,
981 .instance_size = sizeof(PFlashCFI02),
982 .class_init = pflash_cfi02_class_init,
985 static void pflash_cfi02_register_types(void)
987 type_register_static(&pflash_cfi02_info);
990 type_init(pflash_cfi02_register_types)
992 PFlashCFI02 *pflash_cfi02_register(hwaddr base,
993 const char *name,
994 hwaddr size,
995 BlockBackend *blk,
996 uint32_t sector_len,
997 int nb_mappings, int width,
998 uint16_t id0, uint16_t id1,
999 uint16_t id2, uint16_t id3,
1000 uint16_t unlock_addr0,
1001 uint16_t unlock_addr1,
1002 int be)
1004 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI02);
1006 if (blk) {
1007 qdev_prop_set_drive(dev, "drive", blk);
1009 assert(QEMU_IS_ALIGNED(size, sector_len));
1010 qdev_prop_set_uint32(dev, "num-blocks", size / sector_len);
1011 qdev_prop_set_uint32(dev, "sector-length", sector_len);
1012 qdev_prop_set_uint8(dev, "width", width);
1013 qdev_prop_set_uint8(dev, "mappings", nb_mappings);
1014 qdev_prop_set_uint8(dev, "big-endian", !!be);
1015 qdev_prop_set_uint16(dev, "id0", id0);
1016 qdev_prop_set_uint16(dev, "id1", id1);
1017 qdev_prop_set_uint16(dev, "id2", id2);
1018 qdev_prop_set_uint16(dev, "id3", id3);
1019 qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0);
1020 qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1);
1021 qdev_prop_set_string(dev, "name", name);
1022 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1024 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1025 return PFLASH_CFI02(dev);