2 * QEMU generic PowerPC hardware System Emulator
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
28 #include "hw/ppc/ppc.h"
29 #include "hw/ppc/ppc_e500.h"
30 #include "qemu/timer.h"
31 #include "sysemu/cpus.h"
33 #include "qemu/main-loop.h"
34 #include "qemu/error-report.h"
35 #include "sysemu/kvm.h"
36 #include "sysemu/runstate.h"
38 #include "migration/vmstate.h"
41 //#define PPC_DEBUG_IRQ
42 //#define PPC_DEBUG_TB
45 # define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
47 # define LOG_IRQ(...) do { } while (0)
52 # define LOG_TB(...) qemu_log(__VA_ARGS__)
54 # define LOG_TB(...) do { } while (0)
57 static void cpu_ppc_tb_stop (CPUPPCState
*env
);
58 static void cpu_ppc_tb_start (CPUPPCState
*env
);
60 void ppc_set_irq(PowerPCCPU
*cpu
, int n_IRQ
, int level
)
62 CPUState
*cs
= CPU(cpu
);
63 CPUPPCState
*env
= &cpu
->env
;
64 unsigned int old_pending
;
67 /* We may already have the BQL if coming from the reset path */
68 if (!qemu_mutex_iothread_locked()) {
70 qemu_mutex_lock_iothread();
73 old_pending
= env
->pending_interrupts
;
76 env
->pending_interrupts
|= 1 << n_IRQ
;
77 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
79 env
->pending_interrupts
&= ~(1 << n_IRQ
);
80 if (env
->pending_interrupts
== 0) {
81 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
85 if (old_pending
!= env
->pending_interrupts
) {
86 kvmppc_set_interrupt(cpu
, n_IRQ
, level
);
90 LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32
91 "req %08x\n", __func__
, env
, n_IRQ
, level
,
92 env
->pending_interrupts
, CPU(cpu
)->interrupt_request
);
95 qemu_mutex_unlock_iothread();
99 /* PowerPC 6xx / 7xx internal IRQ controller */
100 static void ppc6xx_set_irq(void *opaque
, int pin
, int level
)
102 PowerPCCPU
*cpu
= opaque
;
103 CPUPPCState
*env
= &cpu
->env
;
106 LOG_IRQ("%s: env %p pin %d level %d\n", __func__
,
108 cur_level
= (env
->irq_input_state
>> pin
) & 1;
109 /* Don't generate spurious events */
110 if ((cur_level
== 1 && level
== 0) || (cur_level
== 0 && level
!= 0)) {
111 CPUState
*cs
= CPU(cpu
);
114 case PPC6xx_INPUT_TBEN
:
115 /* Level sensitive - active high */
116 LOG_IRQ("%s: %s the time base\n",
117 __func__
, level
? "start" : "stop");
119 cpu_ppc_tb_start(env
);
121 cpu_ppc_tb_stop(env
);
123 case PPC6xx_INPUT_INT
:
124 /* Level sensitive - active high */
125 LOG_IRQ("%s: set the external IRQ state to %d\n",
127 ppc_set_irq(cpu
, PPC_INTERRUPT_EXT
, level
);
129 case PPC6xx_INPUT_SMI
:
130 /* Level sensitive - active high */
131 LOG_IRQ("%s: set the SMI IRQ state to %d\n",
133 ppc_set_irq(cpu
, PPC_INTERRUPT_SMI
, level
);
135 case PPC6xx_INPUT_MCP
:
136 /* Negative edge sensitive */
137 /* XXX: TODO: actual reaction may depends on HID0 status
138 * 603/604/740/750: check HID0[EMCP]
140 if (cur_level
== 1 && level
== 0) {
141 LOG_IRQ("%s: raise machine check state\n",
143 ppc_set_irq(cpu
, PPC_INTERRUPT_MCK
, 1);
146 case PPC6xx_INPUT_CKSTP_IN
:
147 /* Level sensitive - active low */
148 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
149 /* XXX: Note that the only way to restart the CPU is to reset it */
151 LOG_IRQ("%s: stop the CPU\n", __func__
);
155 case PPC6xx_INPUT_HRESET
:
156 /* Level sensitive - active low */
158 LOG_IRQ("%s: reset the CPU\n", __func__
);
159 cpu_interrupt(cs
, CPU_INTERRUPT_RESET
);
162 case PPC6xx_INPUT_SRESET
:
163 LOG_IRQ("%s: set the RESET IRQ state to %d\n",
165 ppc_set_irq(cpu
, PPC_INTERRUPT_RESET
, level
);
168 /* Unknown pin - do nothing */
169 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__
, pin
);
173 env
->irq_input_state
|= 1 << pin
;
175 env
->irq_input_state
&= ~(1 << pin
);
179 void ppc6xx_irq_init(PowerPCCPU
*cpu
)
181 CPUPPCState
*env
= &cpu
->env
;
183 env
->irq_inputs
= (void **)qemu_allocate_irqs(&ppc6xx_set_irq
, cpu
,
187 #if defined(TARGET_PPC64)
188 /* PowerPC 970 internal IRQ controller */
189 static void ppc970_set_irq(void *opaque
, int pin
, int level
)
191 PowerPCCPU
*cpu
= opaque
;
192 CPUPPCState
*env
= &cpu
->env
;
195 LOG_IRQ("%s: env %p pin %d level %d\n", __func__
,
197 cur_level
= (env
->irq_input_state
>> pin
) & 1;
198 /* Don't generate spurious events */
199 if ((cur_level
== 1 && level
== 0) || (cur_level
== 0 && level
!= 0)) {
200 CPUState
*cs
= CPU(cpu
);
203 case PPC970_INPUT_INT
:
204 /* Level sensitive - active high */
205 LOG_IRQ("%s: set the external IRQ state to %d\n",
207 ppc_set_irq(cpu
, PPC_INTERRUPT_EXT
, level
);
209 case PPC970_INPUT_THINT
:
210 /* Level sensitive - active high */
211 LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__
,
213 ppc_set_irq(cpu
, PPC_INTERRUPT_THERM
, level
);
215 case PPC970_INPUT_MCP
:
216 /* Negative edge sensitive */
217 /* XXX: TODO: actual reaction may depends on HID0 status
218 * 603/604/740/750: check HID0[EMCP]
220 if (cur_level
== 1 && level
== 0) {
221 LOG_IRQ("%s: raise machine check state\n",
223 ppc_set_irq(cpu
, PPC_INTERRUPT_MCK
, 1);
226 case PPC970_INPUT_CKSTP
:
227 /* Level sensitive - active low */
228 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
230 LOG_IRQ("%s: stop the CPU\n", __func__
);
233 LOG_IRQ("%s: restart the CPU\n", __func__
);
238 case PPC970_INPUT_HRESET
:
239 /* Level sensitive - active low */
241 cpu_interrupt(cs
, CPU_INTERRUPT_RESET
);
244 case PPC970_INPUT_SRESET
:
245 LOG_IRQ("%s: set the RESET IRQ state to %d\n",
247 ppc_set_irq(cpu
, PPC_INTERRUPT_RESET
, level
);
249 case PPC970_INPUT_TBEN
:
250 LOG_IRQ("%s: set the TBEN state to %d\n", __func__
,
255 /* Unknown pin - do nothing */
256 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__
, pin
);
260 env
->irq_input_state
|= 1 << pin
;
262 env
->irq_input_state
&= ~(1 << pin
);
266 void ppc970_irq_init(PowerPCCPU
*cpu
)
268 CPUPPCState
*env
= &cpu
->env
;
270 env
->irq_inputs
= (void **)qemu_allocate_irqs(&ppc970_set_irq
, cpu
,
274 /* POWER7 internal IRQ controller */
275 static void power7_set_irq(void *opaque
, int pin
, int level
)
277 PowerPCCPU
*cpu
= opaque
;
278 CPUPPCState
*env
= &cpu
->env
;
280 LOG_IRQ("%s: env %p pin %d level %d\n", __func__
,
284 case POWER7_INPUT_INT
:
285 /* Level sensitive - active high */
286 LOG_IRQ("%s: set the external IRQ state to %d\n",
288 ppc_set_irq(cpu
, PPC_INTERRUPT_EXT
, level
);
291 /* Unknown pin - do nothing */
292 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__
, pin
);
296 env
->irq_input_state
|= 1 << pin
;
298 env
->irq_input_state
&= ~(1 << pin
);
302 void ppcPOWER7_irq_init(PowerPCCPU
*cpu
)
304 CPUPPCState
*env
= &cpu
->env
;
306 env
->irq_inputs
= (void **)qemu_allocate_irqs(&power7_set_irq
, cpu
,
310 /* POWER9 internal IRQ controller */
311 static void power9_set_irq(void *opaque
, int pin
, int level
)
313 PowerPCCPU
*cpu
= opaque
;
314 CPUPPCState
*env
= &cpu
->env
;
316 LOG_IRQ("%s: env %p pin %d level %d\n", __func__
,
320 case POWER9_INPUT_INT
:
321 /* Level sensitive - active high */
322 LOG_IRQ("%s: set the external IRQ state to %d\n",
324 ppc_set_irq(cpu
, PPC_INTERRUPT_EXT
, level
);
326 case POWER9_INPUT_HINT
:
327 /* Level sensitive - active high */
328 LOG_IRQ("%s: set the external IRQ state to %d\n",
330 ppc_set_irq(cpu
, PPC_INTERRUPT_HVIRT
, level
);
333 /* Unknown pin - do nothing */
334 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__
, pin
);
338 env
->irq_input_state
|= 1 << pin
;
340 env
->irq_input_state
&= ~(1 << pin
);
344 void ppcPOWER9_irq_init(PowerPCCPU
*cpu
)
346 CPUPPCState
*env
= &cpu
->env
;
348 env
->irq_inputs
= (void **)qemu_allocate_irqs(&power9_set_irq
, cpu
,
351 #endif /* defined(TARGET_PPC64) */
353 void ppc40x_core_reset(PowerPCCPU
*cpu
)
355 CPUPPCState
*env
= &cpu
->env
;
358 qemu_log_mask(CPU_LOG_RESET
, "Reset PowerPC core\n");
359 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_RESET
);
360 dbsr
= env
->spr
[SPR_40x_DBSR
];
363 env
->spr
[SPR_40x_DBSR
] = dbsr
;
366 void ppc40x_chip_reset(PowerPCCPU
*cpu
)
368 CPUPPCState
*env
= &cpu
->env
;
371 qemu_log_mask(CPU_LOG_RESET
, "Reset PowerPC chip\n");
372 cpu_interrupt(CPU(cpu
), CPU_INTERRUPT_RESET
);
373 /* XXX: TODO reset all internal peripherals */
374 dbsr
= env
->spr
[SPR_40x_DBSR
];
377 env
->spr
[SPR_40x_DBSR
] = dbsr
;
380 void ppc40x_system_reset(PowerPCCPU
*cpu
)
382 qemu_log_mask(CPU_LOG_RESET
, "Reset PowerPC system\n");
383 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
386 void store_40x_dbcr0(CPUPPCState
*env
, uint32_t val
)
388 PowerPCCPU
*cpu
= env_archcpu(env
);
390 switch ((val
>> 28) & 0x3) {
396 ppc40x_core_reset(cpu
);
400 ppc40x_chip_reset(cpu
);
404 ppc40x_system_reset(cpu
);
409 /* PowerPC 40x internal IRQ controller */
410 static void ppc40x_set_irq(void *opaque
, int pin
, int level
)
412 PowerPCCPU
*cpu
= opaque
;
413 CPUPPCState
*env
= &cpu
->env
;
416 LOG_IRQ("%s: env %p pin %d level %d\n", __func__
,
418 cur_level
= (env
->irq_input_state
>> pin
) & 1;
419 /* Don't generate spurious events */
420 if ((cur_level
== 1 && level
== 0) || (cur_level
== 0 && level
!= 0)) {
421 CPUState
*cs
= CPU(cpu
);
424 case PPC40x_INPUT_RESET_SYS
:
426 LOG_IRQ("%s: reset the PowerPC system\n",
428 ppc40x_system_reset(cpu
);
431 case PPC40x_INPUT_RESET_CHIP
:
433 LOG_IRQ("%s: reset the PowerPC chip\n", __func__
);
434 ppc40x_chip_reset(cpu
);
437 case PPC40x_INPUT_RESET_CORE
:
438 /* XXX: TODO: update DBSR[MRR] */
440 LOG_IRQ("%s: reset the PowerPC core\n", __func__
);
441 ppc40x_core_reset(cpu
);
444 case PPC40x_INPUT_CINT
:
445 /* Level sensitive - active high */
446 LOG_IRQ("%s: set the critical IRQ state to %d\n",
448 ppc_set_irq(cpu
, PPC_INTERRUPT_CEXT
, level
);
450 case PPC40x_INPUT_INT
:
451 /* Level sensitive - active high */
452 LOG_IRQ("%s: set the external IRQ state to %d\n",
454 ppc_set_irq(cpu
, PPC_INTERRUPT_EXT
, level
);
456 case PPC40x_INPUT_HALT
:
457 /* Level sensitive - active low */
459 LOG_IRQ("%s: stop the CPU\n", __func__
);
462 LOG_IRQ("%s: restart the CPU\n", __func__
);
467 case PPC40x_INPUT_DEBUG
:
468 /* Level sensitive - active high */
469 LOG_IRQ("%s: set the debug pin state to %d\n",
471 ppc_set_irq(cpu
, PPC_INTERRUPT_DEBUG
, level
);
474 /* Unknown pin - do nothing */
475 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__
, pin
);
479 env
->irq_input_state
|= 1 << pin
;
481 env
->irq_input_state
&= ~(1 << pin
);
485 void ppc40x_irq_init(PowerPCCPU
*cpu
)
487 CPUPPCState
*env
= &cpu
->env
;
489 env
->irq_inputs
= (void **)qemu_allocate_irqs(&ppc40x_set_irq
,
490 cpu
, PPC40x_INPUT_NB
);
493 /* PowerPC E500 internal IRQ controller */
494 static void ppce500_set_irq(void *opaque
, int pin
, int level
)
496 PowerPCCPU
*cpu
= opaque
;
497 CPUPPCState
*env
= &cpu
->env
;
500 LOG_IRQ("%s: env %p pin %d level %d\n", __func__
,
502 cur_level
= (env
->irq_input_state
>> pin
) & 1;
503 /* Don't generate spurious events */
504 if ((cur_level
== 1 && level
== 0) || (cur_level
== 0 && level
!= 0)) {
506 case PPCE500_INPUT_MCK
:
508 LOG_IRQ("%s: reset the PowerPC system\n",
510 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
513 case PPCE500_INPUT_RESET_CORE
:
515 LOG_IRQ("%s: reset the PowerPC core\n", __func__
);
516 ppc_set_irq(cpu
, PPC_INTERRUPT_MCK
, level
);
519 case PPCE500_INPUT_CINT
:
520 /* Level sensitive - active high */
521 LOG_IRQ("%s: set the critical IRQ state to %d\n",
523 ppc_set_irq(cpu
, PPC_INTERRUPT_CEXT
, level
);
525 case PPCE500_INPUT_INT
:
526 /* Level sensitive - active high */
527 LOG_IRQ("%s: set the core IRQ state to %d\n",
529 ppc_set_irq(cpu
, PPC_INTERRUPT_EXT
, level
);
531 case PPCE500_INPUT_DEBUG
:
532 /* Level sensitive - active high */
533 LOG_IRQ("%s: set the debug pin state to %d\n",
535 ppc_set_irq(cpu
, PPC_INTERRUPT_DEBUG
, level
);
538 /* Unknown pin - do nothing */
539 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__
, pin
);
543 env
->irq_input_state
|= 1 << pin
;
545 env
->irq_input_state
&= ~(1 << pin
);
549 void ppce500_irq_init(PowerPCCPU
*cpu
)
551 CPUPPCState
*env
= &cpu
->env
;
553 env
->irq_inputs
= (void **)qemu_allocate_irqs(&ppce500_set_irq
,
554 cpu
, PPCE500_INPUT_NB
);
557 /* Enable or Disable the E500 EPR capability */
558 void ppce500_set_mpic_proxy(bool enabled
)
563 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
565 cpu
->env
.mpic_proxy
= enabled
;
567 kvmppc_set_mpic_proxy(cpu
, enabled
);
572 /*****************************************************************************/
573 /* PowerPC time base and decrementer emulation */
575 uint64_t cpu_ppc_get_tb(ppc_tb_t
*tb_env
, uint64_t vmclk
, int64_t tb_offset
)
577 /* TB time in tb periods */
578 return muldiv64(vmclk
, tb_env
->tb_freq
, NANOSECONDS_PER_SECOND
) + tb_offset
;
581 uint64_t cpu_ppc_load_tbl (CPUPPCState
*env
)
583 ppc_tb_t
*tb_env
= env
->tb_env
;
587 return env
->spr
[SPR_TBL
];
590 tb
= cpu_ppc_get_tb(tb_env
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), tb_env
->tb_offset
);
591 LOG_TB("%s: tb %016" PRIx64
"\n", __func__
, tb
);
596 static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState
*env
)
598 ppc_tb_t
*tb_env
= env
->tb_env
;
601 tb
= cpu_ppc_get_tb(tb_env
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), tb_env
->tb_offset
);
602 LOG_TB("%s: tb %016" PRIx64
"\n", __func__
, tb
);
607 uint32_t cpu_ppc_load_tbu (CPUPPCState
*env
)
610 return env
->spr
[SPR_TBU
];
613 return _cpu_ppc_load_tbu(env
);
616 static inline void cpu_ppc_store_tb(ppc_tb_t
*tb_env
, uint64_t vmclk
,
617 int64_t *tb_offsetp
, uint64_t value
)
619 *tb_offsetp
= value
-
620 muldiv64(vmclk
, tb_env
->tb_freq
, NANOSECONDS_PER_SECOND
);
622 LOG_TB("%s: tb %016" PRIx64
" offset %08" PRIx64
"\n",
623 __func__
, value
, *tb_offsetp
);
626 void cpu_ppc_store_tbl (CPUPPCState
*env
, uint32_t value
)
628 ppc_tb_t
*tb_env
= env
->tb_env
;
631 tb
= cpu_ppc_get_tb(tb_env
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), tb_env
->tb_offset
);
632 tb
&= 0xFFFFFFFF00000000ULL
;
633 cpu_ppc_store_tb(tb_env
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
634 &tb_env
->tb_offset
, tb
| (uint64_t)value
);
637 static inline void _cpu_ppc_store_tbu(CPUPPCState
*env
, uint32_t value
)
639 ppc_tb_t
*tb_env
= env
->tb_env
;
642 tb
= cpu_ppc_get_tb(tb_env
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), tb_env
->tb_offset
);
643 tb
&= 0x00000000FFFFFFFFULL
;
644 cpu_ppc_store_tb(tb_env
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
645 &tb_env
->tb_offset
, ((uint64_t)value
<< 32) | tb
);
648 void cpu_ppc_store_tbu (CPUPPCState
*env
, uint32_t value
)
650 _cpu_ppc_store_tbu(env
, value
);
653 uint64_t cpu_ppc_load_atbl (CPUPPCState
*env
)
655 ppc_tb_t
*tb_env
= env
->tb_env
;
658 tb
= cpu_ppc_get_tb(tb_env
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), tb_env
->atb_offset
);
659 LOG_TB("%s: tb %016" PRIx64
"\n", __func__
, tb
);
664 uint32_t cpu_ppc_load_atbu (CPUPPCState
*env
)
666 ppc_tb_t
*tb_env
= env
->tb_env
;
669 tb
= cpu_ppc_get_tb(tb_env
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), tb_env
->atb_offset
);
670 LOG_TB("%s: tb %016" PRIx64
"\n", __func__
, tb
);
675 void cpu_ppc_store_atbl (CPUPPCState
*env
, uint32_t value
)
677 ppc_tb_t
*tb_env
= env
->tb_env
;
680 tb
= cpu_ppc_get_tb(tb_env
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), tb_env
->atb_offset
);
681 tb
&= 0xFFFFFFFF00000000ULL
;
682 cpu_ppc_store_tb(tb_env
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
683 &tb_env
->atb_offset
, tb
| (uint64_t)value
);
686 void cpu_ppc_store_atbu (CPUPPCState
*env
, uint32_t value
)
688 ppc_tb_t
*tb_env
= env
->tb_env
;
691 tb
= cpu_ppc_get_tb(tb_env
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), tb_env
->atb_offset
);
692 tb
&= 0x00000000FFFFFFFFULL
;
693 cpu_ppc_store_tb(tb_env
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
694 &tb_env
->atb_offset
, ((uint64_t)value
<< 32) | tb
);
697 static void cpu_ppc_tb_stop (CPUPPCState
*env
)
699 ppc_tb_t
*tb_env
= env
->tb_env
;
700 uint64_t tb
, atb
, vmclk
;
702 /* If the time base is already frozen, do nothing */
703 if (tb_env
->tb_freq
!= 0) {
704 vmclk
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
705 /* Get the time base */
706 tb
= cpu_ppc_get_tb(tb_env
, vmclk
, tb_env
->tb_offset
);
707 /* Get the alternate time base */
708 atb
= cpu_ppc_get_tb(tb_env
, vmclk
, tb_env
->atb_offset
);
709 /* Store the time base value (ie compute the current offset) */
710 cpu_ppc_store_tb(tb_env
, vmclk
, &tb_env
->tb_offset
, tb
);
711 /* Store the alternate time base value (compute the current offset) */
712 cpu_ppc_store_tb(tb_env
, vmclk
, &tb_env
->atb_offset
, atb
);
713 /* Set the time base frequency to zero */
715 /* Now, the time bases are frozen to tb_offset / atb_offset value */
719 static void cpu_ppc_tb_start (CPUPPCState
*env
)
721 ppc_tb_t
*tb_env
= env
->tb_env
;
722 uint64_t tb
, atb
, vmclk
;
724 /* If the time base is not frozen, do nothing */
725 if (tb_env
->tb_freq
== 0) {
726 vmclk
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
727 /* Get the time base from tb_offset */
728 tb
= tb_env
->tb_offset
;
729 /* Get the alternate time base from atb_offset */
730 atb
= tb_env
->atb_offset
;
731 /* Restore the tb frequency from the decrementer frequency */
732 tb_env
->tb_freq
= tb_env
->decr_freq
;
733 /* Store the time base value */
734 cpu_ppc_store_tb(tb_env
, vmclk
, &tb_env
->tb_offset
, tb
);
735 /* Store the alternate time base value */
736 cpu_ppc_store_tb(tb_env
, vmclk
, &tb_env
->atb_offset
, atb
);
740 bool ppc_decr_clear_on_delivery(CPUPPCState
*env
)
742 ppc_tb_t
*tb_env
= env
->tb_env
;
743 int flags
= PPC_DECR_UNDERFLOW_TRIGGERED
| PPC_DECR_UNDERFLOW_LEVEL
;
744 return ((tb_env
->flags
& flags
) == PPC_DECR_UNDERFLOW_TRIGGERED
);
747 static inline int64_t _cpu_ppc_load_decr(CPUPPCState
*env
, uint64_t next
)
749 ppc_tb_t
*tb_env
= env
->tb_env
;
752 diff
= next
- qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
754 decr
= muldiv64(diff
, tb_env
->decr_freq
, NANOSECONDS_PER_SECOND
);
755 } else if (tb_env
->flags
& PPC_TIMER_BOOKE
) {
758 decr
= -muldiv64(-diff
, tb_env
->decr_freq
, NANOSECONDS_PER_SECOND
);
760 LOG_TB("%s: %016" PRIx64
"\n", __func__
, decr
);
765 target_ulong
cpu_ppc_load_decr(CPUPPCState
*env
)
767 ppc_tb_t
*tb_env
= env
->tb_env
;
771 return env
->spr
[SPR_DECR
];
774 decr
= _cpu_ppc_load_decr(env
, tb_env
->decr_next
);
777 * If large decrementer is enabled then the decrementer is signed extened
778 * to 64 bits, otherwise it is a 32 bit value.
780 if (env
->spr
[SPR_LPCR
] & LPCR_LD
) {
783 return (uint32_t) decr
;
786 target_ulong
cpu_ppc_load_hdecr(CPUPPCState
*env
)
788 PowerPCCPU
*cpu
= env_archcpu(env
);
789 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
790 ppc_tb_t
*tb_env
= env
->tb_env
;
793 hdecr
= _cpu_ppc_load_decr(env
, tb_env
->hdecr_next
);
796 * If we have a large decrementer (POWER9 or later) then hdecr is sign
797 * extended to 64 bits, otherwise it is 32 bits.
799 if (pcc
->lrg_decr_bits
> 32) {
802 return (uint32_t) hdecr
;
805 uint64_t cpu_ppc_load_purr (CPUPPCState
*env
)
807 ppc_tb_t
*tb_env
= env
->tb_env
;
810 diff
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) - tb_env
->purr_start
;
812 return tb_env
->purr_load
+
813 muldiv64(diff
, tb_env
->tb_freq
, NANOSECONDS_PER_SECOND
);
816 /* When decrementer expires,
817 * all we need to do is generate or queue a CPU exception
819 static inline void cpu_ppc_decr_excp(PowerPCCPU
*cpu
)
822 LOG_TB("raise decrementer exception\n");
823 ppc_set_irq(cpu
, PPC_INTERRUPT_DECR
, 1);
826 static inline void cpu_ppc_decr_lower(PowerPCCPU
*cpu
)
828 ppc_set_irq(cpu
, PPC_INTERRUPT_DECR
, 0);
831 static inline void cpu_ppc_hdecr_excp(PowerPCCPU
*cpu
)
833 CPUPPCState
*env
= &cpu
->env
;
836 LOG_TB("raise hv decrementer exception\n");
838 /* The architecture specifies that we don't deliver HDEC
839 * interrupts in a PM state. Not only they don't cause a
840 * wakeup but they also get effectively discarded.
842 if (!env
->resume_as_sreset
) {
843 ppc_set_irq(cpu
, PPC_INTERRUPT_HDECR
, 1);
847 static inline void cpu_ppc_hdecr_lower(PowerPCCPU
*cpu
)
849 ppc_set_irq(cpu
, PPC_INTERRUPT_HDECR
, 0);
852 static void __cpu_ppc_store_decr(PowerPCCPU
*cpu
, uint64_t *nextp
,
854 void (*raise_excp
)(void *),
855 void (*lower_excp
)(PowerPCCPU
*),
856 target_ulong decr
, target_ulong value
,
859 CPUPPCState
*env
= &cpu
->env
;
860 ppc_tb_t
*tb_env
= env
->tb_env
;
864 /* Truncate value to decr_width and sign extend for simplicity */
865 value
&= ((1ULL << nr_bits
) - 1);
866 negative
= !!(value
& (1ULL << (nr_bits
- 1)));
868 value
|= (0xFFFFFFFFULL
<< nr_bits
);
871 LOG_TB("%s: " TARGET_FMT_lx
" => " TARGET_FMT_lx
"\n", __func__
,
875 /* KVM handles decrementer exceptions, we don't need our own timer */
880 * Going from 2 -> 1, 1 -> 0 or 0 -> -1 is the event to generate a DEC
883 * If we get a really small DEC value, we can assume that by the time we
884 * handled it we should inject an interrupt already.
886 * On MSB level based DEC implementations the MSB always means the interrupt
887 * is pending, so raise it on those.
889 * On MSB edge based DEC implementations the MSB going from 0 -> 1 triggers
890 * an edge interrupt, so raise it here too.
893 ((tb_env
->flags
& PPC_DECR_UNDERFLOW_LEVEL
) && negative
) ||
894 ((tb_env
->flags
& PPC_DECR_UNDERFLOW_TRIGGERED
) && negative
895 && !(decr
& (1ULL << (nr_bits
- 1))))) {
900 /* On MSB level based systems a 0 for the MSB stops interrupt delivery */
901 if (!negative
&& (tb_env
->flags
& PPC_DECR_UNDERFLOW_LEVEL
)) {
905 /* Calculate the next timer event */
906 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
907 next
= now
+ muldiv64(value
, NANOSECONDS_PER_SECOND
, tb_env
->decr_freq
);
911 timer_mod(timer
, next
);
914 static inline void _cpu_ppc_store_decr(PowerPCCPU
*cpu
, target_ulong decr
,
915 target_ulong value
, int nr_bits
)
917 ppc_tb_t
*tb_env
= cpu
->env
.tb_env
;
919 __cpu_ppc_store_decr(cpu
, &tb_env
->decr_next
, tb_env
->decr_timer
,
920 tb_env
->decr_timer
->cb
, &cpu_ppc_decr_lower
, decr
,
924 void cpu_ppc_store_decr(CPUPPCState
*env
, target_ulong value
)
926 PowerPCCPU
*cpu
= env_archcpu(env
);
927 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
930 if (env
->spr
[SPR_LPCR
] & LPCR_LD
) {
931 nr_bits
= pcc
->lrg_decr_bits
;
934 _cpu_ppc_store_decr(cpu
, cpu_ppc_load_decr(env
), value
, nr_bits
);
937 static void cpu_ppc_decr_cb(void *opaque
)
939 PowerPCCPU
*cpu
= opaque
;
941 cpu_ppc_decr_excp(cpu
);
944 static inline void _cpu_ppc_store_hdecr(PowerPCCPU
*cpu
, target_ulong hdecr
,
945 target_ulong value
, int nr_bits
)
947 ppc_tb_t
*tb_env
= cpu
->env
.tb_env
;
949 if (tb_env
->hdecr_timer
!= NULL
) {
950 __cpu_ppc_store_decr(cpu
, &tb_env
->hdecr_next
, tb_env
->hdecr_timer
,
951 tb_env
->hdecr_timer
->cb
, &cpu_ppc_hdecr_lower
,
952 hdecr
, value
, nr_bits
);
956 void cpu_ppc_store_hdecr(CPUPPCState
*env
, target_ulong value
)
958 PowerPCCPU
*cpu
= env_archcpu(env
);
959 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
961 _cpu_ppc_store_hdecr(cpu
, cpu_ppc_load_hdecr(env
), value
,
965 static void cpu_ppc_hdecr_cb(void *opaque
)
967 PowerPCCPU
*cpu
= opaque
;
969 cpu_ppc_hdecr_excp(cpu
);
972 static void cpu_ppc_store_purr(PowerPCCPU
*cpu
, uint64_t value
)
974 ppc_tb_t
*tb_env
= cpu
->env
.tb_env
;
976 tb_env
->purr_load
= value
;
977 tb_env
->purr_start
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
980 static void cpu_ppc_set_tb_clk (void *opaque
, uint32_t freq
)
982 CPUPPCState
*env
= opaque
;
983 PowerPCCPU
*cpu
= env_archcpu(env
);
984 ppc_tb_t
*tb_env
= env
->tb_env
;
986 tb_env
->tb_freq
= freq
;
987 tb_env
->decr_freq
= freq
;
988 /* There is a bug in Linux 2.4 kernels:
989 * if a decrementer exception is pending when it enables msr_ee at startup,
990 * it's not ready to handle it...
992 _cpu_ppc_store_decr(cpu
, 0xFFFFFFFF, 0xFFFFFFFF, 32);
993 _cpu_ppc_store_hdecr(cpu
, 0xFFFFFFFF, 0xFFFFFFFF, 32);
994 cpu_ppc_store_purr(cpu
, 0x0000000000000000ULL
);
997 static void timebase_save(PPCTimebase
*tb
)
999 uint64_t ticks
= cpu_get_host_ticks();
1000 PowerPCCPU
*first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1002 if (!first_ppc_cpu
->env
.tb_env
) {
1003 error_report("No timebase object");
1007 /* not used anymore, we keep it for compatibility */
1008 tb
->time_of_the_day_ns
= qemu_clock_get_ns(QEMU_CLOCK_HOST
);
1010 * tb_offset is only expected to be changed by QEMU so
1011 * there is no need to update it from KVM here
1013 tb
->guest_timebase
= ticks
+ first_ppc_cpu
->env
.tb_env
->tb_offset
;
1015 tb
->runstate_paused
= runstate_check(RUN_STATE_PAUSED
);
1018 static void timebase_load(PPCTimebase
*tb
)
1021 PowerPCCPU
*first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1022 int64_t tb_off_adj
, tb_off
;
1025 if (!first_ppc_cpu
->env
.tb_env
) {
1026 error_report("No timebase object");
1030 freq
= first_ppc_cpu
->env
.tb_env
->tb_freq
;
1032 tb_off_adj
= tb
->guest_timebase
- cpu_get_host_ticks();
1034 tb_off
= first_ppc_cpu
->env
.tb_env
->tb_offset
;
1035 trace_ppc_tb_adjust(tb_off
, tb_off_adj
, tb_off_adj
- tb_off
,
1036 (tb_off_adj
- tb_off
) / freq
);
1038 /* Set new offset to all CPUs */
1040 PowerPCCPU
*pcpu
= POWERPC_CPU(cpu
);
1041 pcpu
->env
.tb_env
->tb_offset
= tb_off_adj
;
1042 kvmppc_set_reg_tb_offset(pcpu
, pcpu
->env
.tb_env
->tb_offset
);
1046 void cpu_ppc_clock_vm_state_change(void *opaque
, int running
,
1049 PPCTimebase
*tb
= opaque
;
1059 * When migrating a running guest, read the clock just
1060 * before migration, so that the guest clock counts
1061 * during the events between:
1067 * This reduces clock difference on migration from 5s
1068 * to 0.1s (when max_downtime == 5s), because sending the
1069 * final pages of memory (which happens between vm_stop()
1070 * and pre_save()) takes max_downtime.
1072 static int timebase_pre_save(void *opaque
)
1074 PPCTimebase
*tb
= opaque
;
1076 /* guest_timebase won't be overridden in case of paused guest */
1077 if (!tb
->runstate_paused
) {
1084 const VMStateDescription vmstate_ppc_timebase
= {
1087 .minimum_version_id
= 1,
1088 .minimum_version_id_old
= 1,
1089 .pre_save
= timebase_pre_save
,
1090 .fields
= (VMStateField
[]) {
1091 VMSTATE_UINT64(guest_timebase
, PPCTimebase
),
1092 VMSTATE_INT64(time_of_the_day_ns
, PPCTimebase
),
1093 VMSTATE_END_OF_LIST()
1097 /* Set up (once) timebase frequency (in Hz) */
1098 clk_setup_cb
cpu_ppc_tb_init (CPUPPCState
*env
, uint32_t freq
)
1100 PowerPCCPU
*cpu
= env_archcpu(env
);
1103 tb_env
= g_malloc0(sizeof(ppc_tb_t
));
1104 env
->tb_env
= tb_env
;
1105 tb_env
->flags
= PPC_DECR_UNDERFLOW_TRIGGERED
;
1106 if (is_book3s_arch2x(env
)) {
1107 /* All Book3S 64bit CPUs implement level based DEC logic */
1108 tb_env
->flags
|= PPC_DECR_UNDERFLOW_LEVEL
;
1110 /* Create new timer */
1111 tb_env
->decr_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, &cpu_ppc_decr_cb
, cpu
);
1112 if (env
->has_hv_mode
) {
1113 tb_env
->hdecr_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, &cpu_ppc_hdecr_cb
,
1116 tb_env
->hdecr_timer
= NULL
;
1118 cpu_ppc_set_tb_clk(env
, freq
);
1120 return &cpu_ppc_set_tb_clk
;
1123 /* Specific helpers for POWER & PowerPC 601 RTC */
1124 void cpu_ppc601_store_rtcu (CPUPPCState
*env
, uint32_t value
)
1126 _cpu_ppc_store_tbu(env
, value
);
1129 uint32_t cpu_ppc601_load_rtcu (CPUPPCState
*env
)
1131 return _cpu_ppc_load_tbu(env
);
1134 void cpu_ppc601_store_rtcl (CPUPPCState
*env
, uint32_t value
)
1136 cpu_ppc_store_tbl(env
, value
& 0x3FFFFF80);
1139 uint32_t cpu_ppc601_load_rtcl (CPUPPCState
*env
)
1141 return cpu_ppc_load_tbl(env
) & 0x3FFFFF80;
1144 /*****************************************************************************/
1145 /* PowerPC 40x timers */
1147 /* PIT, FIT & WDT */
1148 typedef struct ppc40x_timer_t ppc40x_timer_t
;
1149 struct ppc40x_timer_t
{
1150 uint64_t pit_reload
; /* PIT auto-reload value */
1151 uint64_t fit_next
; /* Tick for next FIT interrupt */
1152 QEMUTimer
*fit_timer
;
1153 uint64_t wdt_next
; /* Tick for next WDT interrupt */
1154 QEMUTimer
*wdt_timer
;
1156 /* 405 have the PIT, 440 have a DECR. */
1157 unsigned int decr_excp
;
1160 /* Fixed interval timer */
1161 static void cpu_4xx_fit_cb (void *opaque
)
1166 ppc40x_timer_t
*ppc40x_timer
;
1170 cpu
= env_archcpu(env
);
1171 tb_env
= env
->tb_env
;
1172 ppc40x_timer
= tb_env
->opaque
;
1173 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
1174 switch ((env
->spr
[SPR_40x_TCR
] >> 24) & 0x3) {
1188 /* Cannot occur, but makes gcc happy */
1191 next
= now
+ muldiv64(next
, NANOSECONDS_PER_SECOND
, tb_env
->tb_freq
);
1194 timer_mod(ppc40x_timer
->fit_timer
, next
);
1195 env
->spr
[SPR_40x_TSR
] |= 1 << 26;
1196 if ((env
->spr
[SPR_40x_TCR
] >> 23) & 0x1) {
1197 ppc_set_irq(cpu
, PPC_INTERRUPT_FIT
, 1);
1199 LOG_TB("%s: ir %d TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
"\n", __func__
,
1200 (int)((env
->spr
[SPR_40x_TCR
] >> 23) & 0x1),
1201 env
->spr
[SPR_40x_TCR
], env
->spr
[SPR_40x_TSR
]);
1204 /* Programmable interval timer */
1205 static void start_stop_pit (CPUPPCState
*env
, ppc_tb_t
*tb_env
, int is_excp
)
1207 ppc40x_timer_t
*ppc40x_timer
;
1210 ppc40x_timer
= tb_env
->opaque
;
1211 if (ppc40x_timer
->pit_reload
<= 1 ||
1212 !((env
->spr
[SPR_40x_TCR
] >> 26) & 0x1) ||
1213 (is_excp
&& !((env
->spr
[SPR_40x_TCR
] >> 22) & 0x1))) {
1215 LOG_TB("%s: stop PIT\n", __func__
);
1216 timer_del(tb_env
->decr_timer
);
1218 LOG_TB("%s: start PIT %016" PRIx64
"\n",
1219 __func__
, ppc40x_timer
->pit_reload
);
1220 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
1221 next
= now
+ muldiv64(ppc40x_timer
->pit_reload
,
1222 NANOSECONDS_PER_SECOND
, tb_env
->decr_freq
);
1224 next
+= tb_env
->decr_next
- now
;
1227 timer_mod(tb_env
->decr_timer
, next
);
1228 tb_env
->decr_next
= next
;
1232 static void cpu_4xx_pit_cb (void *opaque
)
1237 ppc40x_timer_t
*ppc40x_timer
;
1240 cpu
= env_archcpu(env
);
1241 tb_env
= env
->tb_env
;
1242 ppc40x_timer
= tb_env
->opaque
;
1243 env
->spr
[SPR_40x_TSR
] |= 1 << 27;
1244 if ((env
->spr
[SPR_40x_TCR
] >> 26) & 0x1) {
1245 ppc_set_irq(cpu
, ppc40x_timer
->decr_excp
, 1);
1247 start_stop_pit(env
, tb_env
, 1);
1248 LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
" "
1249 "%016" PRIx64
"\n", __func__
,
1250 (int)((env
->spr
[SPR_40x_TCR
] >> 22) & 0x1),
1251 (int)((env
->spr
[SPR_40x_TCR
] >> 26) & 0x1),
1252 env
->spr
[SPR_40x_TCR
], env
->spr
[SPR_40x_TSR
],
1253 ppc40x_timer
->pit_reload
);
1256 /* Watchdog timer */
1257 static void cpu_4xx_wdt_cb (void *opaque
)
1262 ppc40x_timer_t
*ppc40x_timer
;
1266 cpu
= env_archcpu(env
);
1267 tb_env
= env
->tb_env
;
1268 ppc40x_timer
= tb_env
->opaque
;
1269 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
1270 switch ((env
->spr
[SPR_40x_TCR
] >> 30) & 0x3) {
1284 /* Cannot occur, but makes gcc happy */
1287 next
= now
+ muldiv64(next
, NANOSECONDS_PER_SECOND
, tb_env
->decr_freq
);
1290 LOG_TB("%s: TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
"\n", __func__
,
1291 env
->spr
[SPR_40x_TCR
], env
->spr
[SPR_40x_TSR
]);
1292 switch ((env
->spr
[SPR_40x_TSR
] >> 30) & 0x3) {
1295 timer_mod(ppc40x_timer
->wdt_timer
, next
);
1296 ppc40x_timer
->wdt_next
= next
;
1297 env
->spr
[SPR_40x_TSR
] |= 1U << 31;
1300 timer_mod(ppc40x_timer
->wdt_timer
, next
);
1301 ppc40x_timer
->wdt_next
= next
;
1302 env
->spr
[SPR_40x_TSR
] |= 1 << 30;
1303 if ((env
->spr
[SPR_40x_TCR
] >> 27) & 0x1) {
1304 ppc_set_irq(cpu
, PPC_INTERRUPT_WDT
, 1);
1308 env
->spr
[SPR_40x_TSR
] &= ~0x30000000;
1309 env
->spr
[SPR_40x_TSR
] |= env
->spr
[SPR_40x_TCR
] & 0x30000000;
1310 switch ((env
->spr
[SPR_40x_TCR
] >> 28) & 0x3) {
1314 case 0x1: /* Core reset */
1315 ppc40x_core_reset(cpu
);
1317 case 0x2: /* Chip reset */
1318 ppc40x_chip_reset(cpu
);
1320 case 0x3: /* System reset */
1321 ppc40x_system_reset(cpu
);
1327 void store_40x_pit (CPUPPCState
*env
, target_ulong val
)
1330 ppc40x_timer_t
*ppc40x_timer
;
1332 tb_env
= env
->tb_env
;
1333 ppc40x_timer
= tb_env
->opaque
;
1334 LOG_TB("%s val" TARGET_FMT_lx
"\n", __func__
, val
);
1335 ppc40x_timer
->pit_reload
= val
;
1336 start_stop_pit(env
, tb_env
, 0);
1339 target_ulong
load_40x_pit (CPUPPCState
*env
)
1341 return cpu_ppc_load_decr(env
);
1344 static void ppc_40x_set_tb_clk (void *opaque
, uint32_t freq
)
1346 CPUPPCState
*env
= opaque
;
1347 ppc_tb_t
*tb_env
= env
->tb_env
;
1349 LOG_TB("%s set new frequency to %" PRIu32
"\n", __func__
,
1351 tb_env
->tb_freq
= freq
;
1352 tb_env
->decr_freq
= freq
;
1353 /* XXX: we should also update all timers */
1356 clk_setup_cb
ppc_40x_timers_init (CPUPPCState
*env
, uint32_t freq
,
1357 unsigned int decr_excp
)
1360 ppc40x_timer_t
*ppc40x_timer
;
1362 tb_env
= g_malloc0(sizeof(ppc_tb_t
));
1363 env
->tb_env
= tb_env
;
1364 tb_env
->flags
= PPC_DECR_UNDERFLOW_TRIGGERED
;
1365 ppc40x_timer
= g_malloc0(sizeof(ppc40x_timer_t
));
1366 tb_env
->tb_freq
= freq
;
1367 tb_env
->decr_freq
= freq
;
1368 tb_env
->opaque
= ppc40x_timer
;
1369 LOG_TB("%s freq %" PRIu32
"\n", __func__
, freq
);
1370 if (ppc40x_timer
!= NULL
) {
1371 /* We use decr timer for PIT */
1372 tb_env
->decr_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, &cpu_4xx_pit_cb
, env
);
1373 ppc40x_timer
->fit_timer
=
1374 timer_new_ns(QEMU_CLOCK_VIRTUAL
, &cpu_4xx_fit_cb
, env
);
1375 ppc40x_timer
->wdt_timer
=
1376 timer_new_ns(QEMU_CLOCK_VIRTUAL
, &cpu_4xx_wdt_cb
, env
);
1377 ppc40x_timer
->decr_excp
= decr_excp
;
1380 return &ppc_40x_set_tb_clk
;
1383 /*****************************************************************************/
1384 /* Embedded PowerPC Device Control Registers */
1385 typedef struct ppc_dcrn_t ppc_dcrn_t
;
1387 dcr_read_cb dcr_read
;
1388 dcr_write_cb dcr_write
;
1392 /* XXX: on 460, DCR addresses are 32 bits wide,
1393 * using DCRIPR to get the 22 upper bits of the DCR address
1395 #define DCRN_NB 1024
1397 ppc_dcrn_t dcrn
[DCRN_NB
];
1398 int (*read_error
)(int dcrn
);
1399 int (*write_error
)(int dcrn
);
1402 int ppc_dcr_read (ppc_dcr_t
*dcr_env
, int dcrn
, uint32_t *valp
)
1406 if (dcrn
< 0 || dcrn
>= DCRN_NB
)
1408 dcr
= &dcr_env
->dcrn
[dcrn
];
1409 if (dcr
->dcr_read
== NULL
)
1411 *valp
= (*dcr
->dcr_read
)(dcr
->opaque
, dcrn
);
1416 if (dcr_env
->read_error
!= NULL
)
1417 return (*dcr_env
->read_error
)(dcrn
);
1422 int ppc_dcr_write (ppc_dcr_t
*dcr_env
, int dcrn
, uint32_t val
)
1426 if (dcrn
< 0 || dcrn
>= DCRN_NB
)
1428 dcr
= &dcr_env
->dcrn
[dcrn
];
1429 if (dcr
->dcr_write
== NULL
)
1431 (*dcr
->dcr_write
)(dcr
->opaque
, dcrn
, val
);
1436 if (dcr_env
->write_error
!= NULL
)
1437 return (*dcr_env
->write_error
)(dcrn
);
1442 int ppc_dcr_register (CPUPPCState
*env
, int dcrn
, void *opaque
,
1443 dcr_read_cb dcr_read
, dcr_write_cb dcr_write
)
1448 dcr_env
= env
->dcr_env
;
1449 if (dcr_env
== NULL
)
1451 if (dcrn
< 0 || dcrn
>= DCRN_NB
)
1453 dcr
= &dcr_env
->dcrn
[dcrn
];
1454 if (dcr
->opaque
!= NULL
||
1455 dcr
->dcr_read
!= NULL
||
1456 dcr
->dcr_write
!= NULL
)
1458 dcr
->opaque
= opaque
;
1459 dcr
->dcr_read
= dcr_read
;
1460 dcr
->dcr_write
= dcr_write
;
1465 int ppc_dcr_init (CPUPPCState
*env
, int (*read_error
)(int dcrn
),
1466 int (*write_error
)(int dcrn
))
1470 dcr_env
= g_malloc0(sizeof(ppc_dcr_t
));
1471 dcr_env
->read_error
= read_error
;
1472 dcr_env
->write_error
= write_error
;
1473 env
->dcr_env
= dcr_env
;
1478 /*****************************************************************************/
1480 void PPC_debug_write (void *opaque
, uint32_t addr
, uint32_t val
)
1492 printf("Set loglevel to %04" PRIx32
"\n", val
);
1493 qemu_set_log(val
| 0x100);
1498 PowerPCCPU
*ppc_get_vcpu_by_pir(int pir
)
1503 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1504 CPUPPCState
*env
= &cpu
->env
;
1506 if (env
->spr_cb
[SPR_PIR
].default_value
== pir
) {